Image sensor chip that feeds back voltage and temperature information, and an image processing system having the same

This application is a continuation of U.S. patent application Ser. No. 15/591,626 filed May 10, 2017, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2016-0062995 filed on May 23, 2016, the disclosures of which are incorporated by reference herein in their entireties.

Exemplary embodiments of the present inventive concept relate to an image sensor chip that feeds back voltage and temperature information, and an image processing system having the same.

An image sensor is an integrated circuit having a photoelectric conversion element. A complementary metal-oxide-semiconductor (CMOS) image sensor is a solid-state imaging device using CMOS technology. The CMOS image sensor can be manufactured using a general-purpose semiconductor manufacture apparatus.

In order for the CMOS image sensor to operate, it is supplied with an operation voltage from an external main power management integrated circuit. A performance of the CMOS image sensor may be determined by the operation voltage.

An exemplary embodiment of the present inventive concept provides an image sensor chip, including an internal voltage generator for generating internal voltages using an external voltage received at a first terminal of the image sensor chip, a temperature sensor for generating a temperature voltage, a selection circuit for outputting one of the external voltage, the internal voltages, and the temperature voltage, a digital code generation circuit for generating a digital code using an output voltage of the selection circuit, and a second terminal for outputting the digital code from the image sensor chip.

An exemplary embodiment of the present inventive concept provides an image processing system, including an external voltage supply device, an image sensor chip for receiving an external voltage supplied from the external voltage supply device, and an application processor connected to the image sensor chip and the external voltage supply device. The image sensor chip includes an internal voltage generator for generating internal voltages using the external voltage, a temperature sensor for generating a temperature voltage, a selection circuit for outputting one of the external voltage, the internal voltages, and the temperature voltage, a digital code generation circuit for generating a digital code using an output voltage of the selection circuit, and an output terminal for transmitting the digital code to the application processor.

An exemplary embodiment of the present inventive concept provides an image sensor chip including: a selection circuit configured to output one of a temperature voltage, an internal voltage, and an external voltage; an attenuator configured to attenuate a first output signal of the selection circuit to generate a second output signal; and an analog-to-digital converter configured to generate a feedback signal using the second output signal.

The above and/or other features of the present inventive concept will become apparent by describing in detail exemplary embodiments thereof, with reference to the accompanying drawings in which:

FIG. 1 is a block diagram of an image sensor chip according to an exemplary embodiment of the present inventive concept;

FIG. 2 is a circuit diagram of an attenuator shown in FIG. 1 according to an exemplary embodiment of the present inventive concept;

FIG. 3 is a block diagram of the image sensor chip shown in FIG. 1 according to an exemplary embodiment of the present inventive concept;

FIG. 4 is a block diagram of an image sensor chip according to an exemplary embodiment of the present inventive concept;

FIG. 5 is a block diagram of the image sensor chip shown in FIG. 4 according to an exemplary embodiment of the present inventive concept;

FIG. 6 is a circuit diagram of a voltage information analog-to-digital converter shown in FIGS. 4 and 5 according to an exemplary embodiment of the present inventive concept;

FIG. 7 is a timing diagram for describing an operation of the voltage information analog-to-digital converter shown in FIG. 6 according to an exemplary embodiment of the present inventive concept;

FIG. 8 is a circuit diagram of a first internal voltage generator shown in FIGS. 1, 4, and 12 according to an exemplary embodiment of the present inventive concept;

FIG. 9 is a circuit diagram of the first internal voltage generator shown in FIGS. 1, 4 , and 12 according to an exemplary embodiment of the present inventive concept;

FIG. 10 is a circuit diagram of a second internal voltage generator shown in FIGS. 1, 4 , and 12 according to an exemplary embodiment of the present inventive concept;

FIG. 11 is a circuit diagram of the second internal voltage generator shown in FIGS. 1, 4, and 12 according to an exemplary embodiment of the present inventive concept;

FIG. 12 is a block diagram of an image sensor chip according to an exemplary embodiment of the present inventive concept;

FIG. 13 is a block diagram of the image sensor chip shown in FIG. 12 according to an exemplary embodiment of the present inventive concept;

FIG. 14 is a timing diagram for describing a method of measuring a first internal voltage of the first internal voltage generator shown in FIG. 8 according to an exemplary embodiment of the present inventive concept;

FIG. 15 shows a structure of the voltage information analog-to-digital converter shown in FIGS. 12 and 13 for measuring the first internal voltage of the first internal voltage generator shown in FIG. 8 according to an exemplary embodiment of the present inventive concept;

FIG. 16 is a timing diagram for describing a method of measuring the first internal voltage of the first internal voltage generator shown in FIG. 9 according to an exemplary embodiment of the present inventive concept;

FIG. 17 shows a structure of the voltage information analog-to-digital converter shown in FIGS. 12 and 13 for measuring the first internal voltage of the first internal voltage generator shown in FIG. 9 according to an exemplary embodiment of the present inventive concept;

FIG. 18 is a timing diagram for describing a method of measuring a second internal voltage of the second internal voltage generator shown in FIG. 10 according to an exemplary embodiment of the present inventive concept;

FIG. 19 shows a structure of the voltage information analog-to-digital converter shown in FIGS. 12 and 13 for measuring the second internal voltage of the second internal voltage generator shown in FIG. 10 according to an exemplary embodiment of the present inventive concept;

FIG. 20 is a timing diagram for describing a method of measuring the second internal voltage of the second internal voltage generator shown in FIG. 11 according to an exemplary embodiment of the present inventive concept;

FIG. 21 shows a structure of the voltage information analog-to-digital converter shown in FIGS. 12 and 13 for measuring the second internal voltage of the second internal voltage generator shown in FIG. 11 according to an exemplary embodiment of the present inventive concept;

FIG. 22 is a block diagram of an image processing system including the image sensor chip shown in FIG. 1, 4 , or 12 according to an exemplary embodiment of the present inventive concept; and

FIG. 23 is a block diagram of an image processing system including the image sensor chip shown in FIG. 1, 4 , or 12 according to an exemplary embodiment of the present inventive concepts.

Exemplary embodiments of the present inventive concept will now be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals refer to like elements.

An analog-to-digital converter (ADC) for converting information of a voltage (or an analog voltage signal) into a digital voltage signal ( 250 of FIG. 1, 250A of FIG. 4, and 250B of FIG. 12 ) is referred to herein as a voltage information ADC.

FIG. 1 is a block diagram of an image sensor chip according to an exemplary embodiment of the present inventive concept. Referring to FIG. 1 , an image sensor chip (or image sensor) 200 A may include a plurality of pins (or pads) 201 , 203 , and 205 , an internal voltage generator 210 , a selection circuit 220 , an attenuator 230 , a voltage information ADC 250 , an encoder 255 , a selection signal generator 260 , and a temperature sensor 270 . For example, the components introduced above 210 , 220 , 230 , 250 , 255 , 260 , and 270 may form (or compose) a voltage and temperature monitoring circuit embodied (or integrated) in a portion of the image sensor chip 200 A.

The image sensor chip 200 A may refer to a complementary metal-oxide-semiconductor (CMOS) image sensor chip (CIS) manufactured by a CMOS process, and may be included (installed) in a mobile device. The mobile device may be embodied in a mobile phone, a smart phone, a tablet personal computer (PC), a mobile internet device (MID), an internet of things (IoT) device, an internet of everything (IoE) device, a wearable computer, or a drone. For example, the image sensor chip 200 A may be included in an image sensor module, and the image sensor module may be included in the mobile device.

A first pin 201 may receive a first external voltage VDD 1 supplied from an external voltage supply device (for example, 300 A of FIG. 22 or 300B of FIG. 23 ). A second pin 203 may receive a second external voltage VDD 2 supplied from the external voltage supply device. Although it is shown that the image sensor chip 200 A receives the first external voltage VDD 1 and the second external voltage VDD 2 in FIG. 1 , it is to be understood that the image sensor chip 200 A may receive various external voltages from the external voltage supply device. Further, the external voltage supply device may be included in the image sensor module, for example.

A third pin 205 may transmit feedback information VIF to the external voltage supply device 300 A shown in FIG. 22 or an application processor 400 shown in FIG. 23 . For example, the third pin 205 may refer to at least one of pins for transmitting image data generated in the image sensor chip 200 A or a dedicated pin.

For example, the feedback information VIF may refer to digital signals or a digital code which shows information on an external voltage VDD 1 or VDD 2 supplied from the external voltage supply device, information on an internal voltage VDD 3 or VDD 4 generated by the internal voltage generator 210 , and/or information VTEMP on a temperature of the image sensor chip 200 A when the image sensor chip 200 A operates.

The internal voltage generator 210 may generate various internal voltages VDD 3 and VDD 4 using the first external voltage VDD 1 . For example, the internal voltage generator 210 may be an internal power management IC. The internal voltage generator 210 may include a first internal voltage generator 212 for generating a first internal voltage VDD 3 and a second internal voltage generator 214 for generating a second internal voltage VDD 4 . A structure and an operation of each of the internal voltage generators 212 and 214 will be described in detail referring to FIGS. 8 to 11 .

For example, the first external voltage VDD 1 may be used as an operation voltage of an analog circuit embodied in the image sensor chip 200 A, the second external voltage VDD 2 may be used as an operation voltage of a digital circuit embodied in the image sensor chip 200 A, the first internal voltage VDD 3 may be used to turn on a transmission transistor of each active pixel sensor included in an active pixel sensor array of the image sensor chip 200 A, and the second internal voltage VDD 4 may be used to turn off the transmission transistors. For example, the first internal voltage VDD 3 may be higher than the first external voltage VDD 1 , and the second internal voltage VDD 4 may be a negative voltage lower than a ground voltage GND; however, it is not limited thereto.

The selection circuit 220 may output at least one of a plurality of voltages VDD 1 , VDD 2 , VDD 3 , VDD 4 , and VTEMP as a first output voltage OUT 1 in response to a selection signal SEL. The selection signal SEL may refer to a plurality of signals. For example, the selection circuit 220 may be embodied in a multiplexer. According to an exemplary embodiment of the present inventive concept, the selection circuit 220 may output the ground voltage GND as the first output voltage OUT 1 in response to the selection signal SEL.

The voltage information ADC 250 may convert an analog input signal OUT 2 into a digital output signal VIF, and may express a relative magnitude of the analog input signal OUT 2 with respect to a reference voltage VREF as the digital output signal VIF. The analog input signal OUT 2 should be smaller than the reference voltage VREF in magnitude (or voltage level) so that the voltage information ADC 250 performs a normal function.

When each of the voltages VDD 1 , VDD 2 , and VDD 3 is larger than the reference voltage VREF in magnitude, the attenuator 230 is used.

FIG. 2 is a circuit diagram of an attenuator shown in FIG. 1 according to an exemplary embodiment of the present inventive concept. The attenuator 230 shown in FIG. 2 includes resistors 231 and 233 . An attenuation constant (a) may be calculated as shown in Equation 1.

Here, R 231 is a resistance value of a first resistor 231 and R 233 is a resistance value of a second resistor 233 . For example, a second output voltage OUT 2 of the attenuator 230 is a*OUT 1 and is smaller than the reference voltage VREF.

The voltage information ADC 250 may use the reference voltage VREF and the ground voltage GND as operation voltages, and convert a second output voltage OUT 2 =a*OUT 1 of the attenuator 230 into a digital output signal VIF.

The encoder 255 may convert a c-bit digital output signal VIF into a d-bit control signal EVIF. Here, c and d are natural numbers and c is greater than d. For example, when c is 10, d may be 4; however, it is not limited thereto. Each of the internal voltage generators 212 and 214 may adjust a level of each internal voltage VDD 3 , VDD 3 ′, VDD 4 , Vx 1 , Vx 2 , Vx 3 , and/or Vy to be described hereinafter in response to a d-bit control signal EVIF.

The selection signal generator 260 may generate a selection signal SEL. As described above, the selection circuit 220 may output at least one of the plurality of voltages VDD 1 , VDD 2 , VDD 3 , VDD 4 , and VTEMP as the first output voltage OUT 1 in response to the selection signal SEL.

The temperature sensor 270 may sense a temperature (for example, an internal temperature) of the image sensor chip 200 A and generate a voltage VTEMP having temperature information according to a result of the sensing. VTEMP may hereinafter be referred to as ‘temperature voltage’. Although one temperature sensor 270 is shown in FIG. 1 , the temperature sensor 270 may collectively represent a plurality of temperature sensors disposed at various positions inside or outside the image sensor chip 200 A.

The image sensor chip 200 A may feedback information VIF on an external voltage VDD 1 and/or VDD 2 supplied from an external voltage supply device (for example, 300 A of FIG. 22 or 300B of FIG. 23 ), information VIF on an internal voltage VDD 3 and/or VDD 4 generated by the internal voltage generator 210 using the first external voltage VDD 1 , and/or information VIF on a temperature of the image sensor chip 200 A to the external voltage supply device (for example, 300 A of FIG. 22 or 300B of FIG. 23 ) and/or the internal voltage generator 210 .

The external voltage supply device (for example, 300 A of FIG. 22 or 300B of FIG. 23 ) can adjust a level of the external voltage VDD 1 and/or VDD 2 supplied to the image sensor chip 200 A using the feedback information VIF, and the internal voltage generator 210 can adjust the internal voltages VDD 3 and/or VDD 4 using a control signal EVIF corresponding to the feedback information VIF. For example, the encoder 255 and the selection signal generation circuit 260 may be disposed in a timing controller for controlling an operation of the image sensor chip 200 A.

A digital code generation circuit may collectively refer to a circuit for generating a digital code VIF using an output voltage OUT 1 of the selection circuit 220 . Accordingly, the digital code generation circuit may include the attenuator 230 and the voltage information ADC 250 .

FIG. 3 is a block diagram of the image sensor chip shown in FIG. 1 according to an exemplary embodiment of the present inventive concept. Referring to FIG. 3 , the image sensor chip 200 A may include an active pixel sensor array 215 , a row driver 217 , a correlated double sampling (CDS) circuit block 219 , the selection circuit 220 , the attenuator 230 , a column ADC block 240 A, and the voltage information ADC 250 .

In the image sensor chip 200 A, components not shown in FIG. 1 may be complemented or supplemented with the components 215 , 217 , 219 , and 240 A shown in FIG. 3 , and components not shown in FIG. 3 may be complemented or supplemented with the components 201 , 203 , 205 , 210 , 255 , 260 , and 270 shown in FIG. 1 .

The active pixel sensor array 215 may include a plurality of active pixel sensors PX. Each of the active pixel sensors PX may include one photoelectric conversion element PD and four transistors; however, the number of transistors may be three or five (or more) depending on a structure of an active pixel sensor.

The row driver 217 may generate each of row control signals ROW 1 to ROWn, where n is a natural number of three or more, for controlling active pixel sensors PX disposed in each row. According to a control of the row driver 217 , each of pixel signals P 1 to Pm output from each active pixel sensor PX disposed in each column may be output to each column line.

The CDS circuit block 219 may include CDS circuits 219 - 1 to 219 - m . The CDS circuits 219 - 1 to 219 - m may perform CDS on the pixel signals P 1 to Pm transmitted through the column lines and generate correlated double sampled pixel signals.

The column ADC block 240 A may include ADCs 240 - 1 to 240 - m . The ADCs 240 - 1 to 240 - m may convert the correlated double sampled pixel signals into digital signals. Each of the ADCs 240 - 1 to 240 - m may be embodied in a single slope ADC; however, it is not limited thereto. The ADCs 240 - 1 to 240 - m are the same as or similar to each other in structure and operation. Each of the ADCs 240 - 1 to 240 - m may be a comparator.

The voltage information ADC 250 may be separately embodied (or integrated) in the image sensor chip 200 A. The voltage information ADC 250 may be different from each of the ADCs 240 - 1 to 240 - m in structure and operation.

FIG. 4 is a block diagram of an image sensor chip according to an exemplary embodiment of the present inventive concept. An image sensor chip 200 B of FIG. 4 does not use the ADC 250 like the image sensor chip 200 A of FIG. 1 , but rather uses a surplus or dummy ADC 240 - 0 embodied in a column ADC block 240 B of FIG. 5 . The surplus or dummy ADC 240 - 0 may be a comparator. Therefore, a voltage information ADC 250 A may include the comparator 240 - 0 and a counter 257 .

The image sensor chip 200 B may include a plurality of pins 201 , 203 , and 205 , the internal voltage generator 210 , the selection circuit 220 , the voltage information ADC 250 A, the encoder 255 , the selection signal generator 260 , and the temperature sensor 270 . The image sensor chip 200 B may be manufactured by a CMOS process and may be included in a mobile device.

Each of the pins 201 and 203 may receive each of the external voltages VDD 1 and VDD 12 supplied by the external voltage supply device (for example, 300 A of FIG. 22 or 300B of FIG. 23 ). A third pin 205 may be used as an output pin for transmitting feedback information DCNT to the external voltage supply device 300 A shown in FIG. 22 or the application processor 400 shown in FIG. 23 . The feedback information VIF of FIG. 1 and the feedback information DCNT of FIG. 4 may include the same information.

For example, the feedback information DCNT may be digital signals or a digital code which includes information on the external voltage VDD 1 and/or VDD 2 supplied by the external voltage supply device 300 A or 300 B, information on the internal voltage VDD 3 and/or VDD 4 generated by the internal voltage generator 210 , and/or information VTEMP on the temperature of the image sensor chip 200 B.

The selection circuit 220 may output at least one of the plurality of voltages VDD 1 , VDD 2 , VDD 3 , VDD 4 , and VTEMP as the first output voltage OUT 1 in response to the selection signal SEL.

When an input stage of the voltage information ADC 250 A includes capacitors 251 , 252 , and 253 for sampling an analog input signal OUT 1 as shown in FIG. 6 , the input stage of the voltage information ADC 250 A may attenuate the analog input signal OUT 1 at a given rate without using the attenuator 230 shown in FIG. 2 . As shown in FIG. 6 , an input signal OUT 1 =IN 1 requiring an analog-to-digital conversion is attenuated by an attenuation constant (a) by the capacitor 251 .

The voltage information ADC 250 A may convert the first output voltage OUT 1 of the selection circuit 220 into a digital signal, e.g., the feedback information DCNT.

The comparator 240 - 0 may compare a ramp signal RAMP with the first output voltage OUT 1 and generate a comparison signal Vo. The counter 257 may generate the feedback information DCNT using the comparison signal Vo and a clock signal CLK. An operation of the voltage information ADC 250 A will be described in detail referring to FIGS. 5 to 7 . A digital code generation circuit may include the voltage information ADC 250 A.

The encoder 255 may convert a c-bit digital output signal DCNT into a d-bit control signal EVIF. Each of the internal voltage generators 212 and 214 may adjust a level of each of the internal voltages VDD 3 and VDD 4 in response to the d-bit control signal EVIF.

The image sensor chip 200 B may feedback information DCNT on the external voltage VDD 1 and/or VDD 2 supplied from the external voltage supply device 300 A or 300 B, information DCNT on the internal voltage VDD 3 and/or VDD 4 generated by the internal voltage generator 210 using the first external voltage VDD 1 , and/or information DCNT on a temperature of the image sensor chip 200 B to the external voltage supply device 300 A or 300 B and/or the internal voltage generator 210 .

Accordingly, the external voltage supply device (for example, 300 A of FIG. 22 or 300B of FIG. 23 ) can adjust a level of the external voltage VDD 1 and/or VDD 2 supplied to the image sensor chip 200 B in response to (or using) the feedback information DCNT, and the internal voltage generator 210 can adjust a level of the internal voltage VDD 3 and/or VDD 4 in response to (or using) the control signal EVIF.

FIG. 5 is a block diagram of the image sensor chip shown in FIG. 4 according to an exemplary embodiment of the present inventive concept. Referring to FIGS. 4 and 5 , the image sensor chip 200 B may include the active pixel sensor array 215 , the row driver 217 , the CDS circuit block 219 , the selection circuit 220 , the column ADC block 240 B, a ramp signal generator 242 , a switch signal generator 244 A, and the counter 257 . As described above, the voltage information ADC 250 A may include a dummy ADC 240 - 0 included in the column ADC block 240 B and the counter 257 . The dummy ADC 240 - 0 may not perform an analog-to-digital conversion operation on the pixel signals P 1 to Pm output from the active pixel sensor array 215 .

In the image sensor chip 200 B, components not shown in FIG. 4 may be complemented or supplemented with the components 215 , 217 , 219 , 240 B, 242 , and 244 A shown in FIG. 5 , and components not shown in FIG. 5 may be complemented or supplemented with the components 201 , 203 , 205 , 210 , 255 , 260 , and 270 shown in FIG. 4 .

The column ADC block 240 B may include ADCs 240 - 1 to 240 - m and the dummy ADC 240 - 0 . The ADCs 240 - 1 to 240 - m may convert correlated double sampled pixel signals into digital signals. Each of the ADCs 240 - 0 to 240 - m may be embodied in a single slope ADC. The ADCs 240 - 0 to 240 - m may be the same as each other in structure and operation.

The ramp signal generator 242 may generate a ramp signal RAMP and the ramp signal RAMP may be supplied to each of the ADCs 240 - 0 to 240 - m . The switch signal generator 244 A may control activation timing and deactivation timing of each of switch signals SS 1 , SS 2 , and SS 3 shown in FIG. 6 .

Switches SW 1 , SW 2 , and SW 3 of FIG. 6 may be turned on in response to a respective one of activated switch signals SS 1 , SS 2 , and SS 3 , and may be turned off in response to a respective one of deactivated switch signals SS 1 , SS 2 , and SS 3 . FIG. 6 is a circuit diagram of a voltage information ADC shown in FIGS. 4 and 5 according to an exemplary embodiment of the present inventive concept. Referring to FIGS. 4 to 6 , the voltage information ADC 250 A may include the plurality of switches SW 1 , SW 2 , and SW 3 , the capacitors 251 , 252 , and 253 , the comparator 240 - 0 , and the counter 257 .

It is assumed that a first capacitor 251 has capacitance of αC, a second capacitor 252 has capacitance of (1−a)C, a third capacitor 255 has capacitance of C, and an attenuation constant α is greater than 0 and less than 1.

FIG. 7 is a timing diagram for describing an operation of the voltage information ADC shown in FIG. 6 according to an exemplary embodiment of the present inventive concept. A process of calculating a count value of the first external voltage VDD 1 among the voltages VDD 1 , VDD 2 . VDD 3 , VDD 4 , and VTEMP will be described in detail referring to FIGS. 4 to 7 . For example, FIG. 7 is a timing diagram of the voltage information ADC 250 A for performing an analog-to-digital conversion on the first external voltage VDD 1 .

The analog-to-digital conversion is performed two times on the first external voltage VDD 1 . To perform the first conversion, each of the switch signals SS 1 and SS 2 is activated to a high level and a third switch signal SS 3 is deactivated to a low level.

For the first conversion, the first output voltage OUT 1 is simultaneously supplied to the first capacitor 251 and the second capacitor 252 . A voltage (IN 1 =OUT 1 ) supplied to the first switch SW 1 is the same as a voltage IN 2 =OUT 1 supplied to the second switch SW 2 . The ramp signal RAMP is supplied to a second input terminal − of the comparator 240 - 0 through a third capacitor 253 . A voltage Vi− of the second input terminal − is the same as the ramp signal RAMP.

For the first conversion, a time interval from time T 1 at which the ramp signal RAMP linearly falls (or ramps-down) to a time T 2 at which an output signal V o of the comparator 240 - 0 transits from a low level to a high level is referred to as a first time interval TCNT 1 . When a voltage Vi+ of a first input terminal + of the comparator 240 - 0 is the same as the voltage Vi− of the second input terminal − of the comparator 240 - 0 , the comparator 240 - 0 generates an output signal Vo, e.g., a comparison signal, transiting from a low level to a high level.

The counter 257 counts the first time interval TCNT 1 in response to the clock signal CLK and generates a first count value, e.g., a first digital code DCNT 1 . In other words, the counter 257 starts a count operation using the clock signal CLK at the time T 1 at which the ramp signal RAMP linearly falls, and stops the count operation at the time T 2 at which the output signal Vo of the comparator 240 - 0 transits from a low level to a high level. The counter 257 may store the first digital code DCNT 1 at a time when the count operation is stopped.

At time T 5 , a first switch signal SS 1 is deactivated to a low level, a second switch signal SS 2 keeps a high level, and a third switch signal SS 3 is activated to a high level to perform the second conversion. As a first terminal of the first capacitor 251 is connected to a ground, the voltage Vi+ of the first input terminal + of the comparator 240 - 0 is changed. A change amount ΔV of the voltage Vi+ of the first input terminal + may be αVDD 1 .

For the second conversion, a time interval from time T 3 at which the ramp signal RAMP linearly falls to a time T 4 at which the output signal Vo of the comparator 240 - 0 transits from a low level to a high level is referred to as a second time interval TCNT 2 . When the voltage Vi+ of the first input terminal + of the comparator 240 - 0 is the same as the voltage Vi− of the second input terminal − of the comparator 240 - 0 , the comparator 240 - 0 generates the output signal Vo transiting from a low level to a high level.

The counter 257 counts the second time interval TCNT 2 in response to the clock signal CLK and generates a second count value, e.g., a second digital code DCNT 2 . In other words, the counter 257 starts a count operation using the clock signal CLK at the time T 3 at which the ramp signal RAMP linearly falls, and stops the count operation at the time T 4 at which the output signal Vo of the comparator 240 - 0 transits from a low level to a high level. The counter 257 may store the second digital code DCNT 2 at a time when the count operation is stopped.

The counter 257 may calculate a difference between the second digital code DCNT 2 and the first digital code DCNT 1 , and generate and store a digital code DCNT=DCNT 2 −DCNT 1 which can be used as feedback information according to a result of the calculation.

According to an exemplary embodiment of the present inventive concept, the counter 257 may calculate a difference between the second digital code DCNT 2 and the first digital code DCNT 1 using a bit reversal technique, and generate and store the digital code DCNT. For example, the counter 257 may generate the digital code DCNT by reversing each of all bits included in the first digital code DCNT 1 and adding the reversed first digital code and the second digital code DCNT 2 . The counter 257 may include a count function, a difference calculation function, and a storage function.

The digital code DCNT=DCNT 2 −DCNT 1 may be transmitted to the power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 through the third pin 205 . The power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 may measure or calculate the first external voltage VDD 1 using Equation 2.

Here, DCNT max is a number determined according to a resolution of the ADC 250 A, and, for example, when the voltage information ADC 250 A is a 10-bit ADC, the DCNT max may be 2 10 =1024.

The power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 knows values of DCNT max , VREF, and a, and thus, may calculate or measure the first external voltage VDD 1 using the digital code DCNT.

Even if the power management IC 300 A of FIG. 22 or the power management IC 300 B of FIG. 23 supplies a supply voltage V 1 to the image sensor chip 200 B, the first external voltage VDD 1 becomes lower than the supply voltage V 1 due to a voltage drop by a transmission line 301 (see FIG. 22 and/or 23 ) present between the power management IC 300 A or 300 B and the image sensor chip 200 B. Accordingly, the power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 may increase or decrease the supply voltage V 1 using the calculated or measured first external voltage VDD 1 .

For example, the first external voltage VDD 1 to be used in the image sensor chip 200 B may be 2.8V in consideration of the voltage drop caused by the transmission line 301 ; however, when the calculated first external voltage VDD 1 corresponding to the digital code DCNT is lower than 2.8V, the power management IC 300 A or 3001 may increase the supply voltage V 1 until the calculated first external voltage VDD 1 corresponding to the digital code DCNT becomes 2.8V.

However, when the first external voltage VDD 1 to be used in the image sensor chip 200 B is 2.8V, and the calculated first external voltage VDD 1 ) corresponding to the digital code DCNT is higher than 2.8V, the power management IC 300 A or 300 B may decrease the supply voltage V 1 until the calculated first external voltage VDD 1 corresponding to the digital code DCNT becomes 2.8V.

Although FIG. 7 shows a timing diagram for calculating the digital code DCNT corresponding to the first external voltage VDD 1 , the voltage information ADC circuit 250 A shown in FIG. 6 may generate a digital code DCNT for each of the voltages VDD 2 , VDD 3 , VDD 4 , and VTEMP using the timing diagram shown in FIG. 7 .

The digital code DCNT for each of the voltages VDD 2 , VDD 3 , VDD 4 , and VTEMP may be transmitted to the power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 through the third pin 205 . The power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 may measure or calculate each of the voltages VDD 2 , VDD 3 , VDD 4 , and VTEMP using Equation 2.

Each of the internal voltage generators 212 and 214 may adjust a level of each voltage VDD 3 or VDD 4 using the control signal EVIF output from the encoder 255 and corresponding to each of the voltages VDD 3 , VDD 4 , and VTEMP.

The image sensor chip 200 A, 200 B, or 200 C (see FIG. 12 ) is configured to make a third internal voltage VDD 3 higher than a highest voltage, e.g., the first external voltage VDD 1 , for a more effective operation of the active pixel sensors PX. In addition, the image sensor chip 200 A, 200 B, or 200 C is configured to make a voltage, e.g., the second internal voltage VDD 4 , lower than the ground voltage (GND, and thus, may include the first internal voltage generator 212 and the second internal voltage generator 214 . Various exemplary embodiments 212 A and 212 B of the first internal voltage generator 212 are shown in FIGS. 8 and 9 , and various exemplary embodiments 214 A and 214 B of the second internal voltage generator 214 are shown in FIGS. 10 and 11 .

FIG. 8 is a circuit diagram of a first internal voltage generator shown in FIGS. 1, 4, and 12 according to an exemplary embodiment of the present inventive concept. The first internal voltage generator 212 A may include a charge pump 502 , an amplifier 504 , a switch circuit 506 , and two resistors 507 - 1 and 507 - 2 .

A voltage regulator may include the amplifier 504 , the switch circuit 506 , and the two resistors 507 - 1 and 507 - 2 . The voltage regulator may generate the first internal voltage VDD 3 higher than the first external voltage VDD 1 .

The charge pump 502 may generate a first voltage pump voltage 2 VDD corresponding to nearly twice the first external voltage VDD 1 by amplifying the first external voltage VDD 1 .

The amplifier 504 may perform a function of an error amplifier using the first voltage pump voltage 2 VDD and the ground voltage as operation voltages, amplify a difference between a reference voltage VBGR and a voltage (e.g., feedback voltage) of a second node ND 2 , and generate an amplified voltage. The reference voltage VBGR may be an output voltage of a bandgap voltage reference circuit.

The switch circuit 506 may perform a function of a power transistor and pull-up a voltage VDD 3 of a first node ND 1 , in other words, the first internal voltage VDD 3 , to the first voltage pump voltage 2 VDD in response to a voltage amplified by the amplifier 504 .

The resistors 507 - 1 and 507 - 2 may form a negative feedback network. The resistors 507 - 1 and 507 - 2 may perform a function of a voltage divider, and generate a first intermediate voltage VDD 3 ′ by dividing the first internal voltage VDD 3 . A resistance value R 2 of a second resistor 507 - 2 may be larger than a resistance value R 1 of a first resistor 507 - 1 . The resistance value R 1 of the first resistor 507 - 1 may be adjusted in response to the control signal EVIF. As the resistance value R 1 of the first resistor 507 - 1 is adjusted, a level of each of the voltages VDD 3 and VDD 3 ′ may be adjusted.

As shown in FIG. 1 or 4 , the first internal voltage VDD 3 may be supplied to the selection circuit 220 . In FIG. 12 , the first intermediate voltage VDD 3 ′ may be supplied to the selection circuit 220 , rather than the first internal voltage VDD 3 .

FIG. 9 is a circuit diagram of the first internal voltage generator shown in FIGS. 1, 4 , and 12 according to an exemplary embodiment of the present inventive concept. The first internal voltage generator 212 B shown in FIG. 9 may include the charge pump 502 , the amplifier 504 , the switch circuit 506 , and three resistors 507 - 1 , 507 - 2 A, and 507 - 2 B. A voltage regulator may include the amplifier 504 , the switch circuit 506 , and the three resistors 507 - 1 , 507 - 2 A, and 507 - 2 B. The voltage regulator may generate the first internal voltage VDD 3 higher than the first external voltage VDD 1 .

Referring to FIGS. 8 and 9 , the second resistor 507 - 2 of FIG. 8 is divided into two resistors 507 - 2 A and 507 - 2 B, and a voltage of a common node (in other words, a third node ND 3 ) of two resistors 507 - 2 A and 507 - 2 B is a first intermediate voltage VDD 3 ′. A resistance value of each of the resistors 507 - 2 A and 507 - 2 B may be R 2 /2.

The charge pump 502 may generate the first voltage pump voltage 2 VDD by amplifying the first external voltage VDD 1 . The amplifier 504 may amplify a difference between the reference voltage VBGR and the voltage, e.g., a feedback voltage, of the second node ND 2 and generate an amplified voltage.

The switch circuit 506 may pull-up the voltage VDD 3 , e.g., the first internal voltage VDD 3 , of the first node ND 1 to the first voltage pump voltage 2 VDD in response to a voltage amplified by the amplifier 504 .

The three resistors 507 - 1 , 507 - 2 A, and 507 - 2 B may form a negative feedback network. The three resistors 507 - 1 , 507 - 2 A, and 507 - 2 B may generate the first intermediate voltage VDD 3 ′ and a second intermediate voltage Vx 1 by dividing the first internal voltage VDD 3 . A resistance value R 1 of the first resistor 507 - 1 may be adjusted in response to the control signal EVIF. As the resistance value of the first resistor 507 - 1 is adjusted, a level of each of the voltages VDD 3 , VDD 3 ′, and Vx 1 may be adjusted.

The first internal voltage VDD 3 may be supplied to the selection circuit 220 as shown in FIG. 1 or 4 . The first intermediate voltage VDD 3 ′ and the second intermediate voltage Vx 1 may be supplied to the selection circuit 220 as shown in FIG. 12 , rather than the first internal voltage VDD 3 .

The first internal voltage VDD 3 may be defined by Equation 3.

VDD 3= Vx 1+2Δ V   [Equation 3]

ΔV may be a difference between the first intermediate voltage VDD 3 ′ and the second intermediate voltage Vx 1 .

FIG. 10 is a circuit diagram of a second internal voltage generator shown in FIGS. 1, 4 , and 12 according to an exemplary embodiment of the present inventive concept. A second internal voltage generator 214 A shown in FIG. 10 may include a first amplifier 520 , a first switch circuit 522 , a second amplifier 524 , a second switch circuit 526 , a charge pump 528 , and two resistors 507 - 4 and 507 - 5 .

For example, the second internal voltage generator 214 A may generate a negative second internal voltage VDD 4 . For example, the second internal voltage generator 214 A may generate a second voltage pump voltage NVDD=−VDD 1 corresponding to a negative first external voltage −VDD 1 using the charge pump 528 .

When the second amplifier 524 , the second switch circuit 526 , and the two resistors 507 - 4 and 507 - 5 configure a first voltage regulator, the first voltage regulator may generate the second internal voltage VDD 4 using the second voltage pump voltage NVDD.

Moreover, when the first amplifier 520 , the first switch circuit 522 , and the two resistors 507 - 4 and 507 - 5 configure a second voltage regulator, the second voltage regulator may generate a third intermediate voltage Vx 2 using the first external voltage VDD 1 .

The first amplifier 520 may use the first external voltage VDD 1 and the ground voltage as operation voltages, amplify a difference between a reference voltage VBGR and a voltage (e.g., feedback voltage) of a first node ND 5 , and generate an amplified voltage.

The first switch circuit 522 may pull-up a voltage Vx 2 , in other words, the third intermediate voltage Vx 2 , of the first node ND 5 to the first external voltage VDD 1 in response to a voltage amplified by the first amplifier 520 . A resistance value R 2 of the second resistor 507 - 5 may be larger than a resistance value R 1 of the first resistor 507 - 4 . The resistance value R 1 of the first resistor 507 - 4 may be adjusted in response to the control signal EVIF. As the resistance value R 1 of the first resistor 507 - 4 is adjusted, a level of each of the voltages Vx 2 and VDD 4 may be adjusted.

The second amplifier 524 may use the first external voltage VDD 1 and the second charge pump voltage NVDD as operation voltages, amplify a difference between a voltage of a second node ND 6 and the ground voltage GND and generate an amplified voltage. The second switch circuit 526 may pull-down a voltage VDD 4 , e.g., the second internal voltage VDD 4 , of a third node ND 7 to the second charge pump voltage NVDD in response to a voltage amplified by the second amplifier 524 .

The second internal voltage VDD 4 may be supplied to the selection circuit 220 as shown in FIG. 1 or 4 . The third intermediate voltage Vx 2 may be supplied to the selection circuit 220 as shown in FIG. 12 , rather than the second internal voltage VDD 4 .

FIG. 11 is a circuit diagram of the second internal voltage generator shown in FIGS. 1, 4, and 12 according to an exemplary embodiment of the present inventive concept. A second internal voltage generator 214 B shown in FIG. 11 may include the first amplifier 520 , the first switch circuit 522 , the second amplifier 524 , the second switch circuit 526 , the charge pump 528 , and three resistors 507 - 4 , 507 - 5 , and 507 - 6 .

Except that a third resistor 507 - 6 is disposed between nodes ND 10 and ND 11 , the second internal voltage generator 214 A of FIG. 10 is the same as the second internal voltage generator 214 B of FIG. 11 in structure and operation. A difference in voltage ΔV may be a difference between a fourth intermediate voltage Vx 3 and a fifth intermediate voltage Vy.

A resistance value R 2 of each of the resistors 507 - 5 and 507 - 6 may be larger than the resistance value R 1 of the first resistor 507 - 4 . The resistance value R 1 of the first resistor 507 - 4 may be adjusted in response to the control signal EVIF. As the resistance value R 1 of the first resistor 507 - 4 is adjusted, a level of each of the voltages Vx 3 and Vy may be adjusted.

The second internal voltage VDD 4 may be supplied to the selection circuit 220 as shown in FIG. 1 or 4 . At least one of the fourth intermediate voltage Vx 3 and the fifth intermediate voltage Vy may be supplied to the selection circuit 220 as shown in FIG. 12 , rather than the second internal voltage VDD 4 .

FIG. 12 is a block diagram of an image sensor chip according to an exemplary embodiment of the present inventive concept. Referring to FIG. 12 , an image sensor chip 200 C of FIG. 12 does not use an additional ADC 250 like the image sensor chip 200 A of FIG. 1 . Rather, the image sensor chip 200 C may use a surplus or dummy ADC 240 - 0 embodied in a column ADC block 240 C of FIG. 13 . The dummy ADC 240 - 0 may be a comparator.

The image sensor chip 200 C may include the plurality of pins 201 , 203 , and 205 , the internal voltage generator 210 , the selection circuit 220 , the voltage information ADC 250 B, the encoder 255 , a selection signal generator 260 A, and the temperature sensor 270 . The image sensor chip 200 C may be manufactured by the CMOS process and may be included in a mobile device. The voltage information ADC 250 B may include the comparator 240 - 0 and the counter 257 .

The pins 201 and 203 may receive the external voltages VDD 1 and VDD 2 supplied by the external voltage supply device (for example, 300 A of FIG. 22 or 300B of FIG. 23 ). The third pin 205 may transmit feedback information DCNT to the external voltage supply device 300 A shown in FIG. 22 or the application processor 400 shown in FIG. 23 .

For example, the feedback information DCNT may be digital signals or a digital code which represents information about the external voltage VDD 1 and/or VDD 2 supplied by the external voltage supply device 300 A or 300 B, information about each of the intermediate voltages Vx 1 , Vx 2 , Vx 3 , Vy, and/or VDD 3 ′ generated by the internal voltage generator 210 , and/or information VTEMP about a temperature (for example, an internal temperature) of the image sensor chip 200 B.

The selection circuit 220 may output at least one of the plurality of voltages VDD 1 , VDD 2 , Vx 1 , Vx 2 , Vx 3 , Vy, VDD 3 ′, and VTEMP as the first output voltage OUT 1 in response to the selection signal SEL 1 .

When an input stage of the voltage information ADC 250 B includes capacitors 251 , 252 , and 253 for sampling an analog input signal OUT 1 as shown in FIG. 15, 17, 19 , or 21 , the input stage of the voltage information ADC 250 B may attenuate the analog input signal OUT 1 at a certain rate even if the attenuator 230 shown in FIG. 2 is not used. As shown in FIG. 15, 17, 19 , or 21 , an input signal OUT 1 =IN 1 requiring an analog-to-digital conversion may be attenuated by the attenuation constant (a) by the capacitor 251 .

The voltage information ADC 250 B may convert the first output voltage OUT 1 into the feedback information DCNT.

The comparator 240 - 0 may compare the ramp signal RAMP with the first output voltage OUT 1 and generate a comparison signal Vo. The counter 257 may generate the feedback information DCNT in response to (or using) the comparison signal Vo and a clock signal CLK. An operation of the voltage information ADC 250 B will be described in detail referring to FIGS. 13 to 21 .

The encoder 255 may convert a c-bit digital output signal DCNT into a d-bit control signal EVIF. Each of the internal voltage generators 212 and 214 may adjust a level of each of the internal voltages VDD 3 and VDD 4 and/or a level of the intermediate voltages Vx 1 , Vx 2 , Vx 3 , Vy, and VDD 3 ′ in response to the d-bit control signal EVIF.

The image sensor chip 200 C may feedback information DCNT about an external voltage VDD 1 and/or VDD 2 supplied by the external voltage supply device (for example, 300 A of FIG. 22 or 300B of FIG. 23 ), information DCNT about each of the intermediate voltages Vx 1 , Vx 2 , Vx 3 , Vy, and VDD 3 ′ generated by the internal voltage generator 210 using the first external voltage VDD 1 , and/or information DCNT about a temperature of the image sensor chip 200 C to the external voltage supply device (for example, 300 A of FIG. 22 or 300B of FIG. 23 ) and/or the internal voltage generator 210 .

Accordingly, the external voltage supply device (for example, 300 A of FIG. 22 or 300B of FIG. 23 ) may adjust a level of the external voltage VDD 1 and/or VDD 2 supplied to the image sensor chip 200 C based on (or using) the feedback information DCNT, and the internal voltage generator 210 may adjust a level of each of the internal voltages VDD 3 and VDD 4 and/or a level of the intermediate voltages Vx 1 , Vx 2 , Vx 3 , Vy, and VDD 3 ′ using (or in response to) the control signal EVIF.

FIG. 13 is a block diagram of the image sensor chip shown in FIG. 12 according to an exemplary embodiment of the present inventive concept. Referring to FIGS. 12 and 13 , the image sensor chip 200 C may include the active pixel sensor array 215 , the row driver 217 , the CDS circuit block 219 , the selection circuit 220 , the column ADC block 240 C, the ramp signal generator 242 , a switch signal generator 244 B, and the counter 257 .

In the image sensor chip 200 C, components not shown in FIG. 12 may be complemented or supplemented with the components 215 , 217 , 219 , 240 C, 242 , and 244 B shown in FIG. 13 , and components not shown in FIG. 13 may be complemented or supplemented with the components 201 , 203 , 205 , 210 , 255 , 260 A, and 270 shown in FIG. 12 .

The column ADC block 240 C may include ADCs 240 - 1 to 240 - m and the dummy ADC 240 - 0 . The ADCs 240 - 1 to 240 - m may convert correlated double sampled pixel signals into digital signals. Each of the ADCs 240 - 0 to 240 - m may be embodied in a single slope ADC. According to an exemplary embodiment of the present inventive concept, each of the ADCs 240 - 1 to 240 - m may be embodied to be the same as or different from the dummy ADC 240 - 0 in structure and operation.

The ramp signal generator 242 may generate a ramp signal RAMP, and the ramp signal RAMP may be supplied to each of the ADCs 240 - 0 to 240 - m . The switch signal generator 244 B may control an activation timing and a deactivation timing of each switch signal shown in FIGS. 6, 14, 16, 18, and 20 .

Referring to FIG. 15 , the voltage information ADC 250 B may include a plurality of switches SW 1 to SW 6 , a plurality of capacitors 251 , 252 , and 253 , the comparator 240 - 0 , and the counter 257 . Some of the plurality of switches SW 1 to SW 6 may not be used by controlling the switch signal generator 244 B according to the voltages VDD 1 , VDD 2 , Vx 1 , Vx 2 , Vx 3 , Vy, VDD 3 ′, VDD 3 , VDD 4 , and/or VTEMP to be subject to analog-to-digital conversion.

For example, referring to FIGS. 6 and 15 , when a voltage to be subject to analog-to-digital conversion is a voltage VDD 1 , VDD 2 , VDD 3 , VDD 4 , or VTEMP, some SW 4 to SW 6 of the plurality of switches SW 1 to SW 6 may not be used.

FIG. 14 is a timing diagram for describing a method of measuring a first internal voltage of the first internal voltage generator shown in FIG. 9 according to an exemplary embodiment of the present inventive concept, and FIG. 15 shows a structure of the voltage information ADC shown in FIGS. 12 and 13 for measuring the first internal voltage of the first internal voltage generator shown in FIG. 8 according to an exemplary embodiment of the present inventive concept.

When a feedback signal DCNT related to each of the voltages VDD 1 , VDD 2 , and VTEMP is generated using the voltage information ADC 250 B, switches SW 4 to SW 6 of the plurality of switches SW 1 to SW 6 included in the voltage information ADC 250 B are not used, and an arrangement and an operation of the switches SW 1 to SW 3 used in the voltage information ADC 250 B are the same as or similar to what is described with reference to FIGS. 6 and 7 .

As shown in FIG. 15 , switches SW 5 and SW 6 of the plurality of switches Sw 1 to SW 6 are not used in the generation of a feedback signal DCNT related to the first internal voltage VDD 3 . The selection circuit 220 outputs the first intermediate voltage VDD 3 ′ as the first output voltage OUT 1 in response to the selection signal SEL 1 .

As shown in FIG. 14 , an analog-to-digital conversion on the first intermediate voltage VDD 3 ′ is performed once. The switch signal generator 244 B activates each of the switch signals SS 1 and SS 2 to a high level and deactivates each of the switch signals SS 3 and SS 4 to a low level.

The first output voltage OUT 1 is supplied to the first capacitor 251 and the second capacitor 252 at the same time. A voltage IN 1 =OUT 1 supplied to the first capacitor 251 through the first switch SW 1 and a voltage IN 2 =OUT 1 supplied to the second capacitor 252 through the second switch SW 2 are the same as each other. The ramp signal RAMP is supplied to the second input terminal − of the comparator 240 - 0 through the third capacitor 253 .

For the conversion, a time interval from a time T 1 ′ at which the ramp signal RAMP linearly falls (or ramps-down) to a time T 2 ′ at which an output signal Vo of the comparator 240 - 0 transits from a low level to a high level is a first time interval TCNT 1 . When a voltage Vi+ of the first input terminal + of the comparator 240 - 0 is the same as a voltage Vi− of the second input terminal − of the comparator 240 - 0 , the comparator 240 - 0 generates the output signal Vo transiting from a low level to a high level.

The counter 257 counts the first time interval TCNT 1 in response to the clock signal CLK and generates a first count value, e.g., a first digital code DCNT 1 . Each of the switch signals SS 1 and SS 2 is deactivated to a low level and each of the switch signals SS 3 and SS 4 is activated to a high level at a time T 5 ′.

As a first terminal of each of the capacitors 251 and 252 is connected to a ground, the voltage Vi+ of the first input terminal + of the comparator 240 - 0 is changed. A change amount ΔV of the voltage Vi+ of the first input terminal + may be VDD 3 ′.

A time interval from a time T 3 ′ at which the ramp signal RAMP linearly falls to a time T 4 ′ at which the output signal V o of the comparator 240 - 0 transits from a low level to a high level is a second time interval TCNT 2 . When the voltage Vi+ of the first input terminal + of the comparator 240 - 0 is the same as the voltage Vi− of the second input terminal − of the comparator 240 - 0 (T 4 ′), the comparator 240 - 0 generates the output signal Vo transiting from a low level to a high level.

From the time T 3 ′, the counter 257 counts the second time interval TCNT 2 in response to the clock signal CLK and generates a second count value, e.g., a second digital code DCNT 2 . In other words, the counter 257 starts a count operation at the time T 3 ′ at which the ramp signal RAMP linearly falls using the clock signal CLK, and stops the count operation at the time T 4 ′ at which the output signal Vo of the comparator 240 - 0 transits from a low level to a high level. The counter 257 may store the second digital code DCNT 2 at a time when the count operation is stopped.

The counter 257 may calculate a difference between the second digital code DCNT 2 and the first digital code DCNT 1 , and generate and store a digital code DCNT=DCNT 2 −DCNT 1 which can be used as feedback information according to a result of the calculation.

According to an exemplary embodiment of the present inventive concept, the counter 257 may calculate a difference between the second digital code DCNT 2 and the first digital code DCNT 1 using the bit reversal technique, and generate and store the digital code DCNT. For example, the counter 257 may reverse each of all bits included in the first digital code DCNT 1 , and generate the digital code DCNT by adding the reversed first digital code and the second digital code DCNT 2 . The counter 257 may include a count function, a difference calculation function, and a storage function.

The digital code DCNT=DCNT 2 −DCNT 1 may be transmitted to the power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 through the third pin 205 . The power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 may measure or calculate the first internal voltage VDD 3 using Equation 4.

DCNT max :V REF=(1+ R 2 /R 1 )× DCNT:VDD 3  [Equation 4]

Here, DCNT max is a number determined according to a resolution of the voltage information ADC 250 B, and, for example, when the voltage information ADC 250 B is a 10-bit ADC, DCNT max may be 2 10 =1024. R 1 is a resistance value of the first resistor 507 - 1 , R 2 is a resistance value of the second resistor 507 - 2 , and DCNT is a digital version of the first intermediate voltage VDD 3 ′.

The power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 know values of DCNT max , VREF, R 1 , and R 2 , and thus, may calculate or measure the first internal voltage VDD 3 using the digital code DCNT.

The power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 may increase or decrease a supply voltage V 1 using the calculated or measured first internal voltage VDD 3 .

FIG. 16 is a timing diagram for describing a method of measuring the first internal voltage of the first internal voltage generator shown in FIG. 9 according to an exemplary embodiment of the present inventive concept, and FIG. 17 shows a structure of the voltage information analog-to-digital converter shown in FIGS. 12 and 13 for measuring the first internal voltage of the first internal voltage generator shown in FIG. 9 according to an exemplary embodiment of the present inventive concept.

When the feedback signal DCNT related to each of the voltages VDD 1 , VDD 2 , and VTEMP is generated using the voltage information ADC 2501 B, switches SW 4 to SW 6 of the plurality of switches SW 1 to SW 6 included in the voltage information ADC 250 B are not used, and the arrangement and the operation of the switches SW 1 to SW 3 used in the voltage information ADC 250 B are the same as or similar to what is described with reference to FIGS. 6 and 7 .

As shown in FIG. 17 , all of the plurality of switches SW 1 to SW 6 are used in the generation of the feedback signal DCNT related to the first internal voltage VDD 3 .

The selection circuit 220 outputs the first intermediate voltage VDD 3 ′ and the second intermediate voltage Vx 1 as first output voltages OUT 1 in response to the selection signal SEL 1 .

A digital version DCNTA of the second intermediate voltage Vx 1 is calculated in a first interval PA, and a digital version DCNTB of a difference ΔV 4 =VDD 3 ′−Vx 1 between the first intermediate voltage VDD 3 ′ and the second intermediate voltage Vx 1 is calculated in a second interval PB.

Each count value, e.g., each of the digital codes DCNT 1 , DCNT 2 , DCNT 3 , and DCNT 4 , is generated by the counter 257 in each of the time intervals TCNT 1 , TCNT 2 , TCNT 3 , and TCNT 4 .

When the second intermediate voltage Vx 1 is supplied to the capacitors 251 and 252 through switches SW 1 and SW 2 in the first interval PA, the first intermediate voltage VDD 3 ′ is not supplied to the switches SW 5 and SW 6 . When the second intermediate voltage Vx 1 is supplied to the capacitors 251 and 252 through the switches SW 1 and SW 2 in the first interval PA, the counter 257 generates the first digital code DCNT 1 in the first time interval TCNT 1 .

When the ground voltage GND is supplied to a first terminal of each of the capacitors 251 and 252 through the switches SW 3 and SW 4 in the first interval PA, the counter 257 generates the second digital code DCNT 2 in the second time interval TCNT 2 . The counter 257 may calculate a difference DCNTA=DCNT 2 −DCNT 1 between the second digital code DCNT 2 and the first digital code DCNT 1 .

When the first intermediate voltage VDD 3 ′ is supplied to the capacitors 251 and 252 through the switches SW 5 and SW 6 in the second interval PB, the second intermediate voltage Vx 1 is not supplied to the switches SW 1 and SW 2 . When the first intermediate voltage VDD 3 ′ is supplied to the capacitors 251 and 252 through the switches SW 5 and SW 6 in the second interval PB, the counter 257 generates a third digital code DCNT 3 in a third time interval TCNT 3 .

When the switches SW 5 and SW 6 are opened and the second intermediate voltage Vx 1 is supplied to a first terminal of each of the capacitors 251 and 252 through the switches SW and SW 2 in the second interval PB, the counter 257 generates a fourth digital code DCNT 4 in a fourth time interval TCNT 4 .

The counter 257 may calculate a difference DCNTB=DCNT 4 −DCNT 3 between the fourth digital code DCNT 4 and the third digital code DCNT 3 , and the counter 257 may output the digital code DCNT according to Equation 5.

DCNT=DCNTA+ 2 *DCNTB

DCNTA=DCNT 2 −DCNT 1 ,DCNTB=DCNT 4 −DCNT 3  [Equation 5]

DCNTA is a digital version of the second intermediate voltage Vx 1 , DCNTB is a digital version of the difference ΔV 4 between the first intermediate voltage VDD 3 ′ and the second intermediate voltage Vx 1 shown in FIG. 10 , and ΔV 3 corresponds to a voltage conversion of the voltage Vi+ of the first input terminal + of the comparator 240 - 0 .

The digital code DCNT may be transmitted to the power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 through the internal voltage generator 210 and/or the third pin 205 .

The power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 know values of DCNT max and VREF, and thus, may calculate or measure the first internal voltage VDD 3 using the digital code DCNT. In other words, the power management IC 300 A or the application processor 400 may calculate or measure the first internal voltage VDD 3 using Equation 6.

DCNT max :V REF= DCNT:VDD 3  [Equation 6]

The power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 may increase or decrease the supply voltage V 1 using the calculated or measured first internal voltage VDD 3 .

FIG. 18 is a timing diagram for describing a method of measuring a second internal voltage of the second internal voltage generator shown in FIG. 10 according to an exemplary embodiment of the present inventive concept, and FIG. 19 shows a structure of the voltage information analog-to-digital converter shown in FIGS. 12 and 13 for measuring the second internal voltage of the second internal voltage generator shown in FIG. 10 according to an exemplary embodiment of the present inventive concept.

When the feedback signal DCNT related to each of the voltages VDD 1 , VDD 2 , and VTEMP is generated using the voltage information ADC 250 B, switches SW 4 to SW 6 of the plurality of switches SW 1 to SW 6 included in the voltage information ADC 250 B are not used, and the arrangement and the operation of the switches SW 1 to SW 3 are the same as or similar to what is described with reference to FIGS. 6 and 7 .

As shown in FIG. 19 , switches SW 5 and SW 6 of the plurality of switches SW 1 to SW 6 are not used in the generation of a feedback signal DCNT related to the second internal voltage VDD 4 .

The selection circuit 220 outputs a third intermediate voltage Vx 2 as the first output voltage OUT 1 in response to the selection signal SEL 1 .

As shown in FIG. 18 , an analog-to-digital conversion on the third intermediate voltage Vx 2 is performed once. The switch signal generator 244 B activates each of the switch signals SS 1 and SS 2 to a high level and deactivates each of the switch signals SS 3 and SS 4 to a low level.

The first output voltage OUT 1 =Vx 2 is supplied to the first capacitor 251 and the second capacitor 252 at the same time. A voltage IN 1 =Vx 2 supplied to the first capacitor 251 through the first switch SW 1 is the same as a voltage IN 2 =Vx 2 supplied to the second capacitor 252 through the second switch SW 2 . The ramp signal RAMP is supplied to the second input terminal − of the comparator 240 - 0 through the third capacitor 253 .

The counter 257 counts the first time interval TCNT 1 in response to the clock signal CLK and generates a first count value, e.g., the first digital code DCNT 1 .

As a first terminal of each of the capacitors 251 and 252 is connected to the ground, the voltage Vi+ of the first input terminal + of the comparator 240 - 0 is changed. A change amount ΔV 5 of the voltage Vi+ of the first input terminal + may be Vx 2 .

The counter 257 counts the second time interval TCNT 2 in response to the clock signal CLK and generates a second count value, e.g., the second digital code DCNT 2 .

The counter 257 may calculate a difference between the second digital code DCNT 2 and the first digital code DCNT 1 , and generate and store the digital code DCNT=DCNT 2 −DCNT 1 which can be used as feedback information according to a result of the calculation.

The digital code DCNT=DCNT 2 −DCNT 1 may be transmitted to the power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 through the third pin 205 . The power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 may measure or calculate the second internal voltage VDD 4 using Equation 7.

DCNT max :V REF=( R 2 /R 1 )× DCNT:VDD 4  [Equation 7]

Here, DCNT max is a number determined according to the resolution of the voltage information ADC 250 B, and, for example, when the voltage information ADC 250 B is a 10-bit ADC, DCNT max may be 2 10 =1024. R 1 is a resistance value of the first resistor 507 - 4 , R 2 is a resistance value of the second resistor 507 - 5 , and DCNT is a digital version of the third intermediate voltage Vx 2 .

The power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 know values of DCNTmax, VREF, R 1 , and R 2 , and thus, may calculate or measure the second internal voltage VDD 4 using the digital code DCNT.

The power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 may increase or decrease the supply voltage V 1 using the calculated or measured second internal voltage VDD 4 . Moreover, the second internal voltage generator 214 A may adjust a level of the third intermediate voltage Vx 2 using the control signal EVIF corresponding to the digital code DCNT.

FIG. 20 is a timing diagram for describing a method of measuring the second internal voltage of the second internal voltage generator shown in FIG. 11 according to an exemplary embodiment of the present inventive concept, and FIG. 21 shows a structure of the voltage information analog-to-digital converter shown in FIGS. 12 and 13 for measuring the second internal voltage of the second internal voltage generator shown in FIG. 11 according to an exemplary embodiment of the present inventive concept.

When the feedback signal DCNT related to each of the voltages VDD 1 , VDD 2 , and VTEMP is generated using the voltage information ADC 250 B, switches SW 4 to SW 6 of the plurality of switches SW 1 to SW 6 included in the voltage information ADC 250 B are not used, and the arrangement and the operation of the switches SW 1 to SW 3 used in the voltage information ADC 250 B are the same as or similar to what is described with reference to FIGS. 6 and 7 .

As shown in FIG. 21 , switches SW 5 and SW 6 of the plurality of switches SW 1 to SW 6 are not used in the generation of the feedback signal DCNT related to the second internal voltage VDD 4 .

The selection circuit 220 outputs the fifth intermediate voltage Vy as the first output voltage OUT 1 in response to the selection signal SEL 1 .

As shown in FIG. 20 , an analog-to-digital conversion on a difference between the fourth intermediate voltage Vx 3 and the fifth intermediate voltage Vy is performed once. The switch signal generator 244 B activates each of the switch signals SS 1 and SS 2 to a high level and deactivates each of the switch signals SS 3 and SS 4 to a low level.

The first output voltage OUT 1 =Vy is supplied to the first capacitor 251 and the second capacitor 252 at the same time. A voltage IN 1 =Vy supplied to the first capacitor 251 through the first switch SW 1 is the same as a voltage IN 2 =Vy supplied to the second capacitor 252 through the second switch SW 2 . The ramp signal RAMP is supplied to the second input terminal − of the comparator 240 - 0 through the third capacitor 253 .

The counter 257 counts the first time interval TCNT 1 in response to the clock signal CLK and generates a first count value, e.g., the first digital code DCNT 1 .

The switch signal generator 244 B deactivates each of the switch signals SS 1 and SS 2 to a low level and activates each of the switch signals SS 3 and SS 4 to a high level. At this time, the selection circuit 220 outputs the fourth intermediate voltage Vx 3 as the first output voltage OUT 1 in response to the selection signal SEL 1 .

As the fourth intermediate voltage Vx 3 is supplied to a first terminal of each of the capacitors 251 and 252 through each of the switches SW 3 and SW 4 , the voltage Vi+ of the first input terminal + of the comparator 240 - 0 is changed. A change amount ΔV 6 of the voltage Vi+ of the first input terminal + may be a difference (=Vy−Vx3) between the fifth intermediate voltage Vy and the fourth intermediate voltage Vx3.

The counter 257 counts the second time interval TCNT 2 in response to the clock signal CLK and generates a second count value, e.g., the second digital code DCNT 2 .

The counter 257 may calculate a difference between the second digital code DCNT 2 and the first digital code DCNT 1 , and generate and store the digital code DCNT=DCNT 2 −DCNT 1 which can be used as feedback information according to a result of the calculation.

The digital code DCNT=DCNT 2 −DCNT may be transmitted to the power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 through the third pin 205 . The power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 may measure or calculate the second internal voltage VDD 4 using Equation 8.

DCNT max :V REF= DCNT:VDD 4  [Equation 8]

The power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 know values of DCNT max and VREF, and thus, may calculate or measure the second internal voltage VDD 4 using the digital code DCNT.

The power management IC 300 A of FIG. 22 or the application processor 400 of FIG. 23 may increase or decrease the supply voltage V 1 using the calculated or measured second internal voltage VDD 4 . Moreover, the second internal voltage generator 214 A may adjust a level of each of the fourth intermediate voltage Vx 3 and the fifth intermediate voltage Vy using the control signal EVIF corresponding to the digital code DCNT.

FIG. 22 is a block diagram of an image processing system 100 A including the image sensor chip 200 shown in FIG. 1, 4 , or 12 according to an exemplary embodiment of the present inventive concept. Referring to FIGS. 1 to 22 , the power management IC 300 A may calculate or measure each of the voltages VDD 1 , VDD 2 , VDD 3 , VDD 4 , and VTEMP using (or in response to) the feedback information (VIF or DCNT) transmitted through the third pin 205 , and adjust (for example, increase, maintain, or decrease) a first voltage V 1 and a second voltage V 2 supplied to the image sensor chip 200 through transmission lines 301 and 303 according to a result of the calculation.

FIG. 23 is a block diagram of an image processing system 100 B including the image sensor chip 200 shown in FIG. 1, 4 , or 12 according to an exemplary embodiment of the present inventive concept. Referring to FIGS. 1 to 21, and 23 , the application processors 400 may calculate or measure each of the voltages VDD 1 , VDD 2 , VDD 3 , VDD 4 , and VTEMP using the feedback information VIF or DCNT transmitted through the third pin 205 , and transmit a voltage control signal CTRL to the power management IC 300 B according to a result of the calculation. The power management IC 300 B may adjust (for example, increase, maintain, or decrease) the first voltage V 1 and the second voltage V 2 in response to the voltage control signal CTRL. The first voltage V 1 and the second voltage V 2 may be transmitted to the image sensor chip 200 through the transmission lines 301 and 303 .

An image sensor chip including an internal voltage generator according to an exemplary embodiment of the present inventive concept can feedback information about an external voltage supplied by an external voltage supply device, information about an internal voltage generated by the internal voltage generator using the external voltage, and information about a temperature of the image sensor chip to the external voltage supply device and/or the internal voltage generator. Therefore, the external voltage supply device can adjust the external voltage supplied to the image sensor chip using the feedback result and the internal voltage generator can adjust the internal voltage using the feedback result.

The image sensor chip according to an exemplary embodiment of the present inventive concept can monitor one of a temperature voltage and all voltages used in the image sensor chip, and feedback a result of the monitoring to a power management IC or an application processor for controlling the image sensor chip as feedback information. Accordingly, the power management IC or the application processor can maximize performance of the image sensor chip using the feedback information in real time.

While the present inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the scope and spirit of the present inventive concept as defined in the appended claims.