Jitter compensation in integrated circuit devices

The disclosure generally relates to jitter compensation in integrated circuit devices.

High-speed electrical devices such as USB 3, HDMI, and display ports are used in high-speed data links. These high-speed electrical devices are generally powered by a regulated power supply, which in ideal conditions provides a stable voltage supply (e.g., 5V, 3.3V, 1.8V). However, when a transition of data occurs (e.g., low-to-high or high-to-low), the devices require increased amount of current from a power supply. The sudden increase in current demand causes transient loads in the power supply. Since a power supply is unable to meet a sudden spike in demand for current, the supply voltage usually drops but later recovers, causing fluctuations in supply voltage. The fluctuations in supply voltage cause jitter in data transmission. In high-speed electrical devices, jitter causes uncertainty in data transmission and reception that may lead to errors and system failure. One approach to reducing jitter is to couple a large capacitor at the output of the power supply. However, a large capacitor is expensive to implement in integrated circuits.

Various aspects of the present disclosure are directed to jitter compensation circuits. In one aspect, a jitter compensation circuit includes a first transistor having a first terminal coupled to a first voltage supply and having a second terminal coupled to a second voltage supply. The first transistor has a gate terminal driven by a first gate voltage responsive to a high-to low transition of data to operate in a first conduction state and to operate in a second conduction state when there is no high-to-low transition of data. The circuit further includes a second transistor having a first terminal coupled to the first voltage supply and having a second terminal coupled to the second voltage supply. The second transistor has a gate terminal driven by a second gate voltage responsive to a low-to-high transition of data to operate in the first conduction state and to operate in the second conduction state when there is no low-to-high transition of data. The circuit also includes a third transistor having a first terminal coupled to the first voltage supply and having a second terminal connected to a gate terminal. The circuit also includes a comparator having a first input coupled to the second voltage supply and having a second input coupled to a reference voltage. The comparator generates a feedback control signal responsive to the second voltage supply and the reference voltage. The circuit also includes a current source coupled between the third transistor and ground. The current source conducts a control current responsive to the feedback control signal. The circuit also includes a first R-C circuit configured to generate the first gate voltage responsive to the high-to-low transition of data. The first R-C circuit is coupled to apply the first gate voltage to the gate terminal of the first transistor. The circuit also includes a second R-C circuit configured to generate the second gate voltage responsive to the low-to-high transition of data. The second R-C circuit is coupled to apply the second gate voltage to the gate terminal of the second transistor. The first R-C circuit comprises a first resistor coupled to a first capacitor, wherein the first R-C circuit is configured to control the duration of the first conduction state responsive to the high-to-low transition of data. The second R-C circuit comprises a second resistor coupled to a second capacitor, wherein the second R-C circuit is configured to control the duration of the first conduction state responsive to the low-to-high transition of data. The first resistor is coupled between the gate terminals of the first and third transistors. The second resistor is coupled between the gate terminals of the second and third transistors. The first and second transistors mirror current in the third transistor when there is no transition of data.

In an additional aspect of the disclosure, a jitter compensation system includes a voltage regulator coupled to receive a first voltage supply and configured to generate a second voltage supply. The system further includes a closed-loop control circuit having a first input coupled to the second voltage supply and having a second input coupled to receive a reference voltage. The closed-loop control circuit generates a feedback control signal responsive to the second voltage supply and the reference voltage. The system also includes a charge compensation circuit having a first input coupled to receive a first gate voltage responsive to a high-to-low transition of data and configured to operate in a first conduction state responsive to the first gate voltage and to operate in a second conduction state when there is no high-to-low transition of data. The charge compensation circuit has a second input coupled to receive a second gate voltage responsive to a low-to-high transition of data and configured to operate in the first conduction state responsive to the second gate voltage and to operate in the second conduction state when there is no low-to-high transition of data. The charge compensation circuit has a third input coupled to the first voltage supply and having a fourth input coupled to receive the feedback control signal. The charge compensation circuit charges the second voltage supply during the first conduction state.

FIG. 1 is a block diagram of a jitter compensation system.

FIG. 2 is a schematic diagram of a compensation circuit.

FIG. 3 shows voltage waveforms of a regulated power supply.

FIG. 4 illustrates an eye diagram without a compensation circuit and with the aid of a compensation circuit.

Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, in which some, but not all embodiments are shown. Indeed, the concepts may be embodied in many different forms and should not be construed as limiting herein. Rather, these descriptions are provided so that this disclosure will satisfy applicable requirements.

FIG. 1 is a block diagram of a jitter compensation system 100 in accordance with an exemplary embodiment. The jitter compensation system 100 includes a compensation circuit 104 coupled to a voltage regulator 108 . Responsive to a high-to-low or a low-to-high transition of data, the compensation circuit 104 compensates charge by providing current to the output of the voltage regulator 108 , thereby reducing sudden drop in voltage caused by the transition of data.

With reference to FIG. 1 , the compensation circuit 104 has a first input 112 coupled to receive a first gate voltage which is generated responsive to a high-to-low transition of data. The compensation circuit 104 is configured to operate in a first conduction state responsive to the first gate voltage and is configured to operate in a second conduction state when no high-to-low transition of data occurs. The high-to-low transition of data refers to a falling edge of data transition.

The compensation circuit 104 also has a second input 116 coupled to receive a second gate voltage which is generated responsive to a low-to-high transition of data. The compensation circuit 104 is configured to operate in the first conduction state responsive to the second gate voltage and is configured to operate in the second conduction state when no low-to-high transition of data occurs. The low-to-high transition of data refers to a rising edge of data transition.

The compensation circuit 104 also has a third input 120 coupled to a first voltage supply 124 , which may be provided by a power supply. The power supply may be an external power supply configured to power an integrated circuit (IC) or may be an internal supply built inside an IC.

With continuing reference to FIG. 1 , the voltage regulator 108 has an input coupled to receive the first voltage supply 124 . The voltage regulator 108 may, for example, be a dc-dc switched regulator which outputs a second voltage supply 132 .

The system 100 includes a closed-loop control circuit 136 having a first input 140 coupled to the second voltage supply 132 . The closed-loop control circuit 136 has a second input 144 coupled to receive a reference voltage 148 . The closed-loop control circuit 136 generates a feedback control signal 152 responsive to the second voltage supply 132 and the reference voltage 148 .

The compensation circuit 104 also has a fourth input 128 coupled to receive the feedback control signal. The feedback control signal biases the compensation circuit 104 to operate in the second conduction state in the absence of a low-to-high or a high-to-low transition of data. When there is a transition of data, the compensation circuit 104 operates in the first conduction state to supplement charge by providing current to the voltage regulator output, thus reducing sudden voltage drops at the second voltage supply 132 .

FIG. 2 is a more detailed schematic diagram of the exemplary jitter compensation circuit 104 . The circuit 104 includes a transistor Q 1 (e.g., PMOS transistor) having a first terminal 204 (e.g., source terminal) coupled to a first voltage supply 220 and having a second terminal 208 (e.g., drain terminal) coupled to a second voltage supply 224 . The transistor Q 1 has a gate terminal 212 which is driven by a first gate voltage responsive to a high-to low transition of data. The transistor Q 1 operates in a first conduction state when the first gate voltage is applied to the gate terminal 212 responsive to the high-to-low transition of data. When there is no high-to-low transition of data, the first gate voltage is not applied to the gate terminal 212 , and as a consequence the first transistor Q 1 operates in a second conduction state.

The circuit 104 also includes a transistor Q 2 (e.g., PMOS transistor) having a first terminal 230 (e.g., source terminal) coupled to the first voltage supply 220 and having a second terminal 234 (e.g., drain terminal) coupled to the second voltage supply 224 . The transistor Q 2 has a gate terminal 238 which is driven by a second gate voltage responsive to a low-to-high transition of data. The transistor Q 2 operates in the first conduction state when the second gate voltage is applied to its gate terminal 238 responsive to the low-to-high transition of data. When there is no low-to-high transition of data, the second gate voltage is not applied to the gate terminal 238 , and as a consequence the transistor Q 2 operates in the second conduction state.

The circuit 104 also includes a transistor Q 3 (e.g., PMOS transistor) having a first terminal 240 (e.g., source terminal) coupled to the first voltage supply 220 and having a second terminal 244 (e.g., drain terminal) connected to its gate terminal 248 .

The circuit 104 also includes a comparator 252 having a first input 256 coupled to the second voltage supply 224 and having a second input 260 coupled to a reference voltage 264 . The comparator 256 generates a feedback control signal 268 responsive to the second voltage supply 224 and the reference voltage 264 . The circuit 104 also includes a current source 272 coupled between the transistor Q 3 and ground. The current source 272 conducts a control current responsive to the feedback control signal 268 .

With continuing reference to FIG. 2 , the circuit 104 also includes a first R-C circuit 276 comprising a capacitor C 1 and a resistor R 1 . The first R-C circuit 276 may be coupled to data via a buffer 278 . The first R-C circuit 276 generates the first gate voltage responsive to the high-to-low transition of data. More specifically, the high-to-low transition of data reverse biases the gate to source voltage of the transistor Q 1 (PMOS transistor), causing the transistor Q 1 to operate in the first conduction state. The first R-C circuit 276 has a decay time determined by R 1 and C 1 , which determines the duration (i.e., time period) of the first conduction state of the transistor Q 1 .

The circuit 104 also includes a second R-C circuit 280 comprising a capacitor C 2 and a resistor R 2 . The second R-C circuit 280 may be coupled to data via an inverting buffer 282 . The second R-C circuit 280 generates the second gate voltage responsive to the low-to-high transition of data. More specifically, the low-to-high transition of data reverse biases the gate to source voltage of the transistor Q 2 (PMOS transistor), causing the transistor Q 2 to operate in the first conduction state. The second R-C circuit 280 has a decay time determined by R 2 and C 2 , which determines the duration (i.e., time period) of the first conduction state of the transistor Q 2 .

According to embodiments of the disclosure, the resistor R 1 is coupled between the gate terminals 212 , 248 of the transistors Q 1 and Q 3 , and the resistor R 2 is coupled between the gate terminals 238 , 248 of the transistors Q 2 and Q 3 . If no high-to-low or low-to-high transition of data occurs, the voltage across the resistors R 1 and R 2 remain close to zero. Thus, when no transition of data occurs, the three gate terminals 212 , 238 and 248 remain approximately at a same potential, causing the transistors Q 1 and Q 2 to mirror current in the transistor Q 3 . Since the current in the transistor Q 3 is adjusted by the current source 272 , the current in the transistors Q 1 and Q 2 are controlled by the current source 272 when no transition of data occurs.

According to embodiments of the disclosure, both the first and the second conduction states are in a linear operating region of the PMOS transistors. However, the transistors Q 1 and Q 2 conduct more current in the first conduction state responsive to the transition of data than in the second conduction state when no transition of data occurs.

Thus, in the absence of a transition of data both the transistors Q 1 and Q 2 operate in the second conduction state, and in second conduction state the transistors Q 1 and Q 2 mirror current in the transistor Q 3 . When a high-to-low transition of data occurs, the transistor Q 1 operates in the first conduction state and supplements charge to the voltage regulator output, which reduces a sudden voltage drop. Similarly, when a low-to-high transition of data occurs, the transistor Q 2 operates in the first conduction state and supplements charge to the voltage regulator output to reduce a sudden voltage drop. However, the duration of the first conduction state of the transistors Q 1 and Q 2 is limited by the decay time of the R-C circuits 276 and 280 . Specifically, the decay time of the first R-C circuit 276 limits the duration of the first conduction state of the transistor Q 1 , causing the transistor Q 1 to return to the second conduction state. Similarly, the decay time of the second R-C circuit 280 limits the duration of the first conduction state of the transistor Q 2 , causing the transistor Q 2 to return to the second conduction state.

FIG. 3 shows output voltage waveforms of a regulated power supply without a compensation circuit and with the aid of a compensation circuit. With a data rate of 10 Gbps, a low-to-high and a high-to-low transition of data causes the output voltage to drop excessively without the aid of a compensation circuit. However, when the compensation circuit is added, the output voltage drop is reduced considerably.

FIG. 4 illustrates an eye diagram of jitter without a compensation circuit and an eye diagram of jitter with the aid of a compensation circuit. The jitter is approximately 10.1 ps without the compensation circuit, but when the compensation circuit is added, the jitter is reduced to 7.1 ps.

Various illustrative components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. The described functionality may be implemented in varying ways for each particular application, but such implementation decision should not be interpreted as causing a departure from the scope of the present disclosure.

For simplicity and clarity, the full structure and operation of all systems suitable for use with the present disclosure is not being depicted or described herein. Instead, only so much of a system as is unique to the present disclosure or necessary for an understanding of the present disclosure is depicted and described.