Power conversion device

The present disclosure relates to a power conversion device that converts a direct-current (DC) voltage from a DC power supply into an alternating-current (AC) voltage.

Conventionally, inverters are known which convert DC voltage generated from an energy source, such as the sunlight, into AC voltage. The inverters are, in general, configured of a bridge circuit having multiple legs each consisting of an upper arm and a lower arm. In such a bridge circuit, the waveform of output AC current is disturbed near a zero crossing, at which output AC current alternates in polarity between positive and negative, due to the timing misalignment between switching of the arms and the zero crossing timing. This may cause the output power rendered unstable. In order to inhibit the current waveform disturbance near the zero crossing, Japanese Patent Laying-Open No. 2014-64363 (PTL 1) discloses an inverter which causes the upper arm and the lower arm of each leg to alternately turn on and off in a period that contains a zero crossing.

Patent Literature

PTL 1: Japanese Patent Laying-Open No. 2014-64363

Technical Problem

However, with the inverter disclosed in Japanese Patent Laying-Open No. 2014-64363, all the arms switch during the period that contains a zero crossing, and thus an increased switching losses result.

The present disclosure is made to solve the above problem, and an object of the present disclosure is to provide a power conversion device that achieves reduction in switching losses and stabilizes the output power.

Solution to Problem

A power conversion device according to a certain aspect of the present disclosure converts a DC voltage from a DC power supply into an AC voltage. The power conversion device includes a first terminal, a second terminal, a third terminal, and a fourth terminal, a full-bridge circuit, a reactor, a switching-mode changer, and a PWM controller. The first terminal and the second terminal are connected to a positive electrode and a negative electrode, respectively, of the DC power supply. The third terminal and the fourth terminal output the AC voltage. The full-bridge circuit includes a first leg and a second leg connected in parallel between the first terminal and the second terminal. The reactor is connected between the third terminal and a first connection point connecting an upper arm and a lower arm of the first leg. The switching-mode changer generates a signal for switching the mode of operation of the full-bridge circuit to a first switching mode or a second switching mode. The PWM controller causes the full-bridge circuit to operate in the first switching mode or the second switching mode in accordance with the signal. The fourth terminal is connected to a second connection point connecting an upper arm and a lower arm of the second leg. In the first switching mode, the upper arm of the first leg and the lower arm of the second leg are switched synchronously, and the lower arm of the first leg and the upper arm of the second leg are non-conducting. In the second switching mode, the lower arm of the first leg and the upper arm of the second leg are switched synchronously, and the upper arm of the first leg and the lower arm of the second leg are non-conducting. The switching-mode changer adjusts the phase of the signal so that reactive power output from the third terminal and the fourth terminal or a distortion rate of the AC voltage is reduced.

Advantageous Effects of Invention

According to the power conversion device of a certain aspect of the present disclosure, two of the four arms are switched and the rest are placed in a non-conducting state. Thus, the switching losses can be reduced, as compared to switching all the arms. Further, the phase of the signal for switching the mode of operation of the full-bridge circuit is adjusted so that the reactive power is reduced or the distortion rate of the AC voltage is reduced. Thus, the output power is stabilized. As such, the power conversion device can reduce the switching losses and stabilize the output power.

FIG. 1 is a block diagram showing a configuration of a power conversion device according to Embodiment 1.

FIG. 2 is a block diagram showing a configuration of a switching-mode changer shown in FIG. 1 .

FIG. 3 is a process flow diagram of a phase adjuster shown in FIG. 2 .

FIG. 4 is a diagram showing an example operation of the power conversion device according to Embodiment 1 when an alternating-current (AC) load is a resistance load.

FIG. 5 is an enlarged view (of A portion) immediately after the start of the operation in FIG. 4 .

FIG. 6 is an enlarged view (of B portion) immediately before the end of the operation in FIG. 4 .

FIG. 7 is a diagram showing an example operation of the power conversion device according to Embodiment 1 when the AC load is an inductive load.

FIG. 8 is an enlarged view (of A portion) immediately after the start of the operation in FIG. 7 .

FIG. 9 is an enlarged view (of B portion) immediately before the end of the operation in FIG. 7 .

FIG. 10 is a diagram showing an example operation of the power conversion device according to Embodiment 1 when the AC load is a rectifier load.

FIG. 11 is an enlarged view (of A portion) immediately after the start of the operation in FIG. 10 .

FIG. 12 is an enlarged view (of B portion) immediately before the end of the operation in FIG. 10 .

FIG. 13 is a block diagram showing a configuration of a switching-mode changer included in a power conversion device according to Embodiment 2.

FIG. 14 is a process flow diagram of a phase adjuster shown in FIG. 13 .

FIG. 15 is a diagram showing an example operation of the power conversion device according to Embodiment 2 when an AC load is a resistance load.

FIG. 16 is an enlarged view (of A portion) immediately after the start of the operation in FIG. 15 .

FIG. 17 is an enlarged view (of B portion) immediately before the end of the operation in FIG. 15 .

FIG. 18 is a diagram showing an example operation of the power conversion device according to Embodiment 2 when the AC load is an inductive load.

FIG. 19 is an enlarged view (of A portion) immediately after the start of the operation in FIG. 18 .

FIG. 20 is an enlarged view (of B portion) immediately before the end of the operation in FIG. 18 .

FIG. 21 is a diagram showing an example operation of the power conversion device according to Embodiment 2 when the AC load is a rectifier load.

FIG. 22 is an enlarged view (of A portion) immediately after the start of the operation in FIG. 21 .

FIG. 23 is an enlarged view (of B portion) immediately before the end of the operation in FIG. 21 .

Hereinafter, embodiments according to the present disclosure will be described, with reference to the accompanying drawings. Note that the same reference signs are used to refer to the same or like parts, and the description thereof will not be repeated. The embodiments and variations thereof described below may be selectively combined as appropriate.

Configuration of Power Conversion Device

Referring to FIG. 1 , a configuration of a power conversion device 100 according to Embodiment 1 will be described. FIG. 1 is a block diagram showing a configuration of power conversion device 100 according to Embodiment 1. As shown in FIG. 1 , power conversion device 100 includes a first terminal P 1 , a second terminal P 2 , a third terminal P 3 , a fourth terminal P 4 , an inverter 1 , an LC filter 2 , low-pass filters 3 , 4 , a switching-mode changer 5 , and a PWM (Pulse Width Modulation) controller 6 .

Power conversion device 100 converts a direct-current (DC) voltage from a DC power supply 7 into an alternating-current (AC) voltage and outputs the AC voltage to an AC load 8 . Power conversion device 100 operates in a discontinuous conduction mode near a zero crossing at which the output AC current alternates in polarity between positive and negative. In the discontinuous conduction mode, there is a time period in which the current output from inverter 1 is zero.

First terminal P 1 and second terminal P 2 are connected to the positive electrode and the negative electrode, respectively, of DC power supply 7 . DC power supply 7 is a constant voltage source, such as a cell, or a control voltage source for a power convertor that can output DC voltage.

Third terminal P 3 and fourth terminal P 4 are connected to AC load 8 , and output AC voltage. AC load 8 is, for example, a resistance load, an inductive load, a rectifier load, or an appliance load. An AC power supply, such as a single-phase AC system, may be connected to third terminal P 3 and fourth terminal P 4 , instead of AC load 8 .

Inverter 1 includes a full-bridge circuit FB. Full-bridge circuit FB includes a first leg LG 1 , a second leg LG 2 , and a current sensor 11 . First leg LG 1 and second leg LG 2 are connected in parallel between first terminal P 1 and second terminal P 2 .

First leg LG 1 includes an upper arm Q 1 , a lower arm Q 2 , and freewheel diodes D 1 , D 2 . Upper arm Q 1 and lower arm Q 2 are connected in series, between first terminal P 1 and second terminal P 2 . Freewheel diode D 1 is connected in anti-parallel with upper arm Q 1 . Freewheel diode D 2 is connected in anti-parallel with lower arm Q 2 . A first connection point N 1 connecting upper arm Q 1 and lower arm Q 2 is connected to LC filter 2 .

Second leg LG 2 includes an upper arm Q 3 , a lower arm Q 4 , and freewheel diodes D 3 , D 4 . Upper arm Q 3 and lower arm Q 4 are connected in series, between first terminal P 1 and second terminal P 2 . Freewheel diode D 3 is connected in anti-parallel with upper arm Q 3 . Freewheel diode D 4 is connected in anti-parallel with lower arm Q 4 . A second connection point N 2 connecting upper arm Q 3 and lower arm Q 4 is connected to fourth terminal P 4 .

Full-bridge circuit FB operates in a first switching mode or a second switching mode. In the first switching mode, upper arm Q 1 and lower arm Q 4 are switched synchronously, and lower arm Q 2 and upper arm Q 3 are non-conducting. In the second switching mode, lower arm Q 2 and upper arm Q 3 are switched synchronously, and upper arm Q 1 and lower arm Q 4 are non-conducting.

Upper arms Q 1 , Q 3 and lower arms Q 2 , Q 4 are self-arc-extinguishing semiconductor switching elements that are represented by, for example, IGBT (Insulated Gate Bipolar Transistor) or MOSFET (Metal Oxide Semiconductor Field Effective Transistor). If upper arms Q 1 , Q 3 and lower arms Q 2 , Q 4 are MOSFETs, parasitic diodes included in MOSFETs may be used, instead of freewheel diodes D 1 to D 4 .

LC filter 2 includes a reactor L, a capacitor C, and a voltage sensor 21 . Reactor L is connected between first connection point N 1 and third terminal P 3 . Capacitor C is connected between third terminal P 3 and fourth terminal P 4 .

LC filter 2 smooths a reactor current Iinv, which is generated by a potential difference between an output voltage Vinv of inverter 1 and a voltage Vc (C voltage) across capacitor C, and outputs the smoothed current to AC load 8 . Output voltage Vinv is a voltage between first connection point N 1 and second connection point N 2 , and output from inverter 1 to LC filter 2 . Reactor current Iinv flows from first connection point N 1 between upper arm Q 1 and lower arm Q 2 to reactor L of LC filter 2 .

Current sensor 11 included in inverter 1 measures reactor current Iinv flow from first connection point N 1 to reactor L, and outputs the measurement to low-pass filter 3 . Voltage sensor 21 included in LC filter 2 measures voltage Vc across capacitor C, and outputs the measurement to low-pass filter 4 . Voltage Vc is an AC voltage that is output from third terminal P 3 and fourth terminal P 4 .

Having received the value of reactor current Iinv measured by current sensor 11 , low-pass filter 3 outputs a current value FIinv to switching-mode changer 5 . Current value FIinv is obtained by reducing the high-frequency component of reactor current Iinv. Low-pass filter 3 may be omitted if power conversion device 100 can obtain, in the discontinuous conduction mode, information for allowing compensation for a difference between the sampled value and an average current of currents in periods including a period in which the current is zero. If the current flow to capacitor C included in LC filter 2 is sufficiently small and the phase difference in fundamental wave between reactor current Iinv and a load current Iload flow through AC load 8 is small, low-pass filter 3 may receive load current Iload, instead of reactor current Iinv.

Having received the value of voltage Vc measured by voltage sensor 21 , low-pass filter 4 outputs a voltage value FVc to switching-mode changer 5 . Voltage value FVc is obtained by reducing a sampling error in voltage Vc caused by the switching noise of full-bridge circuit FB. Low-pass filter 4 may be omitted if effects of the switching noise of full-bridge circuit FB are small.

Switching-mode changer 5 generates a reference signal Dpole* for switching the mode of operation of full-bridge circuit FB to the first switching mode or the second switching mode. When reference signal Dpole* is 1, full-bridge circuit FB operates in the first switching mode. When reference signal Dpole* is 0, full-bridge circuit FB operates in the second switching mode. Switching-mode changer 5 adjusts the phase of reference signal Dpole* so that reactive power output from power conversion device 100 is reduced. A method of adjustment of the phase of reference signal Dpole* by switching-mode changer 5 will be described below.

PWM controller 6 generates PWM signals Sa, Sb, using an output voltage command value Vc* received from a higher-level control unit, a reference triangular wave Carrier, and reference signal Dpole*. PWM controller 6 includes a voltage control circuit 61 , a comparator 62 , and multipliers 63 , 64 .

Voltage control circuit 61 generates a conduction ratio command value D*, based on output voltage command value Vc*. Comparator 62 compares conduction ratio command value D* with reference triangular wave Carrier. When reference triangular wave Carrier is less than conduction ratio command value D*, comparator 62 outputs a signal set to 1 (high level). When reference triangular wave Carrier is greater than or equal to conduction ratio command value D*, comparator 62 outputs a signal set to 0 (low level).

Conduction ratio command value D* is in a range from 0 to 1, and represented by Equation (1) below. In Equation (1), m denotes a value in a range from 0 to 1, indicating a modulation coefficient for the inverter, ω denotes an angular frequency obtained by multiplying the frequency (e.g., 50 Hz or 60 Hz) of output alternating current by 2π, and t denotes a time.

D*= 0.5( m ×sin ω t+ 1)  Equation (1)

Reference triangular wave Carrier is a triangular wave in a range from 0 to 1, and has a carrier period.

Multiplier 63 multiplies the output signal of comparator 62 by reference signal Dpole*, thereby generating PWM signal Sa. For this reason, when reference signal Dpole* is 1, multiplier 63 generates PWM signal Sa whose conduction ratio is D*. When reference signal Dpole* is 0, multiplier 63 generates PWM signal Sa having a value 0. PWM signal Sa is output to upper arm Q 1 and lower arm Q 4 . Upper arm Q 1 and lower arm Q 4 are on when PWM signal Sa is 1, and off when PWM signal Sa is 0.

Multiplier 64 multiplies an inverted signal of the output signal of comparator 62 by an inverted signal of reference signal Dpole*, thereby generating PWM signal Sb. For this reason, when reference signal Dpole* is 0, multiplier 64 generates PWM signal Sb whose conduction ratio is (1−D*). When reference signal Dpole* is 1, multiplier 64 generates PWM signal Sb having a value 0. PWM signal Sb is output to lower arm Q 2 and upper arm Q 3 . Lower arm Q 2 and upper arm Q 3 are on when PWM signal Sb is 1, and off when PWM signal Sb is 0.

As such, PWM controller 6 outputs a signal having a pulse width modulated in accordance with a result of comparison of conduction ratio command value D* with reference triangular wave Carrier. In other words, when reference signal Dpole* is 1, PWM controller 6 generates PWM signal Sa whose conduction ratio is D* and generates PWM signal Sb having a value 0. This causes full-bridge circuit FB to operate in the first switching mode. When reference signal Dpole* is 0, PWM controller 6 generates PWM signal Sb whose conduction ratio is (1−D*) and generates PWM signal Sa having a value 0. This causes full-bridge circuit FB to operate in the second switching mode.

Switching-Mode Changer

Next, a method of adjustment of the phase of reference signal Dpole* by switching-mode changer 5 will be described. Switching-mode changer 5 adjusts the phase of reference signal Dpole* for each predetermined period T. Period T is, for example, a cycle of an alternating current indicated by output voltage command value Vc*.

FIG. 2 is a block diagram showing a configuration of switching-mode changer 5 . As shown in FIG. 2 , switching-mode changer 5 includes multipliers 51 a to 51 d , a mean value operator 52 , effective value operators 53 a , 53 b , a subtractor 54 , a square root operator 55 , a phase adjuster 56 , and a signal generator 57 . The components of switching-mode changer 5 are configured of, for example, a memory storing, for example, a program describing processing operations, and a processor for execution of the program. The processor is configured of, for example, a microcomputer, a DSP (Digital Signal Processor), an FPGA, etc.

Multiplier 51 a multiplies voltage value FVc, received from low-pass filter 4 , by current value FIinv received from low-pass filter 3 . Mean value operator 52 computes, for each period T, effective power value P which is the mean value of values output from multiplier 51 a during the period T. Multiplier 51 b computes a square value of effective power value P output from mean value operator 52 .

Effective value operator 53 a computes, for each period T, an effective value Vrms for voltage values FVc that are received from low-pass filter 4 during the period T. Effective value multiplier 53 b computes, for each period T, an effective value Irms for current values FIinv that are received from low-pass filter 3 during the period T. Multiplier 51 c computes a product VrmsIrms of effective values Vrms, Irms which are respectively output from effective value operators 53 a , 53 b . Multiplier 51 d computes a square value of product VrmsIrms output from multiplier 51 c.

Subtractor 54 computes and outputs a difference between the square value of product VrmsIrms and the square value of effective power value P. Square root operator 55 computes and outputs a square root value Pq of the output value from subtractor 54 .

If frequency components of current value FIinv and frequency components of voltage value FVc include the same frequency, product VrmsIrms indicates an apparent power output from power conversion device 100 , and square root value Pq indicates a reactive power output from power conversion device 100 . Similarly, if frequency components of current value FIinv and frequency components of voltage value FVc include multiple, identical harmonics, square root value Pq, again, indicates a reactive power output from power conversion device 100 .

Phase adjuster 56 computes an adjustment θ0 for the phase of reference signal Dpole*, based on the immediately preceding square root value Pq and square root value Pq0 most recently output from square root operator 55 . Using adjustment θ0 output from phase adjuster 56 , signal generator 57 generates reference signal Dpole* based on Equation (2). In Equation (2), ω denotes an angular frequency obtained by multiplying the frequency (e.g., 50 Hz or 60 Hz) of output alternating current by 2π.

Process by Phase Adjuster

FIG. 3 is a process flow diagram of phase adjuster 56 . Initially, in step S 1 , phase adjuster 56 assigns 0 to Pq0, 0 to θ0, and 1 to the flag. Here, the phase (the initial phase) of reference signal Dpole*, generated when θ0=0, matches the phase of output voltage command value Vc* that is received from a higher-level control unit. The flag indicates a direction of adjustment of adjustment θ0 in the immediately preceding period T. Specifically, the flag=1 indicates that adjustment θ0 has been adjusted in the positive direction in the immediately preceding period T. The flag=0 indicates that adjustment θ0 has been adjusted to in the negative direction in the immediately preceding period T.

In step S 2 , phase adjuster 56 waits for a given time period (here, period T). Next, in step S 3 , phase adjuster 56 obtains square root value Pq from square root operator 55 . In step S 4 , phase adjuster 56 compares square root value Pq, obtained in step S 3 , with Pq0.

If Pq<Pq0 (Yes in step S 4 ), phase adjuster 56 confirms whether the flag is 1 in step S 5 . If the flag is 1 (YES in step S 5 ), phase adjuster 56 adds a predetermined unit adjustment Δθ to adjustment θ0 in step S 6 . If the flag is 0 (NO in step S 5 ), phase adjuster 56 subtracts unit adjustment Δθ from adjustment θ0 in step S 7 .

If Pq≥Pq0 (NO in step S 4 ), phase adjuster 56 confirms whether the flag is 1 in step S 8 . If the flag is 1 (YES in step S 8 ), phase adjuster 56 subtracts unit adjustment Δθ from adjustment θ0 and changes the flag to 0 in step S 9 . If the flag is 0 (NO in step S 8 ), phase adjuster 56 adds unit adjustment Δθ to adjustment θ0 and changes the flag to 1 in step S 10 .

After steps S 6 , S 7 , S 9 , S 10 , phase adjuster 56 , in step S 11 , assigns Pq, received in step S 4 , to Pq0. Phase adjuster 56 then outputs adjustment θ0 in step S 12 . After step S 12 , the process returns to step S 2 .

In steps S 4 to S 12 , if square root value Pq is less than the immediately preceding square root value Pq0, unit adjustment Δθ is added/subtracted to/from adjustment θ0 in the same manner as the immediately preceding process. If square root value Pq is greater than the immediately preceding square root value Pq0, unit adjustment Δθ is added/subtracted to/from adjustment θ0 in a manner different from the immediately preceding process. This adjusts the phase of reference signal Dpole* so that the reactive power output from power conversion device 100 is reduced.

Example Operation

FIG. 4 is an example operation of power conversion device 100 when AC load 8 is a resistance load. FIG. 5 is an enlarged view (of A portion of FIG. 4 ) immediately after the start of the operation of power conversion device 100 in FIG. 4 . FIG. 6 is an enlarged view (of B portion of FIG. 4 ) immediately before the end of the operation of power conversion device 100 in FIG. 4 . FIG. 7 shows an example operation of power conversion device 100 when AC load 8 is an inductive load. FIG. 8 is an enlarged view (of A portion of FIG. 7 ) immediately after the start of the operation of power conversion device 100 in FIG. 7 . FIG. 9 is an enlarged view (of B portion of FIG. 7 ) immediately before the end of the operation of power conversion device 100 in FIG. 7 . FIG. 10 shows an example operation of power conversion device 100 when AC load 8 is a rectifier load. FIG. 11 is an enlarged view (of A portion of FIG. 10 ) immediately after the start of the operation of power conversion device 100 in FIG. 10 . FIG. 12 is an enlarged view (of B portion of FIG. 10 ) immediately before the end of the operation of power conversion device 100 in FIG. 10 . In FIGS. 4 to 12 , the first graph shows voltage Vc (C voltage), the second graph shows reactor current Iinv and load current Iload, the third graph shows adjustment 90 , the fourth graph shows effective power value P and square root value Pq, and the fifth graph shows the total harmonic distortion (THD) factor for voltage Vc.

As shown in FIGS. 4 to 12 , one can notice that square root value Pq, corresponding to the reactive power, gradually decreases and converges over time since the start of the operation of power conversion device 100 . This suggests that power conversion device 100 inhibits the reactive power, thereby allowing supply of stable power to AC load 8 .

Further, one can notice that the total harmonic distortion rate of voltage Vc also gradually decreases and converges over time since the start of the operation of power conversion device 100 . This indicates that the less the total harmonic distortion rate of voltage Vc is, the less the distortion of AC voltage output from power conversion device 100 . The less the distortion of the AC voltage, the closer the characteristics of the AC voltage to the characteristics of AC voltage supplied from an AC system. This suggests that power conversion device 100 outputs an AC voltage having characteristics close to the characteristics of the AC voltage supplied from the AC system.

In particular, if AC load 8 is an inductive load, the AC voltage output from power conversion device 100 and the AC current flow through AC load 8 are out of phase. Thus, voltage Vc, reactor current Iinv, and load current Iload are unstable at the start of the operation of power conversion device 100 . However, the waveforms of voltage Vc, reactor current Iinv, and load current Iload are stabilized over time.

Furthermore, as shown in FIGS. 10 to 12 , if AC load 8 is a rectifier load, a spike current, occurred at the start of the operation of power conversion device 100 , is gradually inhibited.

As shown in FIGS. 4 to 12 , power conversion device 100 operates in the discontinuous conduction mode near the zero crossing at which load current Iload alternates in polarity between positive and negative. In the discontinuous conduction mode, there is a time period in which reactor current Iinv, output from inverter 1 , is zero. This is because either upper arm Q 1 and lower arm Q 4 or lower arm Q 2 and upper arm Q 3 are switched between on and off and the rest are non-conducting, and a duration of no current thus occurs as the conduction ratio command value D* decreases.

Advantageous Effects

As described above, power conversion device 100 includes first terminal P 1 , second terminal P 2 , third terminal P 3 , fourth terminal P 4 , full-bridge circuit FB, reactor L, switching-mode changer 5 , and PWM controller 6 . First terminal P 1 and second terminal P 2 are respectively connected to the positive electrode and negative electrode of DC power supply 7 . Third terminal P 3 and fourth terminal P 4 output AC voltage. Full-bridge circuit FB includes first leg LG 1 and second leg LG 2 connected in parallel between first terminal P 1 and second terminal P 2 . Reactor L is connected between third terminal P 3 and first connection point N 1 connecting upper arm Q 1 and lower arm Q 2 of first leg LG 1 . Switching-mode changer 5 generates reference signal Dpole* for switching the mode of operation of full-bridge circuit FB to the first switching mode or the second switching mode. PWM controller 6 causes full-bridge circuit FB to operate in the first switching mode or the second switching mode, in accordance with reference signal Dpole*. Fourth terminal P 4 is connected to second connection point N 2 connecting upper arm Q 3 and lower arm Q 4 of second leg LG 2 . In the first switching mode, upper arm Q 1 of first leg LG 1 and lower arm Q 4 of second leg LG 2 are switched synchronously, and lower arm Q 2 of first leg LG 1 and upper arm Q 3 of second leg LG 2 are non-conducting. In the second switching mode, lower arm Q 2 and upper arm Q 3 are switched synchronously, and upper arm Q 1 and lower arm Q 4 are non-conducting. Switching-mode changer 5 adjusts the phase of reference signal Dpole* so that the reactive power output from third terminal P 3 and fourth terminal P 4 is reduced.

According to the above configuration, two of the four arms included in full-bridge circuit FB are switched synchronously, and the rest are non-conducting. Specifically, half of the four arms are controlled to an off-state per half the period of the output AC voltage. For this reason, the switching losses can be reduced, as compared to the conventional technology which simultaneously switches the four arms.

Third terminal P 3 is connected to first connection point N 1 connecting upper arm Q 1 and lower arm Q 2 of first leg LG 1 via reactor L. Fourth terminal P 4 is connected to second connection point N 2 connecting upper arm Q 3 and lower arm Q 4 of second leg LG 2 . For this reason, if (i) the zero crossing timing at which the AC current, flow through the load connected to third terminal P 3 and fourth terminal P 4 , alternates in polarity and (ii) the timing at which the first switching mode and the second switching-mode changer are out of sync, the output power becomes unstable. However, with the above configuration, switching-mode changer 5 adjusts the phase of reference signal Dpole* so that the reactive power is reduced. This can inhibit the output power from becoming unstable due to the switching timing of the arms and the zero crossing timing being out of sync, thereby supplying stable power to AC load 8 . As such, power conversion device 100 achieves reduction in the switching losses and stabilization of output power.

Switching-mode changer 5 periodically obtains square root value (parameter value) Pq that correlates with the reactive power and adjusts the phase of reference signal Dpole*. Square root value Pq is calculated using effective power value P output from third terminal P 3 and fourth terminal P 4 , effective value Vrms of voltage Vc, and effective value Irms of reactor current Iinv. Square root value Pq increases with an increase of the reactive power. For this reason, switching-mode changer 5 adjusts the phase of reference signal Dpole* in the same direction as the immediately preceding direction of adjustment if the newly obtained square root value Pq is less than the most recently obtained square root value Pq0. If the newly obtained square root value Pq is greater than the most recently obtained square root value Pq0, switching-mode changer 5 adjusts the phase of reference signal Dpole* in a direction opposite the immediately preceding direction of adjustment. This allows switching-mode changer 5 to readily adjust the phase of reference signal Dpole* so that the reactive power is reduced.

PWM controller 6 controls the operation of full-bridge circuit FB, based on output voltage command value Vc*. Switching-mode changer 5 starts adjusting the phase of reference signal Dpole* using the phase of output voltage command value Vc* as the initial phase for reference signal Dpole*. This allows, when AC load 8 is a resistance load, the initial phase of reference signal Dpole* to be set to some extent close to the phase of the output current even if the output current cannot be observed. As a result, the phase of reference signal Dpole* can converge quickly.

Referring to FIG. 13 , a power conversion device according to Embodiment 2 will be described. FIG. 13 is a block diagram showing a configuration of a switching-mode changer 5 a included in the power conversion device according to Embodiment 2. The power conversion device according to Embodiment 2 is different from power conversion device 100 according to Embodiment 1 in that the power conversion device according to Embodiment 2 includes switching-mode changer 5 a shown in FIG. 13 , instead of switching-mode changer 5 . The other details of the power conversion device according to Embodiment 2 are the same as power conversion device 100 shown in FIG. 1 , and thus the descriptions thereof will not be repeated. Note that the power conversion device according to Embodiment 2 may not be provided with current sensor 11 and low-pass filter 3 shown in FIG. 1 .

Switching-Mode Changer

Switching-mode changer 5 a adjusts the phase of reference signal Dpole* for each predetermined period T. Period T is, for example, a cycle of an alternating current indicated by the output voltage command or the output current command. As shown in FIG. 13 , switching-mode changer 5 a includes a distortion rate meter 58 , a phase adjuster 56 a , and a signal generator 57 . Components of switching-mode changer 5 a are configured of, for example, a memory storing, for example, a program describing processing operations, and a processor for execution of the program.

Distortion rate meter 58 measures, for each period T, the total harmonic distortion rate THD (FVc) of voltage value FVc received in the period T. Phase adjuster 56 a computes adjustment θ0 for the phase of reference signal Dpole*, based on the total harmonic distortion rate THD (FVc) and the most recently measured total harmonic distortion rate THD0. As with Embodiment 1, signal generator 57 generates reference signal Dpole* based on Equation (2) below, using adjustment θ0 output from phase adjuster 56 a.

Process by Phase Adjuster

FIG. 14 is a process flow diagram of phase adjuster 56 a . The process of phase adjuster 56 a is the same as the process of phase adjuster 56 according to Embodiment 1, shown in FIG. 3 , except that the process of phase adjuster 56 a includes execution of steps S 21 , S 23 , S 24 , S 31 , instead of steps S 1 , S 3 , S 4 , S 11 .

In step S 21 , phase adjuster 56 a makes settings as follows: THD0=0, θ0=0, the flag=1. In step S 2 , phase adjuster 56 a waits for period T, after which it obtains, in step S 23 , the total harmonic distortion rate THD (FVc) of voltage value FVc from distortion rate meter 58 . In step S 24 , phase adjuster 56 a compares the total harmonic distortion rate THD (FVc), obtained in step S 23 , with THD0.

If THD (FVc)<THD0 (Yes in step S 24 ), phase adjuster 56 a confirms whether the flag is 1 in step S 5 , as with Embodiment 1. Phase adjuster 56 a adds/subtracts unit adjustment Δθ to/from adjustment θ0, in accordance with a value of the flag (steps S 6 , S 7 ). If THD (FVc)≥THD0 (NO in step S 24 ), phase adjuster 56 a confirms whether the flag is 1 in step S 8 , as with Embodiment 1. Phase adjuster 56 a subtracts/adds unit adjustment Δθ from/to adjustment θ0, in accordance with a value of the flag (steps S 9 , S 10 ).

In step S 31 after steps S 6 , S 7 , S 9 , S 10 , phase adjuster 56 a assigns THD (FVc), obtained in step S 23 , to THD0. Phase adjuster 56 a then outputs adjustment θ0 in step S 12 . After step S 12 , the process returns to step S 2 .

With the process shown in FIG. 14 , as with the immediately preceding process, unit adjustment Δθ is added/subtracted to/from adjustment θ0 if the total harmonic distortion rate THD (FVc) of voltage value FVc is less than the immediately preceding total harmonic distortion rate THD0. If the total harmonic distortion rate THD (FVc) of voltage value FVc is greater than the immediately preceding total harmonic distortion rate THD0, unit adjustment Δθ is added/subtracted to/from adjustment θ0 in a different manner from the immediately preceding process. This adjusts the phase of reference signal Dpole* so that the total harmonic distortion rate of voltage Vc output from power conversion device 100 is reduced.

Example Operation

FIG. 15 is an example operation of the power conversion device when AC load 8 is a resistance load. FIG. 16 is an enlarged view immediately after (A portion of FIG. 15 ) the start of the operation of power conversion device 100 in FIG. 15 . FIG. 17 is an enlarged view immediately before (B portion of FIG. 15 ) the end of the operation of power conversion device 100 in FIG. 15 . FIG. 18 shows an example operation of the power conversion device when AC load 8 is an inductive load. FIG. 19 is an enlarged view immediately after (A portion of FIG. 18 ) the start of the operation of power conversion device 100 in FIG. 18 . FIG. 20 is an enlarged view immediately before (B portion of FIG. 18 ) the end of the operation of power conversion device 100 in FIG. 18 . FIG. 21 shows an example operation of the power conversion device when AC load 8 is a rectifier load. FIG. 22 is an enlarged view immediately after (A portion of FIG. 21 ) the start of the operation of power conversion device 100 in FIG. 21 . FIG. 23 is an enlarged view immediately before (B portion of FIG. 21 ) the end of the operation of power conversion device 100 in FIG. 21 . In FIGS. 15 to 23 , the first graph shows the waveform of voltage Vc (C voltage), the second graph shows reactor current Iinv and load current Iload, the third graph shows adjustment θ0, the fourth graph shows effective power value P and square root value Pq, and the fifth graph shows the total harmonic distortion rate for voltage Vc.

As shown in FIGS. 15 to 23 , it can be seen that, compared to the start of the operation of power conversion device 100 , the total harmonic distortion rate of voltage Vc gradually decreases and converges. This suggests that power conversion device 100 outputs an AC voltage that has characteristics close to the characteristics of the AC voltage supplied from the AC system.

Furthermore, one can notice that square root value Pq, corresponding to the reactive power, gradually decreases and converges, as compared to the start of the operation of power conversion device 100 . This suggests that power conversion device 100 inhibits the reactive power, thereby allowing supply of stable power to AC load 8 .

Furthermore, as shown in FIGS. 21 to 23 , if AC load 8 is a rectifier load, a spike current, occurred at the start of the operation of power conversion device 100 , is gradually inhibited.

Advantageous Effects

As described above, periodically, switching-mode changer 5 a obtains the total harmonic distortion rate of voltage Vc and adjusts the phase of reference signal Dpole*. If the newly obtained total harmonic distortion rate THD (FVc) is less than the most recently obtained total harmonic distortion rate THD0, switching-mode changer 5 a adjusts the phase of reference signal Dpole* in the same direction as the immediately preceding direction of adjustment. If the newly obtained total harmonic distortion rate THD (FVc) is greater than the most recently obtained total harmonic distortion rate THD0, switching-mode changer 5 a adjusts the phase of reference signal Dpole* in a direction opposite the immediately preceding direction of adjustment.

According to the above configuration, as with Embodiment 1, the switching losses can be reduced, as compared to the conventional technology which switches the four arms. Furthermore, switching-mode changer 5 a adjusts the phase of reference signal Dpole* so that the total harmonic distortion rate of voltage Vc is reduced. This allows power conversion device 100 to output an AC voltage that has characteristics close to the characteristics of the AC voltage supplied from the AC system. This can also inhibit the output power from becoming unstable due to the switching timing of the arms and the zero crossing timing being out of sync, thereby allowing supply of stable power to AC load 8 . As such, power conversion device 100 achieves reduction in the switching losses and stabilization of output power.

Variations

In Embodiments 1, 2, PWM controller 6 generates PWM signals Sa, Sb based on output voltage command value Vc*. However, PWM controller 6 may include a current control circuit which receives the output current command value and generates conduction ratio command value D*, instead of voltage control circuit 61 . In this case, PWM controller 6 generates PWM signals Sa, Sb, based on the output current command value. Switching-mode changers 5 , 5 a may start adjusting the phase of reference signal Dpole*, using the phase of the output current command value as the initial phase for reference signal Dpole*.

This allows the initial phase of reference signal Dpole* to be set close to the phase of the output current even if the output current cannot be observed. As a result, the phase of reference signal Dpole* can converge more quickly.

If the power conversion device receives none of the output voltage command value and the output current command value, switching-mode changers 5 , 5 a may determine the initial phase for reference signal Dpole* as follows. In other words, PWM controller 6 causes full-bridge circuit FB to operate in a general continuous conduction mode. Specifically, PWM controller 6 turns on and off the upper arm Q 1 of first leg LG 1 and lower arm Q 4 of second leg LG 2 synchronously, and turns on lower arm Q 2 of first leg LG 1 and upper arm Q 3 of second leg LG 2 alternately to upper arm Q 1 and lower arm Q 4 , respectively. Switching-mode changers 5 , 5 a determine the initial phase for the reference signal Dpole*, based on at least one of voltage value FVc or current value FIinv at this time.

As such, the mode of operation of full-bridge circuit FB includes a continuous conduction mode, in addition to the first switching mode and the second switching mode. The continuous conduction mode is a third switching mode in which upper arm Q 1 and lower arm Q 2 of first leg LG 1 are switched on alternately, and upper arm Q 3 and lower arm Q 4 of second leg LG 2 are switched on alternately. Switching-mode changers 5 , 5 a determine the initial phase for the reference signal Dpole*, based on at least one of voltage value FVc or current value FIinv when full-bridge circuit FB is in operation in the continuous conduction mode, and start adjusting the phase of reference signal Dpole*.

Note that the initial phase of the reference signal Dpole* may be determined based on at least one of voltage value FVc or current value FIinv in the continuous conduction mode, even if the power conversion device receives at least one of the output voltage command value or the output current command value. However, the greater the amounts of changes in effective value of the output voltage command value and the output current command value as the mode of operation switches from the continuous conduction mode to the discontinuous conduction mode, the greater the error in the initial phase to the phase of the output current.

One example will be described in which the initial phase for reference signal Dpole* is determined based on current value FIinv. When full-bridge circuit FB is caused to operate while switching the mode of operation between the first switching mode and the second switching mode in accordance with reference signal Dpole*, a current having the positive polarity is output in the first switching mode, and a current having the negative polarity is output in the second switching mode. In other words, the current polarity remains the same when reference signal Dpole* is generated based only on the polarity of current value FIinv. Thus, the mode of operation does not switch between the first switching mode and the second switching mode. In contrast, a current zero crossing occurs in the third switching mode, and thus reference signal Dpole* can be generated based on current value FIinv. In other words, switching-mode changers 5 , 5 a determine the initial phase for the reference signal Dpole* based on current value FIinv in the third switching mode, and start adjusting the phase of reference signal Dpole*.

Next, one example will be described in which the initial phase for reference signal Dpole* is determined based on both voltage value FVc and current value FIinv. In the third switching mode, operating conditions, in which a two-level inverter—specific ripple current is maximum, can occur near the current zero crossing. Due to this, when reference signal Dpole* is generated based on only the polarity of current value FIinv, a change between the positive and negative polarities occurs several times near the current zero crossing. As a result, an error in the initial phase is great when the mode of operation of full-bridge circuit FB is switched from the third switching mode to the first switching mode or second switching mode.

These problems can be solved by making use of the polarity of voltage value FVc, the polarity of current value FIinv, and the value of current value FIinv. In order to eliminate the effects, on reference signal Dpole*, of the changes in polarity of current value FIinv due to the ripple current near the current zero crossing which occurs in the third switching mode, if reference signal Dpole* corresponds to the first switching mode, voltage value FVc is positive, and current value FIinv is positive, switching-mode changers 5 , 5 a generate reference signal Dpole* that corresponds to the second switching mode, as the current value FIinv decreases to a certain value or lower. If reference signal Dpole* corresponds to the second switching mode, voltage value FVc is negative, and current value FIinv is negative, switching-mode changers 5 , 5 a generate reference signal Dpole* that corresponds to the first switching mode, as the current value FIinv increases to a certain value or greater. Note that the same advantageous effects can be obtained by replacing conduction ratio command value D* having a DC component removed therefrom, with voltage value FVc. In other words, switching-mode changers 5 , 5 a determine the initial phase for the reference signal Dpole* based on voltage value FVc or at least one of conduction ratio command value D* or current value FIinv in the third switching mode, and start adjusting the phase of reference signal Dpole*.

Instead of the configurations according to Embodiments 1 and 2, in order to operate full-bridge circuit FB by switching it between the first switching mode and the second switching mode in accordance with reference signal Dpole*, (i) when voltage value FVc is positive and current value FIinv is positive in the first switching mode, switching-mode changers 5 , 5 a may generate reference signal Dpole* so that the mode of operation of full-bridge circuit FB is changed to the second switching mode as the current value FIinv decreases to a certain value or lower, and (ii) when voltage value FVc is negative and current value FIinv is negative in the second switching mode, switching-mode changers 5 , 5 a may generate reference signal Dpole* so that the mode of operation of full-bridge circuit FB is changed to the first switching mode as the current value FIinv increases to a certain value or greater. This achieves switching of full-bridge circuit FB between the first switching mode and the second switching mode, improving the output reactive power and the waveform distortion. Note that the same advantageous effects can be obtained by replacing conduction ratio command value D* having a DC component removed therefrom, with voltage value FVc. In other words, switching-mode changers 5 , 5 a determine the initial phase for the reference signal Dpole* based on voltage value FVc or at least one of conduction ratio command value D* or current value FIinv in the first switching mode and the second switching mode, and start adjusting the phase of reference signal Dpole*. The phase of reference signal Dpole* is repeatedly adjusted by the determination of the initial phase for the reference signal Dpole*.

In the above description, phase adjusters 56 , 56 a adjust the phase of reference signal Dpole* for each period T of an alternating-current indicated by output voltage command value Vc*. However, phase adjusters 56 , 56 a may adjust the phase of reference signal Dpole* every constant multiple of period T.

In Embodiment 1 above, phase adjuster 56 included in switching-mode changer 5 may obtain, for each period T, another parameter value that correlates with the reactive power, instead of square root value Pq. As another parameter value, phase adjuster 56 may obtain, for example, a ratio (=P/Pq) of effective power value P and square root value Pq. The ratio P/Pq is a parameter value which decreases with an increase of the reactive power. In this case, if the value of the newly obtained ratio P/Pq is greater than the value of the most recently obtained ratio P/Pq, phase adjuster 56 adds/subtracts unit adjustment Δθ to/from adjustment θ0 as with the immediately preceding process. In other words, switching-mode changer 5 adjusts the phase of reference signal Dpole* in the same direction as the immediately preceding direction of adjustment. In contrast, if the value of the newly obtained ratio P/Pq is less than the value of the most recently obtained ratio P/Pq, phase adjuster 56 adds/subtracts unit adjustment Δθ to/from adjustment θ0 in a manner different from the immediately preceding process. In other words, switching-mode changer 5 adjusts the phase of reference signal Dpole* in a direction opposite the immediately preceding direction of adjustment. This allows power conversion device 100 to yield a reduced reactive power, while inhibiting the reduction of effective power.

In the above description, switching-mode changers 5 , 5 a each output reference signal Dpole* indicating 0 or 1. However, reference signal Dpole* may be any signal that indicates one of different two values. For example, reference signal Dpole* may by any signal that indicates 1 or −1. In this case, switching-mode changers 5 , 5 a may generate reference signal Dpole*, in accordance with Equation (3) below:

Dpole*=(sin(ω t+θ 0)/|sin(ω t+θ 0)|)  Equation (3)

When reference signal Dpole* is 1, PWM controller 6 generates PWM signal Sb having a value 0. When reference signal Dpole* is −1, PWM controller 6 generates PWM signal Sa having a value 0.

The presently disclosed embodiments should be considered as illustrative in all aspects and do not limit the present disclosure. The scope of the present disclosure is defined by the appended claims, rather than by the above description of the embodiments. All changes which come within the meaning and range of equivalency of the appended claims are intended to be embraced within their scope.

1 inverter; 2 LC filter; 3 , 4 low-pass filter; 5 , 5 a switching-mode changer; 6 PWM controller; 7 DC power supply; 8 AC load; 11 current sensor; 21 voltage sensor; 51 a to 51 d , 63 , 64 multiplier; 52 mean value operator; 53 a , 53 b effective value operator; 54 subtractor; 55 square root operator; 56 , 56 a phase adjuster; 57 signal generator; 58 distortion rate meter; 61 voltage control circuit; comparator; 100 power conversion device; C capacitor; D 1 to D 4 freewheel diode; FB full-bridge circuit; L reactor; LG 1 first leg; LG 2 second leg; N 1 first connection point; N 2 second connection point; P 1 first terminal; P 2 second terminal; P 3 third terminal; P 4 fourth terminal; Q 1 , Q 3 upper arm; Q 2 , Q 4 lower arm.