Converter with soft switching function

This application is the U.S. National Phase under 35 U.S.C. § 371 of International Patent Application No. PCT/JP2018/030906, filed on Aug. 22, 2018, which claims the benefits of Japanese Patent Application No. 2017-159267, filed on Aug. 22, 2017 the entire contents of which are hereby incorporated by reference.

The present invention relates to a converter that performs soft switching.

Power converters such as DC-DC converters employ zero voltage switching (hereinafter, referred to as ZVS) in order to reduce switching losses and achieve high-efficiency power transfer or in order to reduce noise and suppress switching surges so as to enable the use of low-cost, low withstand voltage devices. Patent Document 1 discloses a DC-DC converter capable of high-efficiency power transfer by implementing ZVS operations when a large voltage difference occurs between a primary direct-current voltage and a secondary direct-current voltage. The DC-DC converter described in Patent Document 1 detects power on each of primary and secondary sides and increases or decreases the duties of primary switches and the duties of secondary switches so as to minimize a power difference between the two sides. Accordingly, ZVS operations are accomplished.

Patent Literature

Patent Document 1: Japanese Patent Application Laid-Open No. 2016-012970

Problems to be Solved by Invention

However, in order to implement ZVS operations, Patent Document 1 requires switching control and the detection of power on each of the primary and secondary sides. This complicates circuit configurations and control of the circuits, making it difficult to improve productivity and achieve cost reduction.

It is an object of the present invention to provide a converter that implements ZVS operations with simple control so as to reduce switching losses.

Means for Solving Problems

A converter according to a first aspect of the present invention includes a first full-bridge circuit including switching elements, each including either a capacitor that is a parasitic capacitance or four external capacitors connected in parallel, a transformer including a first winding connected to the first full-bridge circuit and a second winding coupled magnetically to the first winding, an inductance component connected in series with the first winding or the second winding, and a control circuit that performs soft switching control of each switching element in the first full-bridge circuit. An inductor current flowing through an equivalent inductor that is equivalent to the transformer and the inductance component is larger than or equal to a threshold current at a timing of switching between turn-on and turn-off of each switching element. The threshold current is set to make energy stored in the equivalent inductor greater than or equal to total energy stored in the capacitor or the four capacitors.

According to a second aspect of the present invention, in the converter according to the first aspect, the first full-bridge circuit includes a first leg in which a first switching element and a second switching element are connected in series, and a second leg in which a third switching element and a fourth switching element are connected in series. The control circuit alternately repeats control for turning the first and fourth switching elements on and turning the second and third switching elements off and control for turning the first and fourth switching elements off and turning the second and third switching elements on, while providing a first dead time in between. The inductor current flowing during the first dead time is larger than or equal to the threshold current.

According to a third aspect of the present invention, the converter according to the second aspect further includes a second full-bridge circuit that includes a third leg in which a fifth switching element and a sixth switching element are connected in series and a fourth leg in which a seventh switching element and an eighth switching element are connected in series, each of the fifth to eighth switching elements including either a capacitor that is a parasitic capacitance or four external capacitors connected in parallel. The second winding is connected to a midpoint of each of the third leg and the fourth leg. The control circuit alternately repeats control for turning the fifth and eighth switching elements on and turning the sixth and seventh switching elements off and control for turning the fifth and eighth switching elements off and turning the sixth and seventh switching elements on, while providing a second dead time in between, in synchronization with a switching frequency of the first to fourth switching elements. The inductor current flowing during the second dead time is larger than or equal to the threshold current.

According to a fourth aspect of the present invention, in the converter according to the first to third aspects, the following expression is satisfied:

I ref =α·Vx √(4 C/L ),

where I ref is the threshold current, Vx is an input voltage of the first full-bridge circuit, C is a capacitance of the capacitor, L is an inductance of the equivalent inductor, and α is a correction coefficient.

Effects of the Invention

According to the first to fourth aspects of the present application, it is possible to achieve ZVS of each switching element in the first full-bridge circuit by passing the inductor current larger than or equal to the threshold current through the equivalent inductor.

In particular, according to the third aspect of the present application, it is also possible to achieve ZVS of each switching element in the second full-bridge circuit.

These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

FIG. 1 is a circuit diagram of a DC-DC converter according to an embodiment;

FIG. 2 is a timing chart illustrating turn-on and turn-off of each switching element;

FIGS. 3A and 3B are diagrams for describing current paths in the DC-DC converter;

FIGS. 4A and 4B are diagrams for describing current paths in the DC-DC converter;

FIG. 5 is a diagram for describing a current path in the DC-DC converter;

FIGS. 6A and 6B illustrate the waveform of an inductor current when V 1 (t 1 )≠V 2 (t 2 );

FIG. 7 is a diagram for describing first control and second control;

FIG. 8 illustrates the waveforms of voltages and the inductor current in the first control; and

FIG. 9 illustrates the waveforms of the voltages and the inductor current in the second control.

Embodiments of the present invention will be described hereinafter with reference to the drawings. In the following description, a DC-DC converter is given as an example of the converter according to the present invention.

1. Circuit Configuration of DC-DC Converter

FIG. 1 is a circuit diagram of a DC-DC converter 1 according to an embodiment of the present invention.

The DC-DC converter 1 includes a pair of input/output terminals IO 11 and IO 12 and a pair of input/output terminals IO 21 and IO 22 . A direct-current (DC) power supply E 1 is connected to the input/output terminals IO 11 and IO 12 . The input/output terminals IO 21 and IO 22 are connected to a DC power supply E 2 . The DC-DC converter 1 transforms a power supply voltage of the DC power supply E 1 that is input from the input/output terminals IO 11 and IO 12 , and outputs the transformed voltage from the input/output terminals IO 21 and IO 22 . The DC-DC converter 1 also transforms a power supply voltage of the DC power supply E 2 that is input from the input/output terminals IO 21 and IO 22 , and outputs the transformed voltage from the input/output terminals IO 11 and IO 12 . That is, the DC-DC converter 1 is capable of bidirectional power transfer.

The DC-DC converter 1 includes a first full-bridge circuit 10 , a second full-bridge circuit 20 , and a transformer T.

The transformer T includes a first winding n 1 and a second winding n 2 . The first and second windings n 1 and n 2 are magnetically coupled to each other. The first winding n 1 is connected to the input/output terminals IO 11 and IO 12 via the first full-bridge circuit 10 . The second winding n 2 is connected to the input/output terminals IO 21 and IO 22 via the second full-bridge circuit 20 .

The first full-bridge circuit 10 includes a first leg in which switching elements Q 11 and Q 12 are connected in series, and a second leg in which switching elements Q 13 and Q 14 are connected in series. The switching elements Q 11 , Q 12 , Q 13 , and Q 14 are one example of first, second, third, and fourth switching elements according to the present invention.

The first winding n 1 of the transformer T is connected to the midpoint of each of the first and second legs. An inductor L 1 is provided between the first winding n 1 of the transformer T and the midpoint of the first leg. Note that the inductor L 1 may be connected in series with either the first winding n 1 or the second winding n 2 , and the location of the inductor L 1 may be appropriately changed. For example, the inductor L 1 may be provided between the first winding n 1 and the midpoint of the second leg. The inductor L 1 may be a discrete device or a leakage inductance of the transformer T, or a combination of a discrete device and a leakage inductance.

The switching elements Q 11 , Q 12 , Q 13 , and Q 14 are connected in parallel with diodes D 11 , D 12 , D 13 , and D 14 and capacitors C 11 , C 12 , C 13 , and C 14 . The switching elements Q 11 to Q 14 are MOS-FETs. Alternatively, the switching elements Q 11 to Q 14 may be other transistors such as IGBTs or JFETs. The diodes D 11 to D 14 may be discrete devices or parasitic diodes. Each of the capacitors C 11 to C 14 may be a discrete device or a parasitic capacitance, or a combination of a discrete device and a parasitic capacitance.

The second full-bridge circuit 20 includes a third leg in which switching elements Q 21 and Q 22 are connected in series, and a fourth leg in which the switching elements Q 23 and Q 24 are connected in series. The switching elements Q 21 , Q 22 , Q 23 , and Q 24 are one example of fifth, sixth, seventh, and eighth switching elements according to the present invention.

The second winding n 2 of the transformer T is connected to the midpoint of each of the third and fourth legs. The aforementioned inductor L 1 may be provided between the second winding n 2 and the midpoint of the third or fourth leg.

The switching elements Q 21 , Q 22 , Q 23 , and Q 24 are connected in parallel with diodes D 21 , D 22 , D 23 , and D 24 and capacitors C 21 , C 22 , C 23 , and C 24 . The switching elements Q 21 to Q 24 are MOS-FETs. Alternatively, the switching elements Q 21 to Q 24 may be other transistors such as IGBTs or JFETs. The diodes D 21 to D 24 may be discrete devices or parasitic diodes. Each of the capacitors C 21 to C 24 may be a discrete device or a parasitic capacitance, or a combination of a discrete device and a parasitic capacitance.

Gate terminals of the switching elements Q 11 to Q 14 and Q 21 to Q 24 are each connected to a control circuit 30 . The control circuit 30 controls the switching of each of the switching elements Q 11 to Q 14 , Q 21 to Q 24 so that the output power of the DC-DC converter 1 becomes set target power. In the present embodiment, the control circuit 30 implements soft switching of each of the switching elements Q 11 to Q 14 and Q 21 to Q 24 in order to reduce switching losses.

2. Soft Switching Operations

Soft switching operations of the switching elements Q 11 to Q 14 and Q 21 to Q 24 will be described hereinafter.

The DC-DC converter 1 transfers power from either the input/output terminals IO 11 , IO 12 or the input/output terminals IO 21 , IO 22 to the other, or vice versa. The following description is given on the assumption that the input/output terminals IO 11 and IO 12 are on the input side and the input/output terminals IO 21 and IO 22 are on the output side.

FIG. 2 is a timing chart illustrating turn-on and turn-off of each of the switching elements Q 11 to Q 14 and Q 21 to Q 24 . FIGS. 3, 4, and 5 are diagrams for describing current paths in the DC-DC converter 1 . In FIGS. 3 to 5 , the inductor L 1 and the transformer T in FIG. 1 are illustrated as an equivalent inductor L. This inductor L is one example of an inductance component according to the present invention. In FIGS. 3 to 5 , each switching element is indicated by a simplified graphical symbol.

In FIG. 2 , V 1 is a potential difference between the midpoint between the switching elements Q 11 and Q 12 and the midpoint between the switching elements Q 13 and Q 14 in FIG. 1 , V 2 is a potential difference between the midpoint between the switching elements Q 21 and Q 22 and the midpoint between the switching elements Q 23 and Q 24 , and I L is the current flowing through the inductor L. In FIG. 2 , the DC power supplies E 1 and E 2 are assumed to supply the same power supply voltage. That is, V 1 (t 1 )=V 2 (t 2 ). In FIG. 2 , the solid-line waveforms for the switching elements Q 11 to Q 14 and Q 21 to Q 24 represent the waveforms of source-drain voltages, and the broken-line waveforms therefor represent the waveforms of drain currents.

The control circuit 30 alternately turns on and off the switching elements Q 11 , Q 14 and the switching elements Q 12 , Q 13 in the first full-bridge circuit 10 at a switching frequency f (cycle of 1/f), while providing a dead time (second first dead time) in between. The control circuit 30 also alternatively turns on and off the switching elements Q 21 , Q 24 and the switching elements Q 22 , Q 23 in the second full-bridge circuit 20 at the switching frequency f, while providing a dead time (second dead time) in between.

The control circuit 30 also creates a phase difference δ at the timing of switching between the first full-bridge circuit 10 and the second full-bridge circuit 20 . That is, the switching elements Q 11 , Q 14 and the switching elements Q 21 , Q 24 have a phase difference δ, and the switching elements Q 12 , Q 13 and the switching elements Q 22 , Q 23 have a phase difference δ as illustrated in FIG. 2 . As a result, the voltages V 1 and V 2 also have a phase difference δ.

Period from t 0 to t 1

In the period from t 0 to t 1 , the switching elements Q 11 , Q 14 and the switching elements Q 22 , Q 23 are ON, and the switching elements Q 12 , Q 13 and the switching elements Q 21 , Q 24 are OFF. In this case, current flows in order from the DC power supply E 1 to the switching element Q 11 , the inductor L, the switching element Q 22 , the DC power supply E 2 , the switching element Q 23 , and the switching element Q 14 as illustrated in FIG. 3A . The power supply voltages of the DC power supplies E 1 and E 2 are applied to the inductor L. That is, the inductor current I L increases as illustrated in FIG. 2 .

At timing t 1 , the switching elements Q 22 and Q 23 are turned off, and the switching elements Q 21 and Q 24 are turned on. At this time, due to the presence of the dead time, all of the switching elements Q 21 to Q 24 are OFF during the dead time. At this time, the inductor current I L continues to flow through the inductor L due to the nature of the inductor L. Therefore, current flows through a path from the inductor L to the capacitor C 21 , the capacitor C 23 , and the switching element Q 14 and through a path from the inductor L to the capacitor C 22 , the capacitor C 24 , and the switching element Q 14 as illustrated in FIG. 3B .

Accordingly, the capacitors C 22 and C 23 are charged, and the capacitors C 21 and C 24 are discharged. Here, the time until the charging and discharging of the capacitors C 21 to C 24 are completed is determined by the inductor current I L and the capacitances of the capacitors C 21 to C 24 . If the charge time of the capacitors C 22 and C 23 is longer than the turn-off time of the switching elements Q 22 and Q 23 , the turn-off of the switching elements Q 22 and Q 23 is implemented by soft switching.

After the discharging of the capacitors C 21 and C 24 has been completed, the diodes D 21 and D 24 are turned on. That is, the drain-source voltages of the switching elements Q 21 and Q 24 are zero. If the switching elements Q 21 and Q 24 are turned on at this time, this turn-on is implemented by ZVS.

Period from t 1 to t 2

In the period from t 1 to t 2 , the switching elements Q 11 and Q 14 and the switching elements Q 21 and Q 24 are ON, and the switching elements Q 12 and Q 13 and the switching elements Q 22 and Q 23 are OFF. In this case, current flows in order from the DC power supply E 1 to the switching element Q 11 , the inductor L, the switching element Q 21 , the DC power supply E 2 , the switching element Q 24 , and the switching element Q 14 as illustrated in FIG. 4A . That is, the DC power supply E 1 is discharged, and the DC power supply E 2 is charged.

At timing t 2 , the switching elements Q 11 and Q 14 are turned off, and the switching elements Q 12 and Q 13 are turned on. At this time, all of the switching elements Q 11 to Q 14 are OFF during the dead time in the same manner as described with the switching elements Q 21 to Q 24 . Since the inductor current I L continues to flow through the inductor L, current flows through a path from the inductor L to the switching element Q 21 , the DC power supply E 2 , the switching element Q 24 , the capacitor C 14 , the capacitor C 12 , and the inductor L and through a path from the inductor L to the switching element Q 21 , the DC power supply E 2 , the switching element Q 24 , the capacitor C 13 , the capacitor C 11 , and the inductor L as illustrated in FIG. 4B .

Accordingly, the capacitors C 11 and C 14 are charged, and the capacitors C 12 and C 13 are discharged. As described previously, if the charge time of the capacitors C 11 and C 14 is longer than the turn-off time of the switching elements Q 11 and Q 14 , the turn-off of the switching elements Q 11 and Q 14 is implemented by soft switching.

After the discharging of the capacitors C 12 and C 13 has been completed, the diodes D 12 and D 13 are turned on. That is, the drain-source voltages of the switching elements Q 12 and Q 13 are zero. If the switching elements Q 12 and Q 13 are turned on at this time, the ZVS of the switching elements Q 12 and Q 13 is accomplished.

Period from t 2 to t 3

In the period from t 2 to t 3 , the switching elements Q 12 and Q 13 and the switching elements Q 21 and Q 24 are ON, and the switching elements Q 11 and Q 14 and the switching elements Q 22 and Q 23 are OFF. In this case, as illustrated in FIG. 5 , current flows in order from the DC power supply E 1 to the switching element Q 12 , the inductor L, the switching element Q 21 , the DC power supply E 2 , the switching element Q 24 , and the switching element Q 13 . That is, the DC power supplies E 1 and E 2 are charged. The power supply voltages of the DC power supplies E 1 and E 2 are applied to the inductor L in the opposite direction to the direction in the case of FIG. 3A , and the inductor current I L decreases as illustrated in FIG. 2 .

Period from t 3 to t 0

The period from t 3 to t 0 can be described in the same manner as the operation in the period from t 1 to t 2 . At timing t 3 , the switching elements Q 21 and Q 24 are turned off by ZVS, and the switching elements Q 22 and Q 23 are turned on by ZVS. At timing t 0 , the switching elements Q 11 and Q 14 are turned on by ZVS, and the switching elements Q 12 and Q 13 are turned off by ZVS.

As described above, in the DC-DC converter 1 , each of the switching elements Q 11 to Q 14 and Q 21 to Q 24 can be turned on and off by ZVS. This reduces switching losses and suppresses a reduction in the efficiency of power transfer.

3. Conditions for ZVS at Turn-On

Hereinafter, conditions for accomplishing ZVS will be described in detail.

3.1. Conditions for Inductor Current I L

As described above, for example if the drain-source voltages of the switching elements Q 11 to Q 14 targeted for switching become zero after the capacitors C 11 to C 14 are charged or discharged by the inductor L during the dead time at timing t 2 , the switching elements Q 11 to Q 14 can be turned on and off by ZVS. That is, the ZVS of the switching elements Q 11 to Q 14 can be accomplished if the energy of the inductor L is at least greater than or equal to the total energy stored in the capacitors C 11 to C 14 .

The aforementioned condition is satisfied if Expression (1) below holds true:

½ LI L 2 ≥½·4 CV x 2   (1)

where L is the inductance of the inductor L, C is the capacitance of each of the capacitors C 11 to C 14 , and Vx is the power supply voltage of the DC power supply E 1 (see FIG. 1 ). Expression 1 is converted into Expression 2 below. In Expression 2, α is a correction coefficient that is set to an appropriate value as necessary. Assume that α=1 in the following description.

In Expression 2, α·Vx √(4C/L) represents a threshold current I ref . If |I L |≥|I ref | during the dead time at timing t 2 and at timing t 0 , the ZVS of each of the switching elements Q 11 to Q 14 becomes possible.

FIG. 2 illustrates the waveforms when Vx=Vy. Since V 1 (t 1 )=V 2 (t 2 ), the inductor current I L at timing t 1 is equal to the inductor current I L at timing t 2 , and the inductor current I L at timing t 3 is equal to the inductor current I L at timing t 0 . Therefore, if |I L |≥|I ref | at timing t 0 and at timing t 2 , |I L |≥|I ref | also holds true during the dead time at timing t 1 and at timing t 3 . Accordingly, the ZVS of the switching elements Q 21 to Q 24 also becomes possible.

In contrast, when Vx≠Vy, i.e., V 1 (t 1 )≠V 2 (t 2 ), more specifically when V 1 (t 1 )>V 2 (t 2 ) or when V 1 (t 1 )<V 2 (t 2 ), a potential difference between the voltages V 1 and V 2 is applied to the inductor L. Thus, the inductor current I L at timing t 1 is different from the inductor current I L at timing t 2 . Also, the inductor current I L at timing t 3 is different from the inductor current I L at timing t 0 .

FIGS. 6A and 6B illustrate the waveforms of the inductor current I L when V 1 (t 1 )≠ V 2 (t 2 ). FIG. 6A illustrates the waveform of the inductor current I L when V 1 (t 1 )>V 2 (t 2 ), and FIG. 6B illustrates the waveform of the inductor current I L when V 1 (t 1 )<V 2 (t 2 ).

When V 1 (t 1 )>V 2 (t 2 ), the inductor current I L at timing t 1 (hereinafter, referred to as I L(t1) ) is smaller than the inductor current I L at timing t 2 as illustrated in FIG. 6A . In this case, if |I L(t1) |≥|I ref | is satisfied, the ZVS of the switching elements Q 11 to Q 14 and Q 21 to Q 24 becomes possible.

When V 1 (t 1 )<V 2 (t 2 ), the inductor current I L at timing t 2 (hereinafter, referred to as I L(t2) ) is smaller than the inductor current I L at timing t 1 as illustrated in FIG. 6B . In this case, if |I L(t2) |≥|I ref | is satisfied, the ZVS of the switching elements Q 11 to Q 14 and Q 21 to Q 24 becomes possible.

As described above, the ZVS of the switching elements Q 11 to Q 14 and Q 21 to Q 24 becomes possible if appropriate settings are made so as to pass the inductor current IL greater than or equal to the threshold current Tref through the inductor L, irrespective of the voltages Vx and Vy.

3.2. First Control and Second Control

The control circuit 30 controls the switching of the switching elements Q 11 to Q 14 such that the output power of the DC-DC converter 1 follows a set command value. In the case of performing switching control in accordance with the command value, the control circuit 30 switches between first control and second control and performs the first or second control in order to satisfy the above-described condition |I L |≥|I ref |.

Power P T obtained in the process of causing the output power to follow the command value is expressed by Expression 3 below. In Expression 3, Vy is the power supply voltage (see FIG. 1 ) of the DC power supply E 2 , n is the turns ratio between the first winding n 1 and the second winding n 2 . The power P T is hereinafter referred to as target power.

In Expression 3, ω is the drive angular frequency and ω=2πf as expressed by the aforementioned switching frequency f, and δ is the phase difference between the switching elements Q 12 , Q 13 and the switching elements Q 22 , Q 23 , i.e., the phase difference between the voltage V 1 and the voltage V 2 .

FIG. 7 is a diagram for describing the first control and the second control. The horizontal axis in FIG. 7 indicates the target power P T . In FIG. 7 , td is a time difference [μs] that is equivalent to the phase difference (δ in FIG. 2 ) between the voltages V 1 and V 2 , and td=δ/ω=L·I L /Vx.

As illustrated in FIG. 7 , when the target power P T is greater than power Pb, the control circuit 30 performs the first control. In the first control, the control circuit 30 performs phase shift control for changing the phase difference δ while keeping the switching frequency f (drive angular frequency ω) constant.

FIG. 8 illustrates the waveforms of the voltages V 1 and V 2 and the inductor current I L in the first control. The solid lines in FIG. 8 indicate the waveforms before a phase change, and the broken lines indicate the waveforms after the phase change. The phase after the phase change is expressed by δ 1 (<δ).

As is apparent from Expression 3, the phase difference δ between the first full-bridge circuit 10 and the second full-bridge circuit 20 is changed in order to change the target power P T . That is, in the case of lowering the target power P T , the control circuit 30 reduces the phase difference δ between the first full-bridge circuit 10 and the second full-bridge circuit 20 . In the case of raising the target power P T , the control circuit 30 increases the phase difference δ between the first full-bridge circuit 10 and the second full-bridge circuit 20 . Since td=δ/ω=LI L /Vx, the time difference td and the inductor current I L also decrease with decreasing phase difference δ.

The power Pb is set such that, even in the above case, the inductor current I L , which decreases with the phase difference δ, does not fall below the threshold current I ref . That is, in the first control, the control circuit 30 changes the phase difference δ in a range in which the inductor current I L does not fall below the threshold current I ref . Accordingly, the ZVS of the switching elements Q 11 to Q 14 and Q 21 to Q 24 becomes possible.

As illustrated in FIG. 7 , when the target power P T is smaller than the power Pb, the control circuit 30 performs the second control. In the second control, the control circuit 30 performs frequency conversion control for changing the switching frequency f (drive angular frequency ω) while keeping the time difference td constant.

FIG. 9 illustrates the waveforms of the voltages V 1 and V 2 and the inductor current I L in the second control. The solid lines in FIG. 9 indicate the waveforms before a frequency change, and the broken lines indicate the waveforms after the frequency change. The switching frequency after the frequency change is expressed by f 1 (<f).

Since td=δ/ω, Expression 3 can be converted into Expression 4 below:

As is apparent from Expression 4, the drive angular frequency ω (i.e., switching frequency f) is changed in order to change the target power P T . In order to reduce the target power P T from the power Pb, the drive angular frequency ω is increased. Since td=δ/ω=LI L /Vx and td is kept constant, the phase difference δ also increases with increasing drive angular frequency ω. In this case, the inductor current I L remains constant without falling below the threshold current I ref . Therefore, in the second control, |I L |≥|I ref | is maintained even if the switching frequency f is changed. Accordingly, the ZVS of the switching elements Q 11 to Q 14 becomes possible.

In the second control, the drive angular frequency w is set by Expression 5 below:

As described above, by performing the first control or the second control depending on the target power P T , the control circuit 30 can enlarge the area where ZVS can be performed. In particular, the first control is performed in the area where there is no need to change the switching frequency f. This suppresses heat generation in the inductor L (transformer T) or magnetic saturation, caused by a change in the switching frequency f.

4. Variations

While one embodiment of the present invention has been described thus far, the present invention is not intended to be limited to the above-described embodiment.

The above-described embodiment is explained, assuming that the input/output terminals IO 11 and IO 12 are on the input side and the input/output terminals IO 21 and IO 22 are on the output side. However, the DC-DC converter 1 is capable of bidirectional power transfer. Therefore, the input/output terminals IO 11 and IO 12 may be on the output side, and the input/output terminals IO 21 and IO 22 may be on the input side. This case can be described in the same manner as in the above-described embodiment, and therefore description thereof is omitted. Note that the DC-DC converter 1 does not necessarily have to be a bidirectional converter.

In the above-described embodiment, the switching frequency f is changed in the second control, but another third control may be performed. The third control employs a duty control method. For example, a phase difference between a drive signal for the switching elements Q 11 and Q 12 and a drive signal for the switching elements Q 13 and Q 14 is changed, or a phase difference between a drive signal for the switching elements Q 21 and Q 22 and a drive signal for the switching elements Q 23 and Q 24 is changed. Although the time difference td is kept constant in the second control, the time difference td may be caused to fluctuate.

Each element in the above-described embodiment and variations may be combined appropriately within a range in which no contradictions arise.

While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore to be understood that numerous modifications and variations can be devised without departing from the scope of the invention.

1 DC-DC converter

10 First full-bridge circuit

20 Second full-bridge circuit

30 Control circuit

C 11 , C 12 , C 13 , C 14 Capacitor

C 21 , C 22 , C 23 , C 24 Capacitor

D 11 , D 12 , D 13 , D 14 Diode

D 21 , D 22 , D 23 , D 24 Diode

E 1 DC power supply

E 2 DC power supply

IO 11 Input/output terminal

IO 12 Input/output terminal

IO 21 Input/output terminal

IO 22 Input/output terminal

L Inductor

L 1 Inductor

Q 11 , Q 12 , Q 13 , Q 14 Switching element

Q 21 , Q 22 , Q 23 , Q 24 Switching element

T Transformer

Vx Power supply voltage

Vy Power supply voltage

V 1 Voltage

V 2 Voltage

n 1 First winding

n 2 Second winding