Semiconductor device

This application is a U.S. National Phase of International Patent Application No. PCT/JP2018/014585 filed on Apr. 5, 2018, which claims priority benefit of Japanese Patent Application No. JP 2017-104176 filed in the Japan Patent Office on May 26, 2017. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety.

The present disclosure relates to a semiconductor device that is able to store information.

In recent years, attention has been paid to, for example, a nonvolatile memory device using a resistance change memory that is able to perform data access at a higher speed than a flash memory. For example, PTL 1 discloses a memory device in which a plurality of row electrodes coupled to row drivers different from one another are arranged side by side in one region, and a plurality of column electrodes coupled to column drivers different from one another are arranged side by side in one region.

Patent Literature

PTL 1: U.S. Patent Application Publication No. 2014/0104968

Incidentally, it is generally desired for a semiconductor device to have a simplified layout. By simplifying the layout in this manner, for example, the layout is expected to be facilitated, and, for example, a circuit operation is expected to be simplified.

It is desirable to provide a semiconductor device that makes it possible to simplify a layout.

A semiconductor device according to an embodiment of the present disclosure includes a plurality of first selection lines, a plurality of second selection lines, a plurality of third selection lines, a plurality of fourth selection lines, a first coupling part, a second coupling part, a third coupling part, a fourth coupling part, a driver, a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The plurality of first selection lines is provided in the first region, extends in a first direction, and is aligned in a second direction that intersects the first direction. The plurality of second selection lines is provided in a second region having a portion that overlaps a portion of the first region, extends in the second direction, and is aligned in the first direction. The plurality of third selection lines is provided in a third region having a portion that overlaps a portion of the second region, extends in the first direction, and is aligned in the second direction. The plurality of fourth selection lines is provided in a fourth region having one portion that overlaps a portion of the first region and having another portion that overlaps a portion of the third region, extends in the second direction, and is aligned in the first direction. The first coupling part is coupled to the plurality of first selection lines at a portion, of the first region, other than ends in the first direction. The second coupling part is coupled to the plurality of second selection lines at a portion, of the second region, other than ends in the second direction. The third coupling part is coupled to the plurality of third selection lines at a portion, of the third region, other than ends in the first direction. The fourth coupling part is coupled to the plurality of fourth selection lines at a portion, of the fourth region, other than ends in the second direction. The driver drives the plurality of first selection lines, the plurality of second selection lines, the plurality of third selection lines, and the plurality of fourth selection lines, respectively, through the first coupling part, the second coupling part, the third coupling part, and the fourth coupling part. The first memory cell is interposed between one of the plurality of first selection lines and one of the plurality of fourth selection lines. The second memory cell is interposed between one of the plurality of second selection lines and one of the plurality of first selection lines. The third memory cell is interposed between one of the plurality of third selection lines and one of the plurality of second selection lines. The fourth memory cell is interposed between one of the plurality of fourth selection lines and one of the plurality of third selection lines.

In the semiconductor device according to an embodiment of the present disclosure, a plurality of first selection lines extends in a first direction and is aligned in a second direction that intersects the first direction, in a first region; a plurality of second selection lines extends in the second direction and is aligned in the first direction, in a second region having a portion that overlaps a portion of the first region; a plurality of third selection lines extends in the first direction and is aligned in the second direction, in a third region having a portion that overlaps a portion of the second region; and a plurality of fourth selection lines extends in the second direction and is aligned in the first direction, in a fourth region having one portion that overlaps a portion of the first region and having another portion that overlaps a portion of the third region. The plurality of first selection lines is coupled to the first coupling part at a portion, of the first region, other than ends in the first direction; the plurality of second selection lines is coupled to a second coupling part at a portion, of the second region, other than ends in the second direction; the plurality of third selection lines is coupled to a third coupling part at a portion, of the third region, other than ends in the first direction; and the plurality of fourth selection lines is coupled to a fourth coupling part at a portion, of the fourth region, other than ends in the second direction. The plurality of first selection lines, the plurality of second selection lines, the plurality of third selection lines, and the plurality of fourth selection lines are driven by a driver, respectively, through the first coupling part, the second coupling part, the third coupling part, and the fourth coupling part. A first memory cell is interposed between one of the plurality of first selection lines and one of the plurality of fourth selection lines; a second memory cell is interposed between one of the plurality of second selection lines and one of the plurality of first selection lines; a third memory cell is interposed between one of the plurality of third selection lines and one of the plurality of second selection lines; and a fourth memory cell is interposed between one of the plurality of fourth selection lines and one of the plurality of third selection lines.

According to the semiconductor device in an embodiment of the present disclosure, the plurality of first selection lines extending in the first direction and aligned in the second direction is provided in the first region, and the plurality of first selection lines is coupled to the first coupling part at a portion, of the first region, other than ends in the first direction; the plurality of second selection lines extending in the second direction and aligned in the first direction is provided in the second region, and the plurality of second selection lines is coupled to the second coupling part at a portion, of the second region, other than ends in the second direction; the plurality of third selection lines extending in the first direction and aligned in the second direction is provided in the third region, and the plurality of third selection lines is coupled to the third coupling part at a portion, of the third region, other than ends in the first direction; and the plurality of fourth selection lines extending in the second direction and aligned in the first direction is provided in the fourth region, and the plurality of fourth selection lines is coupled to the fourth coupling part at a portion, of the fourth region, other than ends in the second direction. This makes it possible to simplify the layout. It is to be noted that the effects described herein are not necessarily limitative, and any of the effects described in the present disclosure may be provided.

FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device according to an embodiment of the present disclosure.

FIG. 2 is a block diagram illustrating a configuration example of a memory section illustrated in FIG. 1 .

FIG. 3 is a perspective view of a configuration example of row selection lines and column selection lines according to a first embodiment.

FIG. 4 is a circuit diagram illustrating a configuration example of a memory cell illustrated in FIG. 3 .

FIG. 5 is a characteristic diagram illustrating an example of characteristics of a storage element illustrated in FIG. 3 .

FIG. 6 is an explanatory diagram illustrating an example of a layer configuration of a semiconductor device according to the first embodiment.

FIG. 7 is an explanatory diagram illustrating a configuration example of the row selection lines according to the first embodiment.

FIG. 8 is another explanatory diagram illustrating a configuration example of the row selection lines according to the first embodiment.

FIG. 9 is an explanatory diagram illustrating a configuration example of the column selection lines according to the first embodiment.

FIG. 10 is another explanatory diagram illustrating a configuration example of the column selection lines according to the first embodiment.

FIG. 11 is an explanatory diagram illustrating a configuration example of the row selection lines and the column selection lines according to the first embodiment.

FIG. 12 is an explanatory diagram illustrating a configuration example of the row control lines and the column control lines in a memory section according to the first embodiment.

FIG. 13 is an explanatory diagram illustrating a configuration example of row selection lines according to a comparative example.

FIG. 14 is an explanatory diagram illustrating a configuration example of column selection lines according to the comparative example.

FIG. 15A is an explanatory diagram illustrating a configuration example of the memory section according to an embodiment.

FIG. 15B is another explanatory diagram illustrating a configuration example of the memory section according to an embodiment.

FIG. 15C is another explanatory diagram illustrating a configuration example of the memory section according to an embodiment.

FIG. 16 is an explanatory diagram illustrating a configuration example of row selection lines according to another comparative example.

FIG. 17 is an explanatory diagram illustrating a configuration example of column selection lines according to the other comparative example.

FIG. 18 is an explanatory diagram illustrating a configuration example of the row selection lines and the column selection lines according to the other comparative example.

FIG. 19 is an explanatory diagram illustrating an example of a layer configuration of a semiconductor device according to a modification example of the first embodiment.

FIG. 20 is an explanatory diagram illustrating a configuration example of row selection lines according to the modification example of the first embodiment.

FIG. 21 is an explanatory diagram illustrating a configuration example of column selection lines according to the modification example of the first embodiment.

FIG. 22 is another explanatory diagram illustrating a configuration example of the column selection lines according to the modification example of the first embodiment.

FIG. 23 is another explanatory diagram illustrating a configuration example of the column selection lines according to the modification example of the first embodiment.

FIG. 24 is a perspective view of a configuration example of row selection lines and column selection lines according to a second embodiment.

FIG. 25 is an explanatory diagram illustrating an example of a layer configuration of a semiconductor device according to the second embodiment.

FIG. 26 is an explanatory diagram illustrating a configuration example of the row selection lines according to the second embodiment.

FIG. 27 is another explanatory diagram illustrating a configuration example of the row selection lines according to the second embodiment.

FIG. 28 is another explanatory diagram illustrating a configuration example of the row selection lines according to the second embodiment.

FIG. 29 is an explanatory diagram illustrating a configuration example of the column selection lines according to the second embodiment.

FIG. 30 is another explanatory diagram illustrating a configuration example of the column selection lines according to the second embodiment.

FIG. 31 is an explanatory diagram illustrating a configuration example of the row selection lines and the column selection lines according to the second embodiment.

FIG. 32 is an explanatory diagram illustrating a configuration example of the row control lines and the column control lines in a memory section according to the second embodiment.

FIG. 33 is a perspective view of a configuration example of row selection lines and column selection lines according to a third embodiment.

FIG. 34 is an explanatory diagram illustrating an example of a layer configuration of a semiconductor device according to the third embodiment.

FIG. 35 is an explanatory diagram illustrating a configuration example of the row selection lines according to the third embodiment.

FIG. 36 is another explanatory diagram illustrating a configuration example of the row selection lines according to the third embodiment.

FIG. 37 is another explanatory diagram illustrating a configuration example of the row selection lines according to the third embodiment.

FIG. 38 is an explanatory diagram illustrating a configuration example of the column selection lines according to the third embodiment.

FIG. 39 is another explanatory diagram illustrating a configuration example of the column selection lines according to the third embodiment.

FIG. 40 is another explanatory diagram illustrating a configuration example of the column selection lines according to the third embodiment.

FIG. 41 is an explanatory diagram illustrating a configuration example of the row selection lines and the column selection lines according to the third embodiment.

FIG. 42 is an explanatory diagram illustrating a configuration example of the row control lines and the column control lines in a memory section according to the third embodiment.

FIG. 43 is a perspective view of a configuration example of row selection lines and column selection lines according to a modification example of the third embodiment.

FIG. 44 is an explanatory diagram illustrating an example of a layer configuration of a semiconductor device according to the modification example of the third embodiment.

Hereinafter, description is given in detail of embodiments of the present disclosure with reference to the drawings. It is to be note that the description is given in the following order.

1. First embodiment (An example in which one storage layer is included)

2. Second embodiment (An example in which two storage layers are included)

3. Third Embodiment (An example in which three or more storage layers are included)

1. First Embodiment

Configuration Example

FIG. 1 illustrates a configuration example of a semiconductor device (semiconductor device 1 ) according to a first embodiment. The semiconductor device 1 includes a logic circuit section 10 , a memory section 20 , and a peripheral circuit section 90 . The logic circuit section 10 includes a logic circuit. It is to be noted that this is not limitative; the logic circuit section 10 may include, for example, a static random access memory (SRAM) circuit. The memory section 20 is a so-called cross-point memory, and is a nonvolatile memory. The memory section 20 stores, for example, information to be handled by the logic circuit section 10 . The peripheral circuit section 90 includes various circuits related to an operation of the memory section 20 . Specifically, the peripheral circuit section 90 includes, for example, a power supply circuit that generates a selection voltage Vsel and a non-selection voltage Vinh, which are described later, and a reference voltage generation circuit that generates a reference voltage Vref to be used when performing a reading operation. It is to be noted that this is not limitative; the peripheral circuit section 90 may further include, for example, an oscillation circuit and a delay circuit that define an operation speed and an operation timing of the memory section 20 . In addition, the peripheral circuit section 90 may include, for example, a temperature sensor that measures a temperature in the memory section 20 , and an AD converter that converts voltages (analog values) of various nodes in the memory section 20 into digital codes. In this case, the logic circuit section 10 may perform various types of processing on the basis of the temperature and the digital code. In the semiconductor device 1 , a logic circuit and a nonvolatile memory are mounted together (embedded) in this manner.

(Memory Section 20 )

FIG. 2 illustrates a configuration example of the memory section 20 . The memory section 20 includes a plurality of row controllers 21 , a plurality of column controllers 22 , a plurality of row selection line drivers (RLD) 23 (row selection line drivers (RLD) 231 and 232 ), and a plurality of column selection line drivers (CLD) 24 (column selection line drivers (CLD) 241 and 242 ). In FIG. 2 , a plurality of column selection line drivers (CLD) 24 , out of a plurality of row selection line drivers (RLD) 23 and the plurality of column selection line drivers (CLD) 24 , are drawn with thick lines.

In the memory section 20 , the plurality of row selection line drivers (RLD) 23 and the plurality of column selection line drivers (CLD) 24 are arranged in a checkerboard shape. Specifically, in this example, the row selection line driver (RLD) 231 and the column selection line driver (CLD) 241 are arranged adjacent to each other in the X-direction, and the column selection line driver (CLD) 242 and the row selection line driver (RLD) 232 are arranged adjacent to each other in the X-direction. Further, the row selection line driver (RLD) 231 and the column selection line driver (CLD) 242 are arranged adjacent to each other in the Y-direction, and the column selection line driver (CLD) 241 and the row selection line driver (RLD) 232 are arranged adjacent to each other in the Y-direction.

Each of the row controllers 21 generates a selection control signal SELRL on the basis of a row address signal ADRRL and a mode signal MD. The row address signal ADRRL designates a row address of a memory cell MC (described later) to be subjected to a writing operation or a reading operation. The mode signal MD commands an operation such as a writing operation and a reading operation. The same row address signal ADRRL and the same mode signal MD are supplied to each of the plurality of row controllers 21 . Further, each of the row controllers 21 supplies the generated selection control signal SELRL to the plurality of row selection line drivers (RLD) 23 through row control lines CRL (row control lines CRL 1 and CRL 2 ) extending in the Y-direction. Specifically, each of the row controllers 21 supplies a selection control signal SELRL 1 included in the selection control signal SELRL to the plurality of row selection line drivers (RLD) 231 coupled to the row control line CRL 1 through the row control line CRL 1 , and supplies a selection control signal SELRL 2 included in the selection control signal SELRL to the plurality of row selection line drivers (RLD) 232 coupled to the row control line CRL 2 through the row control line CRL 2 .

Each of the column controllers 22 generates a selection control signal SELCL on the basis of a column address signal ADRCL and the mode signal MD. The column address signal ADRCL designates a column address of the memory cell MC (described later) to be subjected to the writing operation or the reading operation. The same column address signal ADRCL and the same mode signal MD are supplied to each of the plurality of column controllers 22 . Further, each of the column controllers 22 supplies the generated selection control signal SELCL to the plurality of column selection line drivers (CLD) 24 through column control lines CCL (column control lines CCL 1 and CCL 2 ) extending in the X-direction. Specifically, each of the column controllers 22 supplies a selection control signal SELCL 1 included in the selection control signal SELCL to the plurality of column selection line drivers (CLD) 241 coupled to the column control line CCL 1 through the column control line CCL 1 , and supplies a selection control signal SELCL 2 included in the selection control signal SELCL to the plurality of column selection line drivers (CLD) 242 coupled to the column control line CCL 2 through the column control line CCL 2 .

Each of the row selection line drivers (RLD) 23 drives a row selection line RL (described later) on the basis of the selection control signal SELRL. Specifically, the row selection line driver (RLD) 231 drives the row selection line RL (described later) on the basis of the selection control signal SELRL 1 supplied through the row control line CRL 1 . Further, the row selection line driver (RLD) 232 drives the row selection line RL (described later) on the basis of the selection control signal SELRL 2 supplied through the row control line CRL 2 . Further, the row selection line drivers (RLD) 231 and 232 are each coupled to an unillustrated sense amplifier. As described later, the sense amplifier performs a reading operation by comparing a voltage generated in the memory cell MC (described later) with a reference voltage Vref.

Each of the column selection line drivers (CLD) 24 drives a column selection line CL (described later) on the basis of the selection control signal SELCL. Specifically, the column selection line driver (CLD) 241 drives the column selection line CL (described later) on the basis of the selection control signal SELCL 1 supplied through the column control line CCL 1 . Further, the column selection line driver (CLD) 242 drives the column selection line CL (described later) on the basis of the selection control signal SELCL 2 supplied through the column control line CCL 2 .

FIG. 3 illustrates a configuration example of the memory section 20 . The memory section 20 includes a plurality of row selection lines RL, a plurality of column selection lines CL, and a plurality of memory cells MC.

The plurality of row selection lines RL is so formed as to extend in the X-direction and to be aligned in the Y-direction in a X-Y plane parallel to a substrate surface S of a semiconductor substrate. The plurality of column selection lines CL is so formed as to extend in the Y-direction and to be aligned in the X-direction in the X-Y plane. The plurality of column selection lines CL is formed in a layer above a layer in which the plurality of row selection lines RL is formed. This configuration allows the plurality of row selection lines RL and the plurality of column selection lines CL to intersect each other. The plurality of memory cells MC is formed in a storage layer between the layer in which the plurality of row selection lines RL is formed and the layer in which the plurality of column selection lines CL is formed.

FIG. 4 illustrates a configuration example of the memory cell MC. The memory cell MC includes a storage element VR, a selection element SE, and terminals TU and TL.

The storage element VR is a resistance change storage element, and a resistance state RS reversibly changes in accordance with polarity of a voltage difference between voltages applied across both ends. In other words, the resistance state RS of the storage element VR reversibly changes in accordance with a direction of a current flowing between both ends. It is possible to use, as the storage element VR, a stack of an ion source layer and a resistance change layer, for example. One end of the storage element VR is coupled to the terminal TU of the memory cell MC, and another end thereof is coupled to one end of the selection element SE.

FIG. 5 schematically illustrates distribution of resistance values of the storage element VR. The storage element VR may have two distinguishable resistance states RS (a high resistance state HRS and a low resistance state LRS). In this example, the high resistance state HRS is associated with data “0”, and the low resistance state LRS is associated with data “1”, for example. That is, the storage element VR functions as a storage element that stores 1-bit data. For example, changing from the high resistance state HRS to the low resistance state LRS is referred to as “set”, and changing from the low resistance state LRS to the high resistance state HRS is referred to as “reset”.

The selection element SE ( FIG. 4 ) has bidirectional diode characteristics. Specifically, the selection element SE is brought into an electrically conductive state (ON state) in a case where an absolute value of the voltage difference of the voltage applied between both ends is larger than a predetermined voltage difference; the selection element SE is brought into a non-electrically conductive state (OFF state) in a case where the absolute value of the voltage difference is smaller than the predetermined voltage difference. The one end of the selection element SE is coupled to the other end of the storage element VR, and another end thereof is coupled to the TL terminal of the memory cell MC.

The terminal TU is a terminal coupled to a selection line above the storage layer in which the memory cell MC is formed, and the terminal TL is a terminal coupled to a selection line under the storage layer in which the memory cell MC is formed. In this example, as illustrated in FIG. 3 , the terminal TU of the memory cell MC is coupled to any one of the plurality of column selection lines CL, and the terminal TL is coupled to any one of the plurality of row selection lines RL.

In a case where the memory cell MC is set, the selection voltage Vsel of 6V, for example, is applied to the terminal TU, and the selection voltage Vsel of 0V, for example, is applied to the terminal TL. As a result, the selection element SE is brought into an ON state; as illustrated in FIG. 4 , a set current Iset flows from the terminal TU toward the terminal TL, and the storage element VR is set. In a case where the memory cell MC is reset, the selection voltage Vsel of 6V, for example, is applied to the terminal TL, and the selection voltage Vsel of 0V, for example, is applied to the terminal TU. As a result, the selection element SE is brought into an ON state; a reset current Irst flows from the terminal TL toward the terminal TU, and the storage element VR is reset. In addition, in a case where a reading operation is performed on the memory cell MC, the selection voltage Vsel of 5V, for example, is applied to the terminal TU, and the selection voltage Vsel of 1V, for example, is applied to the terminal TL. As a result, a sense current Isns flows from the terminal TU toward the terminal TL. Further, an unillustrated sense amplifier coupled to the row selection driver (RLD) 23 compares a voltage generated in the memory cell MC and the reference voltage Vref with each other to thereby determine the resistance state RS of the storage element VR.

In the memory section 20 , the selection voltage Vsel is applied to each of the row selection line RL and the column selection line CL, whereby the memory cell MC is selected, and a writing operation (set or reset) or a reading operation is performed. In the memory section 20 , as illustrated in FIG. 2 , the same row address signal ADRRL and the same mode signal MD are supplied to the plurality of row controllers 21 , and the same column address signal ADRCL and the same mode signal MD are supplied to the plurality of column controllers 22 . Accordingly, for example, the selection voltage Vsel is applied to the corresponding plurality of row selection lines RL, and the selection voltage Vsel is applied to the corresponding plurality of column selection lines CL. It is to be noted that the non-selection voltage Vinh is applied to other row selection lines RL and other column selection lines CL. As a result, the plurality of memory cells MC is selected in the memory section 20 , and a writing operation and a reading operation are simultaneously performed in each of the memory cells MC.

FIG. 6 illustrates an example of a layer configuration in the semiconductor device 1 . In this example, the semiconductor device 1 includes six wiring layers L 1 to L 6 . The six wiring layers L 1 to L 6 are formed on the substrate surface S in this order, with respective insulating layers interposed therebetween.

In the logic circuit section 10 , metal wiring lines M 1 to M 6 are formed in the wiring layers L 1 to L 6 , respectively. Of the six metal wiring lines M 1 to M 6 , wiring lines adjacent to each other are coupled to each other through a via VA. In addition, the metal wiring line M 1 of the wiring layer L 1 is coupled to an element (such as a transistor TR) formed on the semiconductor substrate through a contact CT.

In the memory section 20 , the metal wiring lines M 1 , M 2 , M 5 , and M 6 are formed in the wiring layers L 1 , L 2 , L 5 , and L 6 , respectively. The metal wiring lines M 1 and M 2 are used for local wiring lines in the row selection line driver (RLD) 23 and the column selection line driver (CLD) 24 , for example. The metal wiring line M 5 is used, for example, for the column control line CCL (column control lines CCL 1 and CCL 2 ), and the metal wiring line M 6 is used, for example, for the row control line CRL (row control lines CRL 1 and CRL 2 ). In addition, in the memory section 20 , the row selection line RL is formed in the wiring layer L 3 , and the column selection line CL is formed in the wiring layer L 4 . The line width of the row selection line RL is, for example, the same as the line width of the metal wiring line M 3 , and the line width of the column selection line CL is, for example, the same as the line width of the metal wiring line M 4 . It is to be noted that this is not limitative; for example, the line width of the row selection line RL may be narrower than the line width of the metal wiring line M 3 , for example, or the line width of the column selection line CL may be narrower than the line width of the metal wiring line M 4 , for example.

(Row Selection Line RL)

FIGS. 7 and 8 each illustrate an example of the row selection lines RL. As illustrated in FIG. 7 , each of the plurality of row selection lines RL is coupled to a coupling part 13 (coupling parts 131 and 132 ) near the middle in an extending direction (X-direction) of the row selection line RL. In addition, each of the row selection line drivers (RLD) 231 is coupled to the coupling part 131 near the middle of the row selection line driver (RLD) 231 in the X-direction, and each of the row selection line drivers (RLD) 232 is coupled to the coupling part 132 near the middle of the row selection line driver (RLD) 232 in the X-direction. As a result, the row selection line driver (RLD) 231 is coupled to the plurality of row selection lines RL through the coupling part 131 , and the row selection line driver (RLD) 232 is coupled to the plurality of row selection lines RL through the coupling part 132 . It is to be noted that, in this example, each of the coupling parts 131 and 132 includes two coupling parts adjacent to each other in the Y-direction, as illustrated in FIG. 7 . As illustrated in FIG. 8 , the coupling part 131 includes the contact CT, the metal wiring line M 1 , the via VA between the wiring layers L 1 and L 2 , the metal wiring line M 2 , and the via VA between the wiring layers L 2 and L 3 . The same holds true also for the coupling part 132 .

One row selection line driver (RLD) 231 is coupled to a plurality of (512 in this example) row selection lines RL, for example. In FIG. 7 , the right ends of the row selection lines RL coupled to the row selection line driver (RLD) 231 are located near the middle in the X-direction of the column selection line driver (CLD) 241 on right side of the row selection line driver (RLD) 231 . In addition, the left ends of the row selection lines RL coupled to the row selection line driver (RLD) 231 are located near the middle in the X-direction of the column selection line driver (CLD) 241 on left side of the row selection line driver (RLD) 231 .

Likewise, one row selection line driver (RLD) 232 is coupled to a plurality of (512 in this example) row selection lines RL. In FIG. 7 , the right ends of the row selection lines RL coupled to the row selection line driver (RLD) 232 are located near the middle in the X-direction of the column selection line driver (CLD) 242 on right side of the row selection line driver (RLD) 232 . In addition, the left ends of the row selection lines RL coupled to the row selection line driver (RLD) 232 are located near the middle in the X-direction of the column selection line driver (CLD) 242 on left side of the row selection line driver (RLD) 232 .

The plurality of row selection line drivers (RLD) 23 and the plurality of column selection line drivers (CLD) 24 are arranged in a checkerboard shape, and thus the plurality of row selection lines RL coupled to the row selection line driver (RLD) 231 and the plurality of row selection lines RL coupled to the row selection line driver (RLD) 232 are staggered from each other in the X-direction.

(Column Selection Line CL)

FIGS. 9 and 10 each illustrate an example of the column selection lines CL. As illustrated in FIG. 9 , each of the plurality of column selection lines CL is coupled to a coupling part 14 (coupling parts 141 and 142 ) near the middle of an extending direction (Y-direction) of the column selection line CL. In addition, each of the column selection line drivers (CLD) 241 is coupled to the coupling part 141 near the middle of the column selection line driver (CLD) 241 in the Y-direction, and each of the column selection line drivers (CLD) 242 is coupled to the coupling part 142 near the middle of the column selection line driver (CLD) 242 in the Y-direction. As a result, the column selection line driver (CLD) 241 is coupled to the plurality of column selection lines CL through the coupling part 141 , and the column selection line driver (CLD) 242 is coupled to the plurality of column selection lines CL through the coupling part 142 . It is to be noted that, in this example, each of the coupling parts 141 and 142 includes two coupling parts adjacent to each other in the X-direction, as illustrated in FIG. 9 . As illustrated in FIG. 10 , the coupling part 141 includes the contact CT, the metal wiring line M 1 , the via VA between the wiring layers L 1 and L 2 , the metal wiring line M 2 , the via VA between the wiring layers L 2 and L 3 , the metal wiring line M 3 , and the via VA between the wiring layers L 3 and L 4 . The same holds true also for the coupling part 142 .

One column selection line driver (CLD) 241 is coupled to a plurality of (512 in this example) column selection lines CL. In FIG. 9 , the upper ends of the column selection lines CL coupled to the column selection line driver (CLD) 241 are located near the middle in the Y-direction of the row selection line driver (RLD) 232 on upper side of the column selection line driver (CLD) 241 . In addition, the lower ends of the column selection lines CL coupled to the column selection line driver (CLD) 241 are located near the middle in the Y-direction of the row selection line driver (RLD) 232 on lower side of the column selection line driver (CLD) 241 .

Likewise, one column selection line driver (CLD) 242 is coupled to a plurality of (512 in this example) column selection lines CL. In FIG. 9 , the upper ends of the column selection lines CL coupled to the column selection line driver (CLD) 242 are located near the middle in the Y-direction of the row selection line driver (RLD) 231 on upper side of the column selection line driver (CLD) 242 . In addition, the lower ends of the column selection lines CL coupled to the column selection line driver (CLD) 242 are located near the middle in the Y-direction of the row selection line driver (RLD) 231 on lower side of the column selection line driver (CLD) 242 .

The plurality of row selection line drivers (RLD) 23 and the plurality of column selection line drivers (CLD) 24 are arranged in a checkerboard shape, and thus the plurality of column selection lines CL coupled to the column selection line driver (CLD) 241 and the plurality of column selection lines CL coupled to the column selection line driver (CLD) 242 are staggered from each other in the Y-direction.

FIG. 11 illustrates an example of the plurality of row selection lines RL and the plurality of column selection lines CL. FIG. 11 depicts the plurality of row selection lines RL illustrated in FIG. 7 and the plurality of column selection lines CL illustrated in FIG. 9 in a superimposed manner.

The row selection line RL extends in the X-direction in the wiring layer L 3 , and the column selection line CL extends in the Y-direction in the wiring layer L 4 , and thus the row selection line RL and the column selection line CL intersect each other. Each of the plurality of row selection lines RL intersects 1024 (=512×2) column selection lines CL in this example, and each of the plurality of column selection lines CL intersects 1024 (=512×2) row selection lines RL in this example. The memory cell MC is formed in a layer between the wiring layer L 3 and the wiring layer L 4 at the intersection. In the memory section 20 , as illustrated in FIG. 11 , a memory array AR including 1M (=1024×1024) memory cells MC is defined. As illustrated in FIG. 7 , the memory array AR includes 512 row selection lines RL coupled to the row selection line driver (RLD) 231 and 512 row selection lines RL coupled to the row selection line driver (RLD) 232 . That is, in this example, in consideration of the row selection line drivers (RLD) 231 and 232 each coupled to an unillustrated sense amplifier, the memory array AR is defined from the viewpoint of a reading operation. As illustrated in FIG. 9 , the column selection lines CL are so formed as to extend across adjacent memory arrays AR.

As illustrated in FIG. 11 , a region corresponding to the row selection line driver (RLD) 231 includes a region (slot region SL 31 ) where the row selection line RL and the column selection line CL are not formed. The slot region SL 31 is located near the middle in the Y-direction of the region corresponding to the row selection line driver (RLD) 231 . Likewise, a region corresponding to the row selection line driver (RLD) 232 includes a region (slot region SL 32 ) where the row selection line RL and the column selection line CL are not formed. The slot region SL 32 is located near the middle in the Y-direction of the region corresponding to the row selection line driver 232 . The slot regions SL 31 and SL 32 are each a rectangular region that is long in the X-direction and short in the Y-direction. In the memory section 20 , as described below, a coupling part CN 31 (described later) that couples the row selection line driver (RLD) 231 and the row control line CRL 1 to each other is formed in the slot region SL 31 , and a coupling part CN 32 (described later) that couples the row selection line driver (RLD) 232 and the row control line CRL 2 to each other is formed in the slot region SL 32 .

Likewise, a region corresponding to the column selection line driver (CLD) 241 includes a region (slot region SL 41 ) where the row selection line RL and the column selection line CL are not formed. The slot region SL 41 is located near the middle in the X-direction of the region corresponding to the column selection line driver (CLD) 241 . Likewise, a region corresponding to the column selection line driver (CLD) 242 includes a region (slot region SL 42 ) where the row selection line RL and the column selection line CL are not formed. The slot region SL 42 is located near the middle in the X-direction of the region corresponding to the column selection line driver (CLD) 242 . The slot regions SL 41 and SL 42 are each a rectangular region that is long in the Y-direction and short in the X-direction. In the memory section 20 , as described below, a coupling part CN 41 (described later) that couples the column selection line driver (CLD) 241 and the column control line CCL 1 to each other is formed in the slot region SL 41 , and a coupling part CN 42 (described later) that couples the column selection line driver (CLD) 242 and the column control line CCL 2 to each other is formed in the slot region SL 42 .

(Row Control Line CRL and Column Control Line CCL)

FIG. 12 illustrates a configuration example of the row control line CRL (row control lines CRL 1 and CRL 2 ) and the column control line CCL (column control lines CCL 1 and CCL 2 ).

The coupling part CN 31 is formed in the slot region SL 31 corresponding to the row selection line driver (RLD) 231 , and the coupling part CN 32 is formed in the slot region SL 32 corresponding to the row selection line driver (RLD) 232 . That is, the coupling part CN 31 is formed near the middle of the row selection line driver (RLD) 231 in the Y-direction, and the coupling part CN 32 is formed near the middle of the row selection line driver (RLD) 232 in the Y-direction.

Likewise, the coupling part CN 41 is formed in the slot region SL 41 corresponding to the column selection line driver (CLD) 241 , and the coupling part CN 42 is formed in the slot region SL 42 corresponding to the column selection line driver (CLD) 242 . That is, the coupling part CN 41 is formed near the middle of the column selection line driver (CLD) 241 in the X-direction, and the coupling part CN 42 is formed near the middle of the column selection line driver (CLD) 242 in the X-direction.

The row control lines CRL 1 and CRL 2 are each formed using, for example, the metal wiring line M 6 of the wiring layer L 6 . The row control line CRL 1 is coupled to the row selection line driver (RLD) 231 through the coupling part CN 31 , and the row control line CRL 2 is coupled to the row selection line driver (RLD) 232 through the coupling part CN 32 . As a result, the row controller 21 supplies the selection control signal SELRL 1 to the plurality of row selection line drivers (RLD) 231 coupled to the row control line CRL 1 through the row control line CRL 1 , and supplies the selection control signal SELRL 2 to the plurality of row selection line drivers (RLD) 232 coupled to the row control line CRL 2 through the row control line CRL 2 .

It is to be noted that, in this example, the selection control signal SELRL 1 is supplied to the row selection line driver (RLD) 231 using the slot region SL 31 , and the selection control signal SELRL 2 is supplied to the row selection line driver (RLD) 232 using the slot region SL 32 ; however, this is not limitative. For example, the slot regions SL 31 and SL 32 may be used to supply power.

The column control lines CCL 1 and CCL 2 are each formed using, for example, the metal wiring line M 5 of the wiring layer L 5 . The column control line CCL 1 is coupled to the column selection line driver (CLD) 241 through the coupling part CN 41 , and the column control line CCL 2 is coupled to the column selection line driver (CLD) 242 through the coupling part CN 42 . As a result, the column controller 22 supplies the selection control signal SELCL 1 to the plurality of column selection line drivers (CLD) 241 coupled to the column control line CCL 1 through the column control line CCL 1 , and supplies the selection control signal SELCL 2 to the plurality of column selection line drivers (CLD) 242 coupled to the column control line CCL 2 through the column control line CCL 2 .

It is to be noted that, in this example, the selection control signal SELCL 1 is supplied to the column selection line driver (CLD) 241 using the slot region SL 41 , and the selection control signal SELCL 2 is supplied to the column selection line driver (CLD) 242 using the slot region SL 42 ; however, this is not limitative. For example, the slot regions SL 41 and SL 42 may be used to supply power.

Here, the plurality of row selection lines RL coupled to the row selection line driver 231 corresponds to a specific example of “a plurality of first selection lines” in the present disclosure. The plurality of column selection lines CL coupled to the column selection line driver 241 corresponds to a specific example of “a plurality of second selection lines” in the present disclosure. The plurality of row selection lines RL coupled to the row selection line driver 232 corresponds to a specific example of “a plurality of third selection lines” in the present disclosure. The plurality of column selection lines CL coupled to the column selection line driver 242 corresponds to a specific example of “a plurality of fourth selection lines” in the present disclosure. The coupling part 131 corresponds to a specific example of a “first coupling part” in the present disclosure. The coupling part 141 corresponds to a specific example of a “second coupling part” in the present disclosure. The coupling part 132 corresponds to a specific example of a “third coupling part” in the present disclosure. The coupling part 142 corresponds to a specific example of a “fourth coupling part” in the present disclosure. The row selection line driver 231 corresponds to a specific example of a “first circuit” in the present disclosure. The column selection line driver 241 corresponds to a specific example of a “second circuit” in the present disclosure. The row selection line driver 232 corresponds to a specific example of a “third circuit” in the present disclosure. The column selection line driver 242 corresponds to a specific example of a “fourth circuit” in the present disclosure. The row controller 21 and the column controller 22 each correspond to a specific example of a “controller” in the present disclosure. The row control line CRL and the column control line CCL each correspond to a specific example of a “control signal line” in the present disclosure. The coupling parts CN 31 and CN 32 each correspond to a specific example of a “control signal coupling part” in the present disclosure.

[Operations and Workings]

Next, description is given of the operations and workings of the semiconductor device 1 of the present embodiment.

(Overview of Overall Operation)

First, description is given of an overview of overall operations of the memory section 20 with reference to FIG. 2 . Each of the row controllers 21 of the memory section 20 generates the selection control signal SELRL (selection control signals SELRL 1 and SELRL 2 ) on the basis of the row address signal ADRRL and the mode signal MD. Each of the column controllers 22 generates the selection control signal SELCL (selection control signals SELCL 1 and SELCL 2 ) on the basis of the column address signal ADRCL and the mode signal MD.

Each of the row selection line drivers (RLD) 231 drives the plurality of (512 in this example) row selection lines RL coupled to the row selection line driver (RLD) 231 on the basis of the selection control signal SELRL 1 . Each of the row selection line drivers (RLD) 232 drives the plurality of (512 in this example) row selection lines RL coupled to the row selection line driver (RLD) 232 on the basis of the selection control signal SELRL 2 .

Each of the column selection line drivers (CLD) 241 drives the plurality of (512 in this example) column selection lines CL coupled to the column selection line driver (CLD) 241 on the basis of the selection control signal SELCL 1 . Each of the column selection line drivers (CLD) 242 drives the plurality of (512 in this example) column selection lines CL coupled to the column selection line driver (CLD) 242 on the basis of the selection control signal SELCL 2 .

(Workings)

In the semiconductor device 1 , as illustrated in FIG. 7 , the row selection line RL is coupled to the row selection line driver (RLD) 23 (row selection line drivers (RLD) 231 and 232 ) through the coupling part 13 (coupling parts 131 and 132 ) near the middle of the extending direction (X-direction) of the row selection line RL. Likewise, in the semiconductor device 1 , as illustrated in FIG. 9 , the column selection line CL is coupled to the column selection line driver (CLD) 24 (column selection line drivers (CLD) 241 and 242 ) through the coupling part 14 (coupling parts 141 and 142 ) near the middle of the extending direction (Y-direction) of the column selection line CL. This makes it possible, in the semiconductor device 1 , to suppress voltage drop in the row selection line RL and the column selection line CL, thus making it possible to reduce a possibility that a write error or a read error may occur in the memory cell MC.

That is, referring, for example to a memory section 20 R illustrated in FIGS. 13 and 14 , the row selection line RL is coupled to a row selection line driver (RLD) 23 R (row selection line drivers (RLD) 231 R and 232 R) through a coupling part 13 R (coupling parts 131 R and 132 R) near the end of the extending direction (X-direction) of the row selection line RL, and the column selection line CL is coupled to a column selection line driver (CLD) 24 R (column selection line drivers (CLD) 241 R and 242 R) through a coupling part 14 R (coupling parts 141 R and 142 R) near the end of the extending direction (Y-direction) of the column selection line CL. In such a case, there is a possibility that the voltage drop in the row selection line RL and the column selection line CL may increase. In this case, when the writing operation is performed on the memory cell MC, it is not possible for the storage element VR to be sufficiently set or reset, thus leading to a possibility that a write error may occur. In addition, when a reading operation is performed on the memory cell MC, there is a possibility that a read error may occur.

Meanwhile, in the memory section 20 according to the present embodiment, the row selection line RL is coupled to the row selection line driver (RLD) 23 through the coupling part 13 near the middle of the extending direction of the row selection line RL, and the column selection line CL is coupled to the column selection line driver (CLD) 24 through the coupling part 14 near the middle of the extending direction of the column selection line CL. This makes it possible to suppress the voltage drop in the row selection line RL and the column selection line CL. As a result, in the semiconductor device 1 , it is possible to reduce the possibility that a write error or a read error may occur.

In addition, in the semiconductor device 1 , as illustrated in FIG. 7 , the row selection line driver (RLD) 231 is coupled to the plurality of row selection lines RL through the coupling part 131 near the middle of the row selection line driver (RLD) 231 in the X-direction, and the row selection line driver (RLD) 232 is coupled to the plurality of row selection lines RL through the coupling part 132 near the middle of the row selection line driver (RLD) 232 in the X-direction. Likewise, in the semiconductor device 1 , as illustrated in FIG. 9 , the column selection line driver (CLD) 241 is coupled to the plurality of column selection lines CL through the coupling part 141 near the middle of the column selection line driver (CLD) 241 in the Y-direction, and the column selection line driver (CLD) 242 is coupled to the plurality of column selection lines CL through the coupling part 142 near the middle of the column selection line driver (CLD) 242 in the Y-direction. This makes it easier, in the semiconductor device 1 , to lay out the row selection line driver (RLD) 23 and the column selection line driver (CLD) 24 .

That is, referring, for example, to the memory section 20 R illustrated in FIGS. 13 and 14 , the row selection line driver (RLD) 23 R (row selection line drivers (RLD) 231 R and 232 R) is coupled to the row selection line RL through the coupling part 13 R (coupling parts 131 R and 132 R) near the end of the row selection line driver (RLD) 23 R in the X-direction, and the column selection line driver (CLD) 24 R (column selection line drivers (CLD) 241 R and 242 R) is coupled to the column selection line CL through the coupling part 14 R (coupling parts 141 R and 142 R) near the end of the column selection line driver (CLD) 24 R in the Y-direction. In such a case, there is a possibility that it may be difficult to lay out the row selection line driver (RLD) 23 and the column selection line driver (CLD) 24 . Specifically, for example, in FIG. 13 , in the row selection line driver (RLD) 231 R, 512 wiring lines are coupled to the coupling part 131 R from right side of the coupling part 131 R, thus causing the wiring lines to be dense near the coupling part 131 R. The same holds true also for the row selection line driver (RLD) 232 R and the column selection line drivers (CLD) 241 R and 242 R.

Meanwhile, in the memory section 20 according to the present embodiment, the row selection line driver (RLD) 23 is coupled to the row selection line RL through the coupling part 13 near the middle of the row selection line driver (RLD) 23 in the X-direction, and the column selection line driver (CLD) 24 is coupled to the column selection line CL through the coupling part 14 near the middle of the column selection line driver (CLD) 24 in the Y-direction. This enables, for example, in the row selection line driver (RLD) 231 in FIG. 7, 256 wiring lines to be coupled to the coupling part 131 from left side of the coupling part 131 and 256 wiring lines to be coupled to the coupling part 131 from right side of the coupling part 131 . This makes it possible, in the row selection line driver (RLD) 231 , to lower density of wiring lines near the coupling part 131 . The same holds true also for the row selection line driver (RLD) 232 and the column selection line drivers (CLD) 241 and 242 . As a result, it becomes easier, in the semiconductor device 1 , to lay out the row selection line driver (RLD) 23 and the column selection line driver (CLD) 24 .

FIGS. 15A, 15B, and 15C illustrate variations of each of the row selection line drivers (RLD) 231 and 232 , the column selection line drivers (CLD) 241 and 242 , and the coupling parts 131 , 132 , 141 and 142 .

In an example of FIG. 15A , similarly to the examples illustrated in FIGS. 7 and 9 , the shape of each of the regions of the row selection line drivers (RLD) 231 and 232 and the column selection line drivers (CLD) 241 and 242 is substantially square. In an example of FIG. 15B , the shape of each of the regions of the row selection line drivers (RLD) 231 and 232 and the column selection line drivers (CLD) 241 and 242 is rectangular.

In addition, in an example of FIG. 15C , the shape of the coupling part 13 (coupling parts 131 and 132 ) and the shape of the coupling part 14 (coupling parts 141 and 142 ) are each asymmetric. In this example, for example, a length in the Y-direction of an upper coupling part of the coupling part 131 coupled to the row selection line driver (RLD) 231 is made shorter than a length in the Y-direction of a lower coupling part of the coupling part 131 . The same holds true also for the coupling part 132 . In addition, for example, a length in the X-direction of a right coupling part of the coupling part 141 coupled to the column selection line driver (CLD) 241 is made longer than a length in the X-direction of a left coupling part of the coupling part 141 . The same holds true also for the coupling part 142 . Accordingly, the coupling part 131 is disposed slightly to the left of the middle in the X-direction in the row selection line driver (RLD) 231 , and the coupling part 132 is disposed slightly to the left of the middle in the X-direction in the row selection line driver (RLD) 232 . In addition, the coupling part 141 is disposed slightly above the middle in the Y-direction in the column selection line driver (CLD) 241 , and the coupling part 142 is disposed slightly above the middle in the Y-direction in the column selection line driver (CLD) 242 .

In any case of FIGS. 15A, 15B, and 15C , for example, in the Y-direction, the coupling part 131 is so disposed as not to overlap the coupling part 132 , and in the X-direction, the coupling part 141 is so disposed as not to overlap the coupling part 142 . In addition, for example, in the X-direction, the coupling part 131 is so disposed as not to overlap the coupling part 142 , and the coupling part 132 is so disposed as not to overlap the coupling part 141 . Likewise, for example, in the Y-direction, the coupling part 131 is so disposed as not to overlap the coupling part 141 , and the coupling part 132 is so disposed as not to overlap the coupling part 142 .

In addition, in the semiconductor device 1 , the row control line CRL (row control lines CRL 1 and CRL 2 ) and the column control line CCL (column control lines CCL 1 and CCL 2 ) are formed in respective layers above the layers (the wiring layers L 3 and L 4 in this example) in which the row selection line RL and the column selection line CL are formed, respectively. This enables the row selection line RL and the column selection line CL to be disposed at positions closer to the semiconductor substrate than a case where the row control line CRL and the column control line CCL are formed in respective layers under the layers in which the row selection line RL and the column selection line CL are formed, respectively. This makes it possible to suppress the voltage drop in the coupling part 13 (coupling parts 131 and 132 ) and the coupling part 14 (coupling parts 141 and 142 ). As a result, it is possible, in the semiconductor device 1 , to reduce the possibility that a write error or a read error may occur.

Further, in the semiconductor device 1 , as illustrated in FIG. 7 , the plurality of (512 in this example) row selection lines RL coupled to the row selection line driver (RLD) 231 are arranged side by side in one region, and the plurality of (512 in this example) row selection lines RL coupled to the row selection line driver (RLD) 232 are arranged side by side in one region. Likewise, in the semiconductor device 1 , as illustrated in FIG. 9 , the plurality of (512 in this example) column selection lines CL coupled to the column selection line driver (CLD) 241 are arranged side by side in one region, and the plurality of (512 in this example) column selection lines CL coupled to the column selection line driver (CLD) 242 are arranged side by side in one region. This makes it easier, in the semiconductor device 1 , to lay out the memory section 20 , and makes it possible to simplify the operation of the memory section 20 .

That is, referring, for example, to a memory section 20 S illustrated in FIGS. 16 and 17 , a plurality of (256 in this example) row selection lines RL coupled to a row selection line driver (RLD) 231 S and a plurality of (256 in this example) row selection lines RL coupled to a row selection line driver (RLD) 233 S are alternately arranged side by side in one region, and a plurality of (256 in this example) column selection lines CL coupled to a column selection line driver (CLD) 241 S and a plurality of (256 in this example) column selection lines CL coupled to a column selection line driver (CLD) 243 S are alternately arranged side by side in one region. In such a case, there is a possibility that it may be difficult to lay out the memory section 20 S. Specifically, for example, as illustrated in FIG. 18 in which the plurality of row selection lines RL illustrated in FIG. 16 and the plurality of column selection lines CL illustrated in FIG. 17 are depicted in a superimposed manner, the memory section 20 S has no region (slot region) where the row selection line RL and the column selection line CL are not formed. Thus, unlike the memory section 20 according to the present embodiment, it is not possible, in the memory section 20 S, to form the row control line CRL and the column control line CCL in the wiring layers L 5 and L 6 . In this case, the row control line CRL and the column control line CCL are formed in wiring layers under the wiring layers in which the row selection line RL and the column selection line CL are formed, respectively, thus leading to a possibility that it may be difficult to lay out the memory section 20 S. Further, for example, as illustrated in FIG. 16 , the plurality of row selection lines RL coupled to the row selection line driver (RLD) 231 S and the plurality of row selection lines RL coupled to the row selection line driver (RLD) 233 S are alternately arranged side by side. Accordingly, unlike the case of the present embodiment ( FIG. 7 ), the definition of the memory array AR becomes complicated, thus leading to a possibility that the operation of the memory section 20 S may be complicated.

Meanwhile, in the memory section 20 according to the present embodiment, for example, the plurality of (512 in this example) row selection lines RL coupled to the row selection line driver (RLD) 231 are arranged side by side in one region, and the plurality of (512 in this example) column selection lines CL coupled to the column selection line driver (CLD) 241 are arranged side by side in one region. This allows for generation, in the memory section 20 , of regions (slot regions SL 31 , SL 32 , SL 41 , and SL 42 ) in which the row selection line RL and the column selection line CL are not formed, as illustrated in FIG. 11 . Accordingly, in the memory section 20 , the coupling parts CN 31 and CN 32 are formed, respectively, in the slot regions SL 31 and SL 32 , thus enabling the row control lines CRL 1 and CRL 2 formed, for example, in the wiring layer L 5 to be coupled to the row selection line drivers 231 and 232 , respectively, through the coupling parts CN 31 and CN 32 . Likewise, in the memory section 20 , the coupling parts CN 41 and CN 42 are formed, respectively, in the slot regions SL 41 and SL 42 , thus enabling the column control lines CCL 1 and CCL 2 formed, for example, in the wiring layer L 6 to be coupled to the column selection line drivers (CLD) 241 and 242 , respectively, through the coupling parts CN 41 and CN 42 . As a result, it becomes easier, in the semiconductor device 1 , to lay out the memory section 20 . In addition, as illustrated in FIG. 7 , it is possible, in the semiconductor device 1 , to simplify the definition of the memory array AR, thus making it possible to simplify the operation of the memory section 20 .

[Effects]

As described above, in the present embodiment, the row selection line is coupled to the row selection line driver through the coupling part near the middle of the extending direction of the row selection line, and the column selection line is coupled to the column selection line driver through the coupling part near the middle of the extending direction of the column selection line. This makes it possible to reduce the possibility that a write error or a read error may occur.

In the present embodiment, the row selection line driver is coupled to a plurality of row selection lines through the coupling part near the middle of the row selection line driver in the X-direction, and the column selection line driver is coupled to a plurality of column selection lines through the coupling part near the middle of the column selection line driver in the Y-direction. This makes it easier to lay out the row selection line driver and the column selection line driver.

In the present embodiment, the row control line and the column control line are formed in respective layers above the layers in which the row selection line and the column selection line are formed. This makes it possible to reduce the possibility that a write error or a read error may occur.

In the present embodiment, a plurality of row selection lines coupled to the row selection line driver are arranged side by side in one region; a plurality of row selection lines coupled to the row selection line driver are arranged side by side in one region; a plurality of column selection lines coupled to the column selection line driver are arranged side by side in one region; and a plurality of column selection lines coupled to the column selection line driver are arranged side by side in one region. This makes it easier to lay out the memory section, and makes it possible to simplify the operation of the memory section.

Modification Example 1-1

In the foregoing embodiment, the row selection line RL is formed in the wiring layer L 3 , and the column selection line CL is formed in the wiring layer L 4 ; however, this is not limitative. In the following, description is given in detail of a semiconductor device 1 A according to the present modification example. The semiconductor device 1 A includes the logic circuit section 10 and a memory section 20 A.

FIG. 19 illustrates an example of a layer configuration in the semiconductor device 1 A. In the memory section 20 A of the semiconductor device 1 A, the metal wiring lines M 1 , M 2 , M 5 , and M 6 are formed in the wiring layers L 1 , L 2 , L 5 , and L 6 , respectively. In addition, in the memory section 20 A, the row selection line RL is formed in the wiring layer L 3 and the column selection line CL is formed in the wiring layer L 4 in a certain region, and the column selection line CL is formed in the wiring layer L 3 and the row selection line RL is formed in the wiring layer L 4 in another certain region.

FIG. 20 illustrates an example of the row selection lines RL. In FIG. 20 , the row selection lines RL formed in the wiring layer L 3 are each indicated by a solid line, and the row selection lines RL formed in the wiring layer L 4 are each indicated by a broken line.

The memory section 20 A includes a row selection line driver (RLD) 23 A (row selection line drivers (RLD) 231 A and 232 A) and a column selection line driver (CLD) 24 A (column selection line drivers (CLD) 241 A and 242 A).

One row selection line driver (RLD) 231 A is coupled to the plurality of (512 in this example) row selection lines RL through a coupling part 131 A. In FIG. 20 , the upper half of the row selection lines RL of the plurality of row selection lines RL coupled to the row selection line driver (RLD) 231 A is formed in the wiring layer L 4 , and the lower half of the row selection lines RL is formed in the wiring layer L 3 .

Likewise, one row selection line driver (RLD) 232 A is coupled to the plurality of (512 in this example) row selection lines RL through a coupling part 132 A. In FIG. 20 , the upper half of the row selection lines RL of the plurality of row selection lines RL coupled to the row selection line driver 232 A is formed in the wiring layer L 3 , and the lower half of the row selection lines RL is formed in the wiring layer L 4 .

FIGS. 21 to 23 each illustrate an example of the column selection lines CL. In FIG. 21 , the column selection lines CL formed in the wiring layer L 3 are each indicated by a solid line, and the column selection lines CL formed in the wiring layer L 4 are each indicated by a broken line.

One column selection line driver (CLD) 241 A is coupled to the plurality of (512 in this example) column selection lines CL through a coupling part 141 A. In FIG. 21 , a portion, of the plurality of column selection lines CL coupled to the column selection line driver (CLD) 241 A, extending to upper side of the coupling part 141 A is formed in the wiring layer L 3 , and a portion extending to lower side of the coupling part 141 A is formed in the wiring layer L 4 . As illustrated in FIG. 22 , the coupling part 141 A includes the contact CT, the metal wiring line M 1 , the via VA between the wiring layers L 1 and L 2 , the metal wiring line M 2 , the via VA between the wiring layers L 2 and L 3 , the column selection line CL, and the via VA between the wiring layers L 3 and L 4 .

One column selection line driver (CLD) 242 A is coupled to the plurality of (512 in this example) column selection lines CL through a coupling part 142 A. In FIG. 21 , a portion, of the plurality of column selection lines CL coupled to the column selection line driver (CLD) 242 A, extending to upper side of the coupling part 142 A is formed in the wiring layer L 4 , and a portion extending to lower side of the coupling part 142 A is formed in the wiring layer L 3 . As illustrated in FIG. 23 , the coupling part 142 A includes the contact CT, the metal wiring line M 1 , the via VA between the wiring layers L 1 and L 2 , the metal wiring line M 2 , the via VA between the wiring layers L 2 and L 3 , the column selection line CL, and the via VA between the wiring layers L 3 and L 4 .

2. Second Embodiment

Next, description is given of a semiconductor device 2 according to a second embodiment. In the present embodiment, two storage layers are provided. It is to be noted that components substantially the same as those of the semiconductor device 1 according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.

As illustrated in FIG. 1 , the semiconductor device 2 includes a logic circuit section 30 and a memory section 40 . Similar to the semiconductor device 1 ( FIG. 2 ) according to the foregoing embodiment, the memory section 40 includes a plurality of row selection line drivers (RLD) 43 (row selection line drivers (RLD) 431 and 432 ) and a plurality of column selection line drivers (CLD) 44 (column selection line drivers (CLD) 441 and 442 ). The plurality of row selection line drivers (RLD) 43 and the plurality of column selection line drivers (CLD) 44 are arranged in a checkerboard shape.

FIG. 24 illustrates a configuration example of the memory section 40 . The memory section 40 includes a plurality of row selection lines RL (row selection lines RL 0 and RL 1 ), the plurality of column selection lines CL, and a plurality of memory cells MC (memory cells MC 0 and MC 1 ).

The plurality of row selection lines RL 0 is so formed as to extend in the X-direction and to be aligned in the Y-direction in the X-Y plane parallel to the substrate surface S of the semiconductor substrate. The plurality of column selection lines CL is so formed as to extend in the Y-direction and to be aligned in the X-direction in the X-Y plane. The plurality of row selection lines RL 1 is so formed as to extend in the X-direction and to be aligned in the Y-direction in the X-Y plane. The plurality of column selection lines CL is formed in a layer above the layer in which the plurality of row selection lines RL 0 is formed, and the plurality of row selection lines RL 1 is formed in a layer above the layer in which the plurality of column selection lines CL is formed.

A plurality of memory cells MC (memory cells MC 0 ) is formed in a storage layer between the layer in which the plurality of row selection lines RL 0 is formed and the layer in which the plurality of column selection lines CL is formed. Likewise, a plurality of memory cells MC (memory cells MC 1 ) is formed in a layer between the layer in which the plurality of column selection lines CL is formed and the storage layer in which the plurality of row selection lines RL 1 is formed.

As illustrated in FIG. 4 , the memory cells MC 0 and MC 1 each include the storage element VR and the selection element SE. In the memory cell MC 0 , the terminal TU is coupled to any one of the plurality of column selection lines CL, and the terminal TL is coupled to any one of the plurality of row selection lines RL 0 . Likewise, in the memory cell MC 1 , the terminal TU is coupled to any one of the plurality of row selection lines RL 1 , and the terminal TL is coupled to any one of the plurality of column selection lines CL. As illustrated in FIG. 24 , this allows for formation of the storage element VR in the upper layer of the selection element SE in the memory cell MC, regardless of which storage layer is formed.

FIG. 25 illustrates an example of a layer configuration in the semiconductor device 2 . In this example, the semiconductor device 2 includes seven wiring layers L 1 to L 7 . In the logic circuit section 30 , metal wiring lines M 1 to M 7 are formed in wiring layers L 1 to L 7 , respectively.

In the memory section 40 , the metal wiring lines M 1 to M 3 and M 7 are formed in the wiring layers L 1 to L 3 and L 7 , respectively. The metal wiring lines M 1 to M 3 are used, for example, for local wiring lines in the row selection line driver (RLD) 43 and the column selection line driver (CLD) 44 , and for the column control line CCL (column control lines CCL 1 and CCL 2 ). The metal wiring line M 7 is used, for example, for the row control line CRL (row control lines CRL 1 and CRL 2 ). In addition, in the memory section 40 , the row selection line RL 0 is formed in the wiring layer L 4 , the column selection line CL is formed in the wiring layer L 5 , and the row selection line RL 1 is formed in the wiring layer L 6 .

(Row Selection Lines RL 0 and RL 1 )

FIG. 26 illustrates an example of the row selection lines RL 0 . FIG. 27 illustrates an example of the row selection lines RL 1 . FIG. 28 illustrates an example of the row selection lines RL 0 and RL 1 . The length of each of the row selection lines RL 0 and RL 1 is about twice that of the row selection line RL according to the foregoing first embodiment.

The plurality of row selection line drivers (RLD) 431 includes a row selection line driver (RLD) 431 A that drives the plurality of row selection lines RL 0 and a row selection line driver (RLD) 431 B that drives the plurality of row selection lines RL 1 . The row selection line drivers (RLD) 431 A and 431 B are alternately arranged with the column selection line driver (CLD) 441 interposed therebetween in the X-direction. Likewise, the plurality of row selection line drivers (RLD) 432 includes a row selection line driver (RLD) 432 A that drives the plurality of row selection lines RL 0 and a row selection line driver (RLD) 432 B that drives the plurality of row selection lines RL 1 . The row selection line drivers (RLD) 432 A and 432 B are alternately arranged with the column selection line driver (CLD) 442 interposed therebetween in the X-direction.

As illustrated in FIG. 26 , each of the plurality of row selection lines RL 0 is coupled to a coupling part 33 A (coupling parts 331 A and 332 A) near the middle of the extending direction (X-direction) of the row selection line RL 0 . In addition, each row selection line driver (RLD) 431 A is coupled to the coupling part 331 A near the middle of the row selection line driver (RLD) 431 A in the X-direction, and each row selection line driver (RLD) 432 A is coupled to the coupling part 332 A near the middle of the row selection line driver (RLD) 432 A in the X-direction. As a result, the row selection line driver (RLD) 431 A is coupled to the plurality of row selection lines RL 0 through the coupling part 331 A, and the row selection line driver (RLD) 432 A is coupled to the plurality of row selection lines RL 0 through the coupling part 332 A. As illustrated in FIG. 28 , the coupling part 331 A includes the contact CT, the metal wiring line M 1 , the via VA between the wiring layers L 1 and L 2 , the metal wiring line M 2 , the via VA between the wiring layers L 2 and L 3 , the metal wiring line M 3 , and the via VA between the wiring layers L 3 and L 4 . The same holds true also for the coupling part 332 A.

One row selection line driver (RLD) 431 A is coupled to the plurality of (512 in this example) row selection lines RL 0 , for example. In FIG. 26 , the right ends of the row selection lines RL 0 coupled to the row selection line driver (RLD) 431 A are located near the middle in the X-direction of the row selection line driver (RLD) 431 B on right side of the row selection line driver (RLD) 431 A. In addition, the left ends of the row selection lines RL 0 coupled to the row selection line driver (RLD) 431 A are located near the middle in the X-direction of the row selection line driver (RLD) 431 B on left side of the row selection line driver (RLD) 431 A.

Likewise, one row selection line driver (RLD) 432 A is coupled to the plurality of (512 in this example) row selection lines RL 0 , for example. In FIG. 26 , the right ends of the row selection lines RL 0 coupled to the row selection line driver (RLD) 432 A are located near the middle in the X-direction of the row selection line driver (RLD) 432 B on right side of the row selection line driver (RLD) 432 A. In addition, the left ends of the row selection lines RL 0 coupled to the row selection line driver (RLD) 432 A are located near the middle in the X-direction of the row selection line driver (RLD) 432 B on left side of the row selection line driver (RLD) 432 A.

As illustrated in FIG. 27 , each of the plurality of row selection lines RL 1 is coupled to a coupling part 33 B (coupling parts 331 B and 332 B) near the middle of the extending direction (X-direction) of the row selection line RL 1 . In addition, each row selection line driver (RLD) 431 B is coupled to the coupling part 331 B near the middle of the row selection line driver (RLD) 431 B in the X-direction, and each row selection line driver (RLD) 432 B is coupled to the coupling part 332 B near the middle of the row selection line driver (RLD) 432 B in the X-direction. As a result, the row selection line driver (RLD) 431 B is coupled to the plurality of row selection lines RL 1 through the coupling part 331 B, and the row selection line driver (RLD) 432 B is coupled to the plurality of row selection lines RL 1 through the coupling part 332 B. As illustrated in FIG. 28 , the coupling part 331 B includes the contact CT, the metal wiring line M 1 , the via VA between the wiring layers L 1 and L 2 , the metal wiring line M 2 , the via VA between the wiring layers L 2 and L 3 , the metal wiring line M 3 , the via VA between the wiring layers L 3 and L 4 , the metal wiring line M 4 , the via VA between the wiring layers L 4 and L 5 , the metal wiring line M 5 , and the via VA between the wiring layers L 5 and L 6 . The same holds true also for the coupling part 332 B.

One row selection line driver (RLD) 431 B is coupled to the plurality of (512 in this example) row selection lines RL 1 , for example. In FIG. 27 , the right ends of the row selection lines RL 1 coupled to the row selection line driver (RLD) 431 B are located near the middle in the X-direction of the row selection line driver (RLD) 431 A on right side of the row selection line driver (RLD) 431 B. In addition, the left ends of the row selection lines RL 1 coupled to the row selection line driver (RLD) 431 B are located near the middle in the X-direction of the row selection line driver (RLD) 431 A on left side of the row selection line driver (RLD) 431 B.

Likewise, one row selection line driver (RLD) 432 B is coupled to the plurality of (512 in this example) row selection lines RL 1 , for example. In FIG. 27 , the right ends of the row selection lines RL 1 coupled to the row selection line driver (RLD) 432 B are located near the middle in the X-direction of the row selection line driver (RLD) 432 A on right side of the row selection line driver (RLD) 432 B. In addition, the left ends of the row selection lines RL 1 coupled to the row selection line driver (RLD) 432 B are located near the middle in the X-direction of the row selection line driver (RLD) 432 A on left side of the row selection line driver (RLD) 432 B.

(Column Selection Line CL)

FIGS. 29 and 30 each illustrate an example of the column selection lines CL. The configuration of the column selection line CL is the same as that of the column selection line CL ( FIG. 9 ) according to the foregoing first embodiment. The column selection line driver (CLD) 441 is coupled to the plurality of column selection lines CL through a coupling part 341 , and the column selection line driver (CLD) 442 is coupled to the plurality of column selection lines CL through a coupling part 342 . As illustrated in FIG. 30 , the coupling part 341 includes the contact CT, the metal wiring line M 1 , the via VA between the wiring layers L 1 and L 2 , the metal wiring line M 2 , the via VA between the wiring layers L 2 and L 3 , the metal wiring line M 3 , the via VA between the wiring layers L 3 and L 4 , the metal wiring line M 4 , and the via VA between the wiring layers L 4 and L 5 . The same holds true also for the coupling part 342 .

FIG. 31 illustrates an example of the plurality of row selection lines RL 0 and RL 1 and the plurality of column selection lines CL. FIG. 31 depicts the plurality of row selection lines RL 0 and RL 1 illustrated in FIGS. 26 and 27 and the plurality of column selection lines CL illustrated in FIG. 29 in a superimposed manner.

Each of the plurality of row selection lines RL 0 intersects 2048 (=512×4) column selection lines CL in this example, and each of the plurality of column selection lines CL intersects 1024 (=512×2) row selection lines RL 0 in this example. Likewise, each of the plurality of row selection lines RL 1 intersects 2048 (=512×4) column selection lines CL in this example, and each of the plurality of column selection lines CL intersects 1024 (=512×2) row selection lines RL 1 in this example.

In the memory section 40 , a memory array AR 0 including 2M (=2048×1024) memory cells MC 0 and a memory array AR 1 including 2M (=2048×1024) memory cells MC 1 are defined. As illustrated in FIG. 26 , the memory array AR 0 includes 512 row selection lines RL 0 coupled to the row selection line driver (RLD) 431 A and 512 row selection lines RL 0 coupled to the row selection line driver (RLD) 432 A. As illustrated in FIG. 27 , the memory array AR 1 includes 512 row selection lines RL 1 coupled to the row selection line driver (RLD) 431 B and 512 row selection lines RL 1 coupled to the row selection line driver (RLD) 432 B.

As illustrated in FIG. 31 , a region corresponding to the row selection line driver (RLD) 431 (row selection line drivers (RLD) 431 A and 431 B) includes a region (slot region SL 31 ) where the row selection lines RL 0 and RL 1 and the column selection line CL are not formed. The slot region SL 31 is located near the middle in the Y-direction of the region corresponding to the row selection line driver (RLD) 431 . Likewise, a region corresponding to the row selection line driver (RLD) 432 (row selection line drivers (RLD) 432 A and 432 B) includes a region (slot region SL 32 ) where the row selection lines RL 0 and RL 1 and the column selection line CL are not formed. The slot region SL 32 is located near the middle in the Y-direction of the region corresponding to the row selection line driver (RLD) 432 . The slot regions SL 31 and SL 32 are each a rectangular region that is long in the X-direction and short in the Y-direction. In the memory section 40 , as described below, the coupling part CN 31 that couples the row selection line driver (RLD) 431 and the row control line CRL 1 to each other is formed in the slot region SL 31 , and the coupling part CN 32 that couples the row selection line driver (RLD) 432 and the row control line CRL 2 to each other is formed in the slot region SL 32 .

(Row Control Line CRL and Column Control Line CCL)

FIG. 32 illustrates a configuration example of the row control line CRL (row control lines CRL 1 and CRL 2 ) and the column control line CCL (column control lines CCL 1 and CCL 2 ).

In the row selection line driver (RLD) 431 (row selection line drivers (RLD) 431 A and 431 B), the coupling part CN 31 is formed in the slot region SL 31 , and in the row selection line driver (RLD) 432 (row selection line drivers (RLD) 432 A and 432 B), the coupling part CN 32 is formed in the slot region SL 32 .

The row control lines CRL 1 and CRL 2 are each formed using, for example, the metal wiring line M 7 of the wiring layer L 7 . The row control line CRL 1 is coupled to the row selection line driver (RLD) 431 through the coupling part CN 31 , and the row control line CRL 2 is coupled to the row selection line driver (RLD) 432 through the coupling part CN 32 . As a result, the row controller 21 supplies the selection control signal SELRL 1 to the plurality of row selection line drivers (RLD) 431 coupled to the row control line CRL 1 through the row control line CRL 1 , and supplies the selection control signal SELRL 2 to the plurality of row selection line drivers (RLD) 432 coupled to the row control line CRL 2 through the row control line CRL 2 .

The column control lines CCL 1 and CCL 2 are each formed using, for example, the metal wiring line M 2 of the wiring layer L 2 . The column control line CCL 1 is coupled to the column selection line driver (CLD) 441 through an unillustrated coupling part, and the column control line CCL 2 is coupled to the column selection line driver (CLD) 442 through an unillustrated coupling part. As a result, the column controller 22 supplies the selection control signal SELCL 1 to the plurality of column selection line drivers (CLD) 441 coupled to the column control line CCL 1 through the column control line CCL 1 , and supplies the selection control signal SELCL 2 to the plurality of column selection line drivers (CLD) 442 coupled to the column control line CCL 2 through the column control line CCL 2 .

The semiconductor device 2 is provided with the plurality of row selection lines RL 0 and RL 1 as well as the row selection line drivers (RLD) 431 A and 432 A that each drive the plurality of row selection lines RL 0 and the row selection line drivers (RLD) 431 B and 432 B that each drive the plurality of row selection lines RL 1 , allowing two storage layers to be provided, thus making it possible to increase a storage capacity.

As described above, in the present embodiment, the plurality of row selection lines RL 0 and RL 1 is provided, and the row selection line driver that drives the plurality of row selection lines RL 0 and the row selection line driver that drives the plurality of row selection lines RL 1 are provided, thus making it possible to increase a storage capacity. Other effects are similar to those in the case of the foregoing first embodiment.

3. Third Embodiment

Next, description is given of a semiconductor device 3 according to a third embodiment. In the present embodiment, the number of storage layers is further increased. It is to be noted that components substantially the same as those of the semiconductor device 2 according to the foregoing second embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.

As illustrated in FIG. 1 , the semiconductor device 3 includes a logic circuit section 50 and a memory section 60 . Similarly to the semiconductor device 3 ( FIG. 2 ) according to the foregoing embodiment, the memory section 60 includes a plurality row selection line drivers (RLD) 63 (row selection line drivers (RLD) 631 and 632 ) and a plurality of column selection line drivers (CLD) 64 (column selection line drivers (CLD) 641 and 642 ). The plurality of row selection line drivers (RLD) 63 and the plurality of column selection line drivers (CLD) 64 are arranged in a checkerboard shape.

FIG. 33 illustrates a configuration example of the memory section 60 . The memory section 60 includes a plurality of row selection lines RL (row selection lines RL 0 , RL 1 , and RL 2 ), a plurality of column selection lines CL (column selection lines CL 1 and CL 2 ), and a plurality of memory cells MC (memory cells MC 0 , MC 1 , MC 2 , and MC 3 ).

The plurality of row selection lines RL 0 is so formed as to extend in the X-direction and to be aligned in the Y-direction in the X-Y plane parallel to the substrate surface S of the semiconductor substrate. The plurality of column selection lines CL 0 is so formed as to extend in the Y-direction and to be aligned in the X-direction in the X-Y plane. The plurality of row selection lines RL 1 is so formed as to extend in the X-direction and to be aligned in the Y-direction in the X-Y plane parallel to the substrate surface S of the semiconductor substrate. The plurality of column selection lines CL 1 is so formed as to extend in the Y-direction and to be aligned in the X-direction in the X-Y plane. The plurality of row selection lines RL 2 is so formed as to extend in the X-direction and to be aligned in the Y-direction in the X-Y plane parallel to the substrate surface S of the semiconductor substrate. The plurality of column selection lines CL 0 is formed in a layer above the layer in which the plurality of row selection lines RL 0 is formed; the plurality of row selection lines RL 1 is formed in a layer above the layer in which the plurality of column selection lines CL 0 is formed; the plurality of column selection lines CL 1 is formed in a layer above the layer in which the plurality of row selection lines RL 1 is formed; and the plurality of row selection lines RL 2 is formed in a layer above the layer in which the plurality of column selection lines CL 1 is formed. As described later, each of the plurality of row selection lines RL 2 is coupled to a corresponding row selection line RL 0 of the plurality of row selection lines RL 0 .

The plurality of memory cells MC (memory cells MC 0 ) is formed in a storage layer between the layer in which the plurality of row selection lines RL 0 is formed and the layer in which the plurality of column selection lines CL 0 is formed. Likewise, the plurality of memory cells MC (memory cells MC 1 ) is formed in a layer between the layer in which the plurality of column selection lines CL 0 is formed and the storage layer in which the plurality of row selection lines RL 1 is formed; the plurality of memory cells MC (memory cells MC 2 ) is formed in a storage layer between the layer in which the plurality of row selection lines RL 1 is formed and the layer in which the plurality of column selection lines CL 1 is formed; and the plurality of memory cells MC (MC 3 ) is formed in a layer between the layer in which the plurality of column selection lines CL 1 is formed and the storage layer in which the plurality of row selection lines RL 2 is formed.

As illustrated in FIG. 4 , the memory cells MC 0 to MC 3 each include the storage element VR and the selection element SE. In the memory cell MC 0 , the terminal TU is coupled to any one of the plurality of column selection lines CL 0 , and the terminal TL is coupled to any one of the plurality of row selection lines RL 0 . Likewise, in the memory cell MC 1 , the terminal TU is coupled to any one of the plurality of row selection lines RL 1 , and the terminal TL is coupled to any one of the plurality of column selection lines CL 0 . In the memory cell MC 2 , the terminal TU is coupled to any one of the plurality of column selection lines CL 1 , and the terminal TL is coupled to any one of the plurality of row selection lines RL 1 . In the memory cell MC 3 , the terminal TU is coupled to any one of the plurality of row selection lines RL 2 , and the terminal TL is coupled to any one of the plurality of column selection lines CL 1 . As illustrated in FIG. 33 , this allows for formation of the storage element VR in the upper layer of the selection element SE in the memory cell MC, regardless of which storage layer is formed.

FIG. 34 illustrates an example of a layer configuration in the semiconductor device 3 . In this example, the semiconductor device 3 includes nine wiring layers L 1 to L 9 . In the logic circuit section 50 , metal wiring lines M 1 to M 9 are formed in wiring layers L 1 to L 9 , respectively.

In the memory section 60 , the metal wiring lines M 1 to M 4 are formed in the wiring layers L 1 to L 4 , respectively. The metal wiring lines M 1 to M 4 are used, for example, for local wiring lines in the row selection line driver (RLD) 63 and the column selection line driver (CLD) 64 , and for the row control line CRL (row control lines CRL 1 and CRL 2 ) and the column control line CCL (column control lines CCL 1 and CCL 2 ). Further, in the memory section 60 , the row selection line RL 0 is formed in the wiring layer L 5 , the column selection line CL 0 is formed in the wiring layer L 6 , the row selection line RL 1 is formed in the wiring layer L 7 , the column selection line CL 1 is formed in the wiring layer L 8 , and the row selection line RL 2 is formed in the wiring layer L 9 .

(Row Selection Lines RL 0 to RL 2 )

FIG. 35 illustrates an example of the row selection lines RL 0 and RL 2 . FIG. 36 illustrates an example of the row selection line RL 1 . FIG. 37 illustrates an example of the row selection lines RL 0 to RL 2 .

The plurality of row selection line drivers (RLD) 631 includes a row selection line driver (RLD) 631 A that drives the plurality of row selection lines RL 0 and RL 2 and a row selection line driver (RLD) 631 B that drives the plurality of row selection lines RL 1 . The row selection line drivers (RLD) 631 A and 631 B are alternately arranged with the column selection line driver (CLD) 641 interposed therebetween in the X-direction. Likewise, the plurality of row selection line drivers (RLD) 632 includes a row selection line driver (RLD) 632 A that drives the plurality of row selection lines RL 0 and RL 2 and a row selection line driver (RLD) 632 B that drives the plurality of row selection lines RL 1 . The row selection line drivers (RLD) 632 A and 632 B are alternately arranged with the column selection line driver (CLD) 642 interposed therebetween in the X-direction.

The configuration of the row selection line RL 0 is the same as that of the row selection line RL 1 ( FIG. 26 ) according to the foregoing second embodiment, and the configuration of the row selection line RL 1 is the same as that of the row selection line RL 2 ( FIG. 27 ) according to the foregoing second embodiment.

As illustrated in FIG. 35 , the row selection line driver (RLD) 631 A is coupled to the plurality of row selection lines RL 0 and RL 2 through a coupling part 531 A, and the row selection line driver (RLD) 632 A is coupled to the plurality of row selection lines RL 0 and RL 2 through a coupling part 532 A. As illustrated in FIG. 37 , the coupling part 531 A includes the contact CT, the metal wiring line M 1 , the via VA between the wiring layers L 1 and L 2 , the metal wiring line M 2 , the via VA between the wiring layers L 2 and L 3 , the metal wiring line M 3 , the via VA between the wiring layers L 3 and L 4 , the metal wiring line M 4 , the via VA between the wiring layers L 4 and L 5 , the row selection line RL 0 , the via VA between the wiring layers L 5 and L 6 , the metal wiring line M 6 , the via VA between the wiring layers L 6 and L 7 , the metal wiring line M 7 , the via VA between the wiring layers L 7 and L 8 , the metal wiring line M 8 , and the via VA between the wiring layers L 8 and L 9 . That is, the row selection line RL 2 is coupled to the row selection line RL 0 using the coupling part 531 A. The same holds true also for the coupling part 532 A.

In addition, as illustrated in FIG. 36 , the row selection line driver (RLD) 631 B is coupled to the plurality of row selection lines RL 1 through a coupling part 531 B, and the row selection line driver (RLD) 632 B is coupled to the plurality of row selection lines RL 1 through a coupling part 532 B. As illustrated in FIG. 37 , the coupling part 531 B includes the contact CT, the metal wiring line M 1 , the via VA between the wiring layers L 1 and L 2 , the metal wiring line M 2 , the via VA between the wiring layers L 2 and L 3 , the metal wiring line M 3 , the via VA between the wiring layers L 3 and L 4 , the metal wiring line M 4 , the via VA between the wiring layers L 4 and L 5 , the metal wiring line M 5 , the via VA between the wiring layers L 5 and L 6 , the metal wiring line M 6 , and the via VA between the wiring layers L 6 and L 7 . The same holds true also for the coupling part 532 B.

(Column Selection Lines CL 0 and CL 1 )

FIG. 38 illustrates an example of the column selection lines CL 0 . FIG. 39 illustrates an example of the column selection lines CL 1 . FIG. 40 illustrates an example of the column selection lines CL 0 and CL 1 . The length of each of the column selection lines CL 0 and CL 1 is about twice that of the column selection line CL according to the foregoing second embodiment.

The plurality of column selection line drivers (CLD) 641 includes a column selection line driver (CLD) 641 A that drives the plurality of column selection lines CL 0 and a column selection line driver (CLD) 641 B that drives the plurality of column selection lines CL 1 . The column selection line drivers (CLD) 641 A and 641 B are alternately arranged with the row selection line driver (RLD) 631 interposed therebetween in the Y-direction. Likewise, the plurality of column selection line drivers (CLD) 642 includes a column selection line driver (CLD) 642 A that drives the plurality of column selection lines CL 0 and a column selection line driver (CLD) 642 B that drives the plurality of column selection lines CL 1 . The column selection line drivers (CLD) 642 A and 642 B are alternately arranged with the row selection line driver (RLD) 632 interposed therebetween in the Y-direction.

As illustrated in FIG. 38 , each of the plurality of column selection lines CL 0 is coupled to a coupling part 54 A (coupling parts 541 A and 542 A) near the middle of the extending direction (Y-direction) of the column selection line CL 0 . In addition, each column selection line driver (CLD) 641 A is coupled to the coupling part 541 A near the middle of the column selection line driver (CLD) 641 A in the Y-direction, and each column selection line driver (CLD) 642 A is coupled to the coupling part 542 A near the middle of the column selection line driver (CLD) 642 A in the Y-direction. As a result, the column selection line driver (CLD) 641 A is coupled to the plurality of column selection lines CL 0 through the coupling part 541 A, and the column selection line driver (CLD) 642 A is coupled to the plurality of column selection lines CL 0 through the coupling part 542 A. As illustrated in FIG. 40 , the coupling part 541 A includes the contact CT, the metal wiring line M 1 , the via VA between the wiring layers L 1 and L 2 , the metal wiring line M 2 , the via VA between the wiring layers L 2 and L 3 , the metal wiring line M 3 , the via VA between the wiring layers L 3 and L 4 , the metal wiring line M 4 , the via VA between the wiring layers L 4 and L 5 , the metal wiring line M 5 , and the via VA between the wiring layers L 5 and L 6 . The same holds true also for the coupling part 542 A.

One column selection line driver (CLD) 641 A is coupled to the plurality of (512 in this example) column selection lines CL 0 , for example. In FIG. 38 , the upper ends of the column selection lines CL 0 coupled to the column selection line driver (CLD) 641 A are located near the middle in the Y-direction of the column selection line driver (CLD) 641 B on upper side of the column selection line driver (CLD) 641 A. In addition, the lower ends of the column selection lines CL 0 coupled to the column selection line driver (CLD) 641 A are located near the middle in the Y-direction of the column selection line driver (CLD) 641 B on lower side of the column selection line driver (CLD) 641 A.

Likewise, one column selection line driver (CLD) 642 A is coupled to the plurality of (512 in this example) column selection lines CL 0 , for example. In FIG. 38 , the upper ends of the column selection lines CL 0 coupled to the column selection line driver (CLD) 642 A are located near the middle in the Y-direction of the column selection line driver (CLD) 642 B on upper side of the column selection line driver (CLD) 642 A. In addition, the lower ends of the column selection lines CL 0 coupled to the column selection line driver (CLD) 642 A are located near the middle in the Y-direction of the column selection line driver (CLD) 642 B on lower side of the column selection line driver (CLD) 642 A.

As illustrated in FIG. 39 , each of the plurality of column selection lines CL 1 is coupled to a coupling part 54 B (coupling parts 541 B and 542 B) near the middle of the extending direction (Y-direction) of the column selection line CL 1 . In addition, each column selection line driver (CLD) 641 B is coupled to the coupling part 541 B near the middle of the column selection line driver (CLD) 641 B in the Y-direction, and each column selection line driver (CLD) 642 B is coupled to the coupling part 542 B near the middle of the column selection line driver (CLD) 642 B in the Y-direction. As a result, the column selection line driver (CLD) 641 B is coupled to the plurality of column selection lines CL 1 through the coupling part 541 B, and the column selection line driver (CLD) 642 B is coupled to the plurality of column selection lines CL 1 through the coupling part 542 B. As illustrated in FIG. 40 , the coupling part 541 B includes the contact CT, the metal wiring line M 1 , the via VA between the wiring layers L 1 and L 2 , the metal wiring line M 2 , the via VA between the wiring layers L 2 and L 3 , the metal wiring line M 3 , the via VA between the wiring layers L 3 and L 4 , the metal wiring line M 4 , the via VA between the wiring layers L 4 and L 5 , the metal wiring line M 5 , the via VA between the wiring layers L 5 and L 6 , the metal wiring line M 6 , the via VA between the wiring layers L 6 and L 7 , the metal wiring line M 7 , and the via VA between the wiring layers L 7 and L 8 . The same holds true also for the coupling part 542 B.

One column selection line driver (CLD) 641 B is coupled to the plurality of (512 in this example) column selection lines CL 1 , for example. In FIG. 39 , the upper ends of the column selection lines CL 1 coupled to the column selection line driver (CLD) 641 B are located near the middle in the Y-direction of the column selection line driver (CLD) 641 A on upper side of the column selection line driver (CLD) 641 B. In addition, the lower ends of the column selection lines CL 1 coupled to the column selection line driver (CLD) 641 B are located near the middle in the Y-direction of the column selection line driver (CLD) 641 A on lower side of the column selection line driver (CLD) 641 B.

Likewise, one column selection line driver (CLD) 642 B is coupled to the plurality of (512 in this example) column selection lines CL 1 , for example. In FIG. 39 , the upper ends of the column selection lines CL 1 coupled to the column selection line driver (CLD) 642 B are located near the middle in the Y-direction of the column selection line driver (CLD) 642 A on upper side of the column selection line driver (CLD) 642 B. In addition, the lower ends of the column selection lines CL 1 coupled to the column selection line driver (CLD) 642 B are located near the middle in the Y-direction of the column selection line driver (CLD) 642 A on lower side of the column selection line driver (CLD) 642 B.

FIG. 41 illustrates an example of the plurality of row selection lines RL 0 to RL 2 and the plurality of column selection lines CL 0 and CL 1 . FIG. 41 depicts the plurality of row selection lines RL 0 to RL 2 illustrated in FIGS. 35 and 36 and the plurality of column selection lines CL 0 and CL 1 illustrated in FIGS. 38 and 39 in a superimposed manner.

Each of the plurality of row selection lines RL 0 intersects 2048 (=512×4) column selection lines CL 0 in this example, and each of the plurality of column selection lines CL 0 intersects 2048 (=512×4) row selection lines RL 0 in this example. Likewise, each of the plurality of row selection lines RL 1 intersects 2048 (=512×4) column selection lines CL 0 in this example, and each of the plurality of column selection lines CL 0 intersects 2048 (=512×4) row selection lines RL 1 in this example. Each of the plurality of row selection lines RL 1 intersects 2048 (=512×4) column selection lines CL 1 in this example, and each of the plurality of column selection lines CL 1 intersects 2048 (=512×4) row selection lines RL 1 in this example. Each of the plurality of row selection lines RL 2 intersects 2048 (=512×4) column selection lines CL 1 in this example, and each of the plurality of column selection lines CL 1 intersects 2048 (=512×4) row selection lines RL 2 in this example.

In the memory section 40 , a memory array AR 0 ( FIG. 35 ) including 4M (=2048×2048) memory cells MC 0 , a memory array AR 1 ( FIG. 36 ) including 4M (=2048×2048) memory cells MC 1 , a memory array AR 2 ( FIG. 36 ) including 4M (=2048×2048) memory cells MC 2 , and a memory array AR 3 ( FIG. 35 ) including 4M (=2048×2048) memory cells MC 3 are defined.

As illustrated in FIG. 41 , in the memory section 60 , unlike the memory section 40 ( FIG. 31 ), for example, in the region corresponding to the row selection line driver (RLD) 63 (row selection line drivers (RLD) 631 and 632 ), there is no region where the row selection lines RL 0 to RL 2 as well as the column selection lines CL 0 and CL 1 are not formed; in the region corresponding to the column selection line driver (CLD) 64 (column selection line drivers (CLD) 641 and 642 ), there is no region where the row selection lines RL 0 to RL 2 as well as the column selection lines CL 0 and CL 1 are not formed.

(Row Control Line CRL and Column Control Line CCL)

FIG. 42 illustrates a configuration example of the row control line CRL (row control lines CRL 1 and CRL 2 ) and the column control line CCL (column control lines CCL 1 and CCL 2 ).

The row control lines CRL 1 and CRL 2 are each formed using, for example, the metal wiring line M 4 of the wiring layer L 4 . The row control line CRL 1 is coupled to the row selection line driver (RLD) 631 through an unillustrated coupling part, and the row control line CRL 2 is coupled to the row selection line driver (RLD) 632 through an unillustrated coupling part. As a result, the row controller 21 supplies the selection control signal SELRL 1 to the plurality of row selection line drivers (RLD) 631 coupled to the row control line CRL 1 through the row control line CRL 1 , and supplies the selection control signal SELRL 2 to the plurality of row selection line drivers (RLD) 632 coupled to the row control line CRL 2 through the row control line CRL 2 .

The column control lines CCL 1 and CCL 2 are each formed using, for example, the metal wiring line M 3 of the wiring layer L 3 . The column control line CCL 1 is coupled to the column selection line driver (CLD) 641 through an unillustrated coupling part, and the column control line CCL 2 is coupled to the column selection line driver (CLD) 642 through an unillustrated coupling part. As a result, the column controller 22 supplies the selection control signal SELCL 1 to the plurality of column selection line drivers (CLD) 641 coupled to the column control line CCL 1 through the column control line CCL 1 , and supplies the selection control signal SELCL 2 to the plurality of column selection line drivers (CLD) 642 coupled to the column control line CCL 2 through the column control line CCL 2 .

The semiconductor device 3 is provided with the plurality of row selection lines RL 0 to RL 2 and the plurality of column selection lines CL 0 and CL 1 as well as with the row selection line drivers (RLD) 631 A and 632 A that each drive the plurality of row selection lines RL 0 and RL 2 ; the row selection line drivers (RLD) 631 B and 632 B that each drive the plurality of row selection lines RL 1 ; the column selection line drivers (CLD) 641 A and 642 A that each drive the plurality of column selection lines CL 0 ; and the column selection line drivers (CLD) 641 B and 642 B that each drive the plurality of column selection lines CL 1 , allowing four storage layers to be provided, thus making it possible to increase a storage capacity.

As described above, in the present embodiment, there are provided the plurality of row selection lines RL 0 to RL 2 and the plurality of column selection lines CL 0 and CL 1 , and there are provided the row selection line driver that drives the plurality of row selection lines RL 0 and RL 2 ; the row selection line driver that drives the plurality of row selection lines RL 1 ; the column selection line driver that drives the plurality of column selection lines CL 0 ; and the column selection line driver that drives the plurality of column selection lines CL 1 , thus making it possible to increase a storage capacity. Other effects are similar to those in the case of the foregoing second embodiment.

Modification Example 3-1

In the foregoing embodiment, four storage layers are provided; however, this is not limitative. Three storage layers may be provided, or five or more storage layers may be provided. In the following, description is given in detail of a semiconductor device 3 A provided with three storage layers. The semiconductor device 3 A includes a logic circuit section 50 A and a memory section 60 A.

FIG. 43 illustrates a configuration example of the memory section 60 A. The memory section 60 A includes the plurality of row selection lines RL (row selection lines RL 0 and RL 1 ), the plurality of column selection lines CL (column selection lines CL 0 and CL 1 ), and the plurality of memory cells MC (memory cells MC 0 , MC 1 , and MC 2 ).

The plurality of row selection lines RL 0 is so formed as to extend in the X-direction and to be aligned in the Y-direction in the X-Y plane parallel to the substrate surface S of the semiconductor substrate. The plurality of column selection lines CL 0 is so formed as to extend in the Y-direction and to be aligned in the X-direction in the X-Y plane. The plurality of row selection lines RL 1 is so formed as to extend in the X-direction and to be aligned in the Y-direction in the X-Y plane. The plurality of column selection lines CL 1 is so formed as to extend in the Y-direction and to be aligned in the X-direction in the X-Y plane. The plurality of column selection lines CL 0 is formed in a layer above the layer in which the plurality of row selection lines RL 0 is formed; the plurality of row selection lines RL 1 is formed in a layer above the layer in which the plurality of column selection lines CL 0 is formed; and the plurality of column selection lines CL 1 is formed in a layer above the layer in which the plurality of row selection lines RL 1 is formed.

The plurality of memory cells MC (memory cells MC 0 ) is formed in a storage layer between the layer in which the plurality of row selection lines RL 0 is formed and the layer in which the plurality of column selection lines CL 0 is formed. Likewise, the plurality of memory cells MC (memory cells MC 1 ) is formed in a layer between the layer in which the plurality of column selection lines CL 0 is formed and the storage layer in which the plurality of row selection lines RL 1 is formed, and the plurality of memory cells MC (memory cells MC 2 ) is formed in a layer between the layer in which the plurality of row selection lines RL 1 is formed and the storage layer in which the plurality of column selection lines CL 1 is formed.

As illustrated in FIG. 4 , the memory cells MC 0 to MC 2 each include the storage element VR and the selection element SE. In the memory cell MC 0 , the terminal TU is coupled to any one of the plurality of column selection lines CL 0 , and the terminal TL is coupled to any one of the plurality of row selection lines RL 0 . Likewise, in the memory cell MC 1 , the terminal TU is coupled to any one of the plurality of row selection lines RL 1 , and the terminal TL is coupled to any one of the plurality of column selection lines CL 0 . In the memory cell MC 2 , the terminal TU is coupled to any one of the plurality of column selection lines CL 1 , and the terminal TL is coupled to any one of the plurality of row selection lines RL 1 . As illustrated in FIG. 43 , this allows for formation of the storage element VR in the upper layer of the selection element SE in the memory cell MC, regardless of which storage layer is formed.

FIG. 44 illustrates an example of a layer configuration in the semiconductor device 3 A. In this example, the semiconductor device 3 A includes eight wiring layers L 1 to L 8 . In the logic circuit section 50 A, the metal wiring lines M 1 to M 8 are formed in the wiring layers L 1 to L 8 , respectively.

In the memory section 60 A, the metal wiring lines M 1 to M 4 are formed in the wiring layers L 1 to L 4 , respectively. The metal wiring lines M 1 to M 4 are used, for example, for local wiring lines in the row selection line driver (RLD) 63 and the column selection line driver (CLD) 64 , and for the row control line CRL (row control lines CRL 1 and CRL 2 ) and the column control line CCL (column control lines CCL 1 and CCL 2 ). In addition, in the memory section 60 A, the row selection line RL 0 is formed in the wiring layer L 5 , the column selection line CL 0 is formed in the wiring layer L 6 , the row selection line RL 1 is formed in the wiring layer L 7 , and the column selection line CL 1 is formed in the wiring layer L 8 .

The configurations of the row selection lines RL 0 and RL 1 in the memory section 60 A are similar to those of the row selection lines RL 0 and RL 1 ( FIGS. 35 and 36 ) of the memory section 60 according to the foregoing embodiment. In addition, the configurations of the column selection lines CL 0 and CL 1 in the memory section 60 A are similar to those of the column selection lines CL 0 and CL 1 ( FIGS. 38 and 39 ) of the memory section 60 according to the foregoing embodiment.

Although the present technology has been described with reference to several embodiments and modification examples, the present technology is not limited to these embodiments, etc., and may be modified in a variety of ways.

For example, the layer configurations, the number of the row selection lines RL, the number of the column selection lines CL, and the like in each of the foregoing embodiments, etc. are merely exemplary, and may be modified as appropriate.

Further, for example, in each of the foregoing embodiments, etc., the logic circuit and the nonvolatile memory are mounted together (embedded); however, this is not limitative. The logic circuit and the nonvolatile memory may not be mounted together. In this case, it is possible to manufacture the memory section using a manufacturing process optimized for the non-volatile memory.

It is to be noted that the effects described herein are merely illustrative and non-limiting, and other effects may be included.

It is to be noted that the present technology may have the following configurations.

(1)

A semiconductor device including:

a plurality of first selection lines provided in a first region, the plurality of first selection lines extending in a first direction and being aligned in a second direction that intersects the first direction;

a plurality of second selection lines provided in a second region having a portion that overlaps a portion of the first region, the plurality of second selection lines extending in the second direction and being aligned in the first direction;

a plurality of third selection lines provided in a third region having a portion that overlaps a portion of the second region, the plurality of third selection lines extending in the first direction and being aligned in the second direction;

a plurality of fourth selection lines provided in a fourth region having one portion that overlaps a portion of the first region and having another portion that overlaps a portion of the third region, the plurality of fourth selection lines extending in the second direction and being aligned in the first direction;

a first coupling part coupled to the plurality of first selection lines at a portion, of the first region, other than ends in the first direction;

a second coupling part coupled to the plurality of second selection lines at a portion, of the second region, other than ends in the second direction;

a third coupling part coupled to the plurality of third selection lines at a portion, of the third region, other than ends in the first direction;

a fourth coupling part coupled to the plurality of fourth selection lines at a portion, of the fourth region, other than ends in the second direction;

a driver that drives the plurality of first selection lines, the plurality of second selection lines, the plurality of third selection lines, and the plurality of fourth selection lines, respectively, through the first coupling part, the second coupling part, the third coupling part, and the fourth coupling part;

a first memory cell interposed between one of the plurality of first selection lines and one of the plurality of fourth selection lines;

a second memory cell interposed between one of the plurality of second selection lines and one of the plurality of first selection lines;

a third memory cell interposed between one of the plurality of third selection lines and one of the plurality of second selection lines; and

a fourth memory cell interposed between one of the plurality of fourth selection lines and one of the plurality of third selection lines.

(2)

The semiconductor device according to (1), in which

the driver includes

a first circuit provided in a first circuit region, the first circuit being coupled to the first coupling part in a region of the first circuit region and driving the plurality of first selection lines,

a second circuit provided in a second circuit region adjacent to the first circuit region in the first direction, the second circuit being coupled to the second coupling part in a region of the second circuit region and driving the plurality of second selection lines,

a third circuit provided in a third circuit region adjacent to the second circuit region in the second direction, the third circuit being coupled to the third coupling part in a region of the third circuit region and driving the plurality of third selection lines, and

a fourth circuit provided in a fourth circuit region that is adjacent to the first circuit region in the second direction and is adjacent to the third circuit region in the second direction, the fourth circuit being coupled to the fourth coupling part in a region of the fourth circuit region and driving the plurality of fourth selection lines.

(3)

The semiconductor device according to (2), in which

the first circuit is coupled to the first coupling part at a portion, of the first circuit region, other than ends in the first direction,

the second circuit is coupled to the second coupling part at a portion, of the second circuit region, other than ends in the second direction,

the third circuit is coupled to the third coupling part at a portion, of the third circuit region, other than ends in the first direction, and

the fourth circuit is coupled to the fourth coupling part at a portion, of the fourth circuit region, other than ends in the second direction.

(4)

The semiconductor device according to (2) or (3), in which

the plurality of first selection lines and the plurality of third selection lines are formed in a first layer,

the plurality of second selection lines and the plurality of fourth selection lines are formed in a second layer, and

a first end, which is one of ends of the first region in the first direction, is located within the region of the second circuit region.

(5)

The semiconductor device according to (4), in which the first end is located in a region other than ends within the region of the second circuit region in the first direction.

(6)

The semiconductor device according to (4) or (5), further including:

a plurality of fifth selection lines provided in a fifth region, the plurality of fifth selection lines extending in the first direction and being aligned in the second direction, the fifth region being adjacent to and apart from the first region in the first direction and having a portion that overlaps a portion of the second region; and

a fifth coupling part coupled to the plurality of fifth selection lines at a portion, of the fifth region, other than ends in the first direction, in which

the driver further includes a fifth circuit provided in a fifth circuit region adjacent to the second circuit region in the first direction, the fifth circuit being coupled to the fifth coupling part in a region of the fifth circuit region and driving the plurality of fifth selection lines, and

a second end, which is one of ends of the fifth region in the first direction, is located within the region of the second circuit region.

(7)

The semiconductor device according to (6), further including:

a controller that generates a control signal;

a control signal line formed in an upper layer of the first layer and the second layer, the control signal line extending in the first direction and transmitting the control signal; and

a control signal coupling part coupled to the control signal line, in which

the second circuit is coupled to the control signal coupling part at a portion, in the second circuit region, sandwiched between the first end of the first region and the second end of the fifth region.

(8)

The semiconductor device according to any one of (4) to (7), in which one of ends of the fourth region in the second direction is located within the region of the first circuit region.

(9)

The semiconductor device according to (2) or (3), in which

the first coupling part includes a first partial coupling part and a second partial coupling part arranged in the second direction, and

a layer in which selection lines, of the plurality of first selection lines, coupled to the first partial coupling part are formed is different from a layer in which selection lines, of the plurality of first selection lines, coupled to the second partial coupling part are formed.

(10)

The semiconductor device according to (2) or (3), in which a layer in which line portions, of the plurality of second selection lines, on one side as viewed from the second coupling part in the second direction are formed is different from a layer in which line portions, of the plurality of second selection lines, on the other side as viewed from the second coupling part in the second direction are formed.

(11)

The semiconductor device according to (2), further including:

a plurality of sixth selection lines provided in a sixth region having a portion that overlaps a portion of the first region and a portion of the second region, the plurality of sixth selection lines extending in the first direction and being aligned in the second direction; and

a sixth coupling part coupled to the plurality of sixth selection lines at a portion, of the sixth region, other than ends in the first direction, in which

the plurality of first selection lines and the plurality of third selection lines are formed in a first layer,

the plurality of second selection lines and the plurality of fourth selection lines are formed in a second layer,

the plurality of sixth selection lines is formed in a third layer,

the first layer, the second layer, and the third layer are disposed in this order,

the driver further includes a sixth circuit provided in a sixth circuit region adjacent to the second circuit region in the first direction, the sixth circuit being coupled to the sixth coupling part in a region of the sixth circuit region and driving the plurality of sixth selection lines,

a third end, which is one of ends of the first region in the first direction, is located within the region of the sixth circuit region, and

a fourth end, which is one of ends of the sixth region in the first direction, is located within the region of the first circuit region.

(12)

The semiconductor device according to (11), in which

the third end of the first region is located in a region, within the region of the sixth circuit region, other than the ends in the first direction, and

the fourth end of the sixth region is located in a region, within the region of the first circuit region, other than the ends in the first direction.

(13)

The semiconductor device according to (11) or (12), in which one of the ends of the fourth region in the second direction is located within the region of the first circuit region.

(14)

The semiconductor device according to (11), further including:

a plurality of seventh selection lines provided in a seventh region having a portion that overlaps a portion of the second region and a portion of the third region, the plurality of seventh selection lines extending in the second direction and being aligned in the first direction; and

a seventh coupling part coupled to the plurality of seventh selection lines at a portion, of the seventh region, other than ends in the second direction, in which

the plurality of seventh selection lines is formed in a fourth layer,

the first layer, the second layer, the third layer, and the fourth layer are disposed in this order,

the driver further includes a seventh circuit provided in a seventh circuit region adjacent to the third circuit region in the second direction, the seventh circuit being coupled to the seventh coupling part in a region of the seventh circuit region and driving the plurality of seventh selection lines,

a fifth end, which is one of the ends of the second region in the second direction, is located within the region of the seventh circuit region, and

a sixth end, which is one of the ends of the seventh region in the second direction, is located within the region of the second circuit region.

(15)

The semiconductor device according to (14), further including a plurality of eighth selection lines provided in the first region, the plurality of eighth selection lines extending in the first direction and being aligned in the second direction, in which

the plurality of eighth selection lines is coupled to the first coupling part at the portion, of the first region, other than the ends in the first direction, and

the first circuit also drives the eighth selection lines in addition to the plurality of first selection lines.

This application claims the benefit of Japanese Priority Patent Application JP2017-104176 filed with the Japan Patent Office on May 26, 2017, the entire contents of which are incorporated herein by reference.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations, and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.