Array substrate and method of manufacturing same

The present disclosure relates to display technologies, and more particularly, to an array substrate and a method of manufacturing the same.

Liquid crystal display (LCD) is the mainstream of displays, but its light utilization rate has not been easy to improve for a long time, and its light transmittance is limited.

Low temperature poly-Silicon (LTPS) technologies are used to fabricate a channel of a thin film transistor. Because of its high carrier mobility, a higher current can be obtained, which can reduce the size of the thin film transistor and increase the transmittance area of each sub-pixel, but increase of light transmittance is still limited.

Therefore, there is a need to solve the above problems.

In view of the above, the present disclosure provides a array substrate and a method of manufacturing the same to resolve above-mentioned technical problem.

In order to achieve above-mentioned object of the present disclosure, one embodiment of the disclosure provides an array substrate including a substrate, a plurality of thin film transistors disposed on the substrate, and a planarization layer covering the plurality of thin film transistors and filled a region defined by the plurality of thin film transistors and the substrate.

In one embodiment of the disclosure, the plurality of thin film transistors include a molybdenum shading layer disposed on the substrate, a buffer layer covering on the molybdenum shading layer, an active layer disposed on the buffer layer, a gate insulating layer covering on the active layer, a patterned gate layer disposed on the gate insulating layer, an interlayer dielectric covering on the patterned gate layer, and a source/drain layer disposed on the interlayer dielectric and connected to the active layer by a first through-hole layer.

In one embodiment of the disclosure, the array substrate further includes a transparent common conductive layer disposed on the planarization layer, a passivation layer disposed on the transparent common conductive layer, and transparent pixel electrodes disposed on the passivation layer.

In one embodiment of the disclosure, the array substrate further includes a patterned metallic layer and an insulating layer disposed between the planarization layer and the transparent common conductive layer.

In one embodiment of the disclosure, the active layer includes a poly-silicon layer, light doping layers disposed at opposite sides of the poly-silicon layer, and heavy doping layers contacted the light doping layers.

Furthermore, another embodiment of the disclosure provides a method of manufacturing an array substrate including steps of:

providing an array substrate with a source/drain layer;

providing a patterned photoresist layer covering the array substrate by half tone photo mask developing process;

etching the source/drain layer;

etching an interlayer dielectric, a gate insulating layer, and a buffer layer;

ashing the patterned photoresist layer;

etching the source/drain layer second time to form a patterned source/drain layer; and

providing a planarization layer covering on the substrate.

In one embodiment of the disclosure, the method of manufacturing the array substrate further includes:

providing a transparent common conductive layer disposed on the planarization layer;

providing a passivation layer disposed on the transparent common conductive layer; and

providing a transparent pixel electrode disposed on the passivation layer.

In one embodiment of the disclosure, the step of providing an array substrate with a source/drain layer further includes steps of:

providing a substrate;

providing a patterned molybdenum shading layer disposed on the substrate;

providing the buffer layer disposed on the patterned molybdenum shading layer;

providing a patterned active layer disposed on the buffer layer;

providing the gate insulating layer covering the patterned active layer;

providing a patterned gate layer disposed on the gate insulating layer;

providing the interlayer dielectric covering on the patterned gate layer;

and

providing the source/drain layer disposed on the interlayer dielectric.

In one embodiment of the disclosure, the patterned active layer includes poly-silicon.

In one embodiment of the disclosure, the patterned active layer includes a poly-silicon layer, light doping layers disposed at opposite sides of the poly-silicon layer, and heavy doping layers disposed beside the light doping layers respectively.

In comparison with prior art, the array substrate and the method of manufacturing the same of the disclosure reduce light absorption, reflection, refraction, or scattering between layers and increase light transmittance by filling planarization layer in the region defined by the thin film transistors and the substrate after excavating the buffer layer, the gate insulating layer, and the interlayer dielectric between the thin film transistors and the substrate.

FIG. 1 is a schematic view of a structure of an array substrate according to an embodiment of the present disclosure.

FIG. 2 is a schematic view of a structure of an array substrate according to an embodiment of the present disclosure.

FIG. 3 is a schematic flowchart of a method of manufacturing the array substrate according to an embodiment of the present disclosure.

FIG. 4 is a schematic flowchart of a step of providing an array substrate with source/drain layer according to an embodiment of the present disclosure.

FIG. 5 is a schematic process of a step of providing an array substrate with source/drain layer according to an embodiment of the present disclosure.

FIG. 6 is a schematic process of a step of providing a patterned photoresist layer covering the array substrate by half tone photo mask developing process according to an embodiment of the present disclosure.

FIG. 7 is a schematic process of a step of etching the source/drain layer according to an embodiment of the present disclosure.

FIG. 8 is a schematic process of a step of etching an interlayer dielectric, a gate insulating layer, and a buffer layer according to an embodiment of the present disclosure.

FIG. 9 is a schematic process of a method of manufacturing an array substrate according to an embodiment of the present disclosure.

FIG. 10 is a schematic process of a method of manufacturing an array substrate according to an embodiment of the present disclosure.

The following description of the embodiments is provided by reference to the following drawings and illustrates the specific embodiments of the present disclosure. Directional terms mentioned in the present disclosure, such as “up,” “down,” “top,” “bottom,” “forward,” “backward,” “left,” “right,” “inside,” “outside,” “side,” “peripheral,” “central,” “horizontal,” “peripheral,” “vertical,” “longitudinal,” “axial,” “radial,” “uppermost” or “lowermost,” etc., are merely indicated the direction of the drawings. Therefore, the directional terms are used for illustrating and understanding of the application rather than limiting thereof.

Referring to FIG. 1 , one embodiment of the disclosure provides an array substrate 1000 including a substrate 100 , a plurality of thin film transistors (TFT) 200 disposed on the substrate 100 , and a planarization layer (PLN) 300 covering the plurality of thin film transistors 200 and filled a region defined by the plurality of thin film transistors 200 and the substrate 100 .

Referring to FIG. 1 , in one embodiment of the disclosure, the plurality of thin film transistors 200 include a molybdenum (Mo) shading layer 10 disposed on the substrate, a buffer layer (BL) 20 covering on the molybdenum shading layer 10 , an active layer 30 disposed on the buffer layer 20 , a gate insulating layer (GI) 40 covering on the active layer 30 , a patterned gate layer 50 disposed on the gate insulating layer 40 , an interlayer dielectric (ILD) 60 covering on the patterned gate layer 50 , and a source/drain layer 70 disposed on the interlayer dielectric 60 and connected to the active layer 30 by a first through-hole layer Via_ 1 .

Referring to FIG. 1 , in one embodiment of the disclosure, the array substrate 1000 further includes a transparent common conductive layer 400 disposed on the planarization layer 300 , a passivation layer (PV) 500 disposed on the transparent common conductive layer 400 , and transparent pixel electrodes 600 disposed on the passivation layer 500 .

In detail, material of the transparent common conductive layer 400 may be indium tin oxide (ITO). Material of the transparent pixel electrodes 600 may be ITO.

In detail, the transparent common conductive layer 400 is electrically connected to the source/drain layer 70 by a second through-hole layer Via_ 2 . The transparent pixel electrodes 600 is electrically connected to the source/drain layer 70 by a third through-hole layer Via_ 3 and the second through-hole layer Via_ 2 .

Referring to FIG. 2 , in one embodiment of the disclosure, the array substrate 1000 ′ further includes a patterned metallic layer 700 and an insulating layer (IL) 800 disposed between the planarization layer 300 and the transparent common conductive layer 400 .

In detail, the patterned metallic layer 700 is disposed above the molybdenum (Mo) shading layer 10 to avoid reducing light transmittance or scattering light.

In detail, the transparent common conductive layer 400 can serve as a common electrode of an in-cell touch panel. There is some distance between the patterned metallic layer 700 and the patterned gate layer 50 to avoid crosstalk of signal.

Referring to FIG. 1 , in one embodiment of the disclosure, the active layer 30 includes a poly-silicon layer 31 , light doping layers 32 disposed at opposite sides of the poly-silicon layer 31 , and heavy doping layers 33 contacted the light doping layers 32 .

In detail, the heavy doping layers 33 are used to reduce junction resistance between metallic material of first through-hole layer Via_ 1 and semiconductor material of the active layer 30 . The light doping layers 32 are used to reduce a width of a depletion region between the heavy doping layers 33 and the poly-silicon layer 31 .

Furthermore, referring to FIG. 3 , another embodiment of the disclosure provides a method of manufacturing an array substrate including steps of:

At block S 100 : providing an array substrate with a source/drain layer;

Referring to FIGS. 3 and 6 , at block S 200 : providing a patterned photoresist (PR) layer covering the array substrate by half tone photo mask developing process;

In detail, half tone photo mask developing process can provide patterned photoresist layer with different depths at the same time.

Referring to FIGS. 3 and 7 , at block S 300 : etching the source/drain layer 70 ;

Referring to FIGS. 3 and 8 , at block S 400 : etching an interlayer dielectric 60 , a gate insulating layer 40 , and a buffer layer 20 ;

Referring to FIGS. 3 and 9 , at block S 500 : ashing the patterned photoresist layer;

At block S 600 : etching the source/drain layer 70 second time to form a patterned source/drain layer; and

At block S 700 : providing a planarization layer 700 covering on the substrate.

Referring to FIGS. 3 and 10 , in one embodiment of the disclosure, the method of manufacturing the array substrate further includes:

At block S 800 : providing a transparent common conductive layer 400 disposed on the planarization layer;

At block S 900 : providing a passivation layer 500 disposed on the transparent common conductive layer 400 ; and

At block S 1000 : providing a transparent pixel electrode 600 disposed on the passivation layer 500 .

Referring to FIGS. 4 and 5 , in one embodiment of the disclosure, the step S 100 of providing an array substrate with a source/drain layer further includes steps of:

At block S 110 : providing a substrate 100 ;

At block S 120 : providing a patterned molybdenum shading layer 10 disposed on the substrate 100 ;

At block S 130 providing the buffer layer 20 disposed on the patterned molybdenum shading layer 10 ;

At block S 140 : providing a patterned active layer 30 disposed on the buffer layer 20 ;

At block S 150 : providing the gate insulating layer 40 covering the patterned active layer 30 ;

At block S 160 : providing a patterned gate layer 50 disposed on the gate insulating layer 40 ;

At block S 170 : providing the interlayer dielectric 60 covering on the patterned gate layer 50 ; and

At block S 180 : providing the source/drain layer 70 disposed on the interlayer dielectric 60 .

In one embodiment of the disclosure, the patterned active layer includes poly-silicon.

Referring to FIG. 1 , in one embodiment of the disclosure, the patterned active layer includes a poly-silicon layer, light doping layers disposed at opposite sides of the poly-silicon layer, and heavy doping layers disposed beside the light doping layers respectively.

In detail, the heavy doping layers 33 are used to reduce junction resistance between metallic material of first through-hole layer Via_ 1 and semiconductor material of the active layer 30 . The light doping layers 32 are used to reduce a width of a depletion region between the heavy doping layers 33 and the poly-silicon layer 31 .

In comparison with prior art, the array substrate and the method of manufacturing the same of the disclosure reduce light absorption, reflection, refraction, or scattering between layers by filling planarization layer in the region defined by the thin film transistors and the substrate after excavating the buffer layer, the gate insulating layer, and the interlayer dielectric between the thin film transistors and the substrate.

The present disclosure has been described by the above embodiments, but the embodiments are merely examples for implementing the present disclosure. It must be noted that the embodiments do not limit the scope of the invention. In contrast, modifications and equivalent arrangements are intended to be included within the scope of the invention.