Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation

This application is a continuation of U.S. patent application Ser. No. 16/162,668 filed Oct. 17, 2018, which claims priority to United States Provisional Application for Patent No. 62/575,692 filed Oct. 23, 2017, the disclosures of which are incorporated by reference.

The present invention relates to voltage multiplying (for example, doubling) circuits configured to generate positive and negative voltages.

Reference is made to FIG. 1 showing a circuit diagram for a voltage doubler circuit 100 . The circuit 100 includes an n-channel MOS transistor MN 1 having a source (conduction) terminal coupled to node A and a drain (conduction) terminal coupled to node NA 1 and an n-channel MOS transistor MN 2 having a source terminal coupled to node A and a drain terminal coupled to node NA 2 . The transistors MN 1 and MN 2 are cross-coupled with the gate terminal of transistor MN 1 coupled to the drain terminal of transistor MN 2 at node NA 2 and the gate terminal of transistor MN 2 coupled to the drain terminal of transistor MN 1 at node NA 1 .

The circuit 100 further includes an n-channel MOS transistor MN 3 having a source terminal coupled to node NA 1 and a drain terminal coupled to node NB 1 and an n-channel MOS transistor MN 4 having a source terminal coupled to node NA 2 and a drain terminal coupled to node NB 2 . The transistors MN 3 and MN 4 are cross-coupled with the gate terminal of transistor MN 3 coupled to the source terminal of transistor MN 4 at node NA 2 and the gate terminal of transistor MN 4 coupled to the source terminal of transistor MN 3 at node NA 1 .

The circuit 100 still further includes an n-channel MOS transistor MN 5 having a drain terminal coupled to node B and a source terminal coupled to node NA 1 and an n-channel MOS transistor MN 6 having a drain terminal coupled to node B and a source terminal coupled to node NA 2 . The gate terminal of transistor MN 5 is coupled to node NB 1 and the gate terminal of transistor MN 6 is coupled to node NB 2 .

A capacitor C 1 has one terminal coupled to node NA 1 and another terminal coupled to receive a clock signal CK. A capacitor C 2 has one terminal coupled to node NA 2 and another terminal coupled to receive a clock signal CKN (which is a logical inversion of the clock signal CK). A bootstrap capacitor Cbs 1 has one terminal coupled to node NB 1 and another terminal coupled to receive a clock signal CKH. A bootstrap capacitor Cbs 2 has one terminal coupled to node NB 2 and another terminal coupled to receive a clock signal CKHN (which is a logical inversion of the clock signal CKH).

The clock signals CKH and CKHN are generated from the clock signals CK and CKN using a clock voltage boosting circuit 110 shown in FIG. 2 . The circuit 110 includes an n-channel MOS transistor 112 having a source terminal coupled to a positive supply voltage node VDD and a drain terminal coupled to node 114 and an n-channel MOS transistor 116 having a source terminal coupled to the VDD node and a drain terminal coupled to node 118 . The transistors 112 and 116 are cross-coupled with the gate terminal of transistor 112 coupled to the drain terminal of transistor 116 at node 118 and the gate terminal of transistor 116 coupled to the drain terminal of transistor 112 at node 114 .

A capacitor C 1 ′ has one terminal coupled to node 114 and another terminal coupled to receive the clock signal CK. A capacitor C 2 ′ has one terminal coupled to node 118 and another terminal coupled to receive the clock signal CKN.

A CMOS inverter 120 has an input coupled to the VDD node and an output generating the clock signal CKH. A source terminal of the p-channel MOS transistor in inverter 120 is coupled to the node 114 and a source terminal of the n-channel MOS transistor in inverter 120 is coupled to receive the clock signal CK.

A CMOS inverter 122 has an input coupled to the VDD node and an output generating the clock signal CKHN. A source terminal of the p-channel MOS transistor in inverter 122 is coupled to the node 118 and a source terminal of the n-channel MOS transistor in inverter 122 is coupled to receive the clock signal CKN.

The clock voltage boosting circuit 110 functions to level shift the clock signals CK and CKN to generate the clock signals CKH and CKHN. FIG. 3A shows the waveforms for the clock signals CK and CKN. FIG. 3B shows the waveforms for the clock signals CKH and CKHN. It will be noted that the clock voltage boosting circuit 110 functions to boost the high voltage level of the clock signals CKH and CKHN to 2*VDD, with the high voltage level of the clock signals CK and CKN being VDD. The clock signals CKH and CKHN have a same phase as the clock signals CK and CKN, respectively.

The voltage doubler circuit 100 of FIG. 1 is operable to generate either a positive voltage or a negative voltage. When the voltage doubler circuit 100 is to be used as a positive voltage doubler (i.e., operating in a high positive voltage mode), an input voltage such as the supply voltage VDD is connected to node A and an output voltage such as a high positive voltage of 2*VDD is generated at node B. Conversely, when the voltage doubler circuit 100 is to be used as a negative voltage doubler (i.e., operating in a high negative voltage mode), an input voltage such as the ground supply voltage GND is connected to node B and an output voltage such as a high negative voltage of −VDD is generated at node A.

The voltage doubler circuit 100 advantageously operates from just two clocks (CK/CKH and CKN/CKHN).

The voltage doubler circuit 100 operates as follows in the high positive voltage mode:

To begin, assume that no clock is present. In this situation, the nodes NA 1 and NA 2 will be charged to the VDD−Vt voltage level, where Vt is the threshold voltage of the n-channel MOS transistors MN 1 and MN 2 . Now, assume the clock signal is applied. With the clock signal CK at the VDD voltage level and the clock signal CKN at the 0 (ground GND) voltage level, then the clock signal CKH is at the 2*VDD voltage level and the clock signal CKHN is at the 0 voltage level. In this configuration, the node NA 1 will shift to the 2VDD−Vt voltage level and the node NA 2 will shift to the VDD voltage level. Due to the cross coupling between transistors MN 3 and MN 4 , the node NB 1 will be charged to the 3*VDD voltage level and the node NB 2 will be charged to the VDD voltage level. As the node NB 1 is at the 3*VDD voltage level and the node NA 1 is at the 2*VDD voltage level, the n-channel MOS transistor MN 5 has sufficient Vgs (gate to source voltage) to pass the 2*VDD voltage from node NA 1 to node B. In this way, a high positive voltage (higher than input supply voltage VDD) is generated and passed for output. So, during high positive voltage mode operation, the voltage VDD is applied at node A and the 2*VDD voltage is generated at node B. During the opposite phase of the clocks, the nodes NA 1 and NA 2 switch between the VDD voltage level and the 2*VDD voltage level. Similarly, the nodes NB 1 and NB 2 switch between the VDD voltage level and the 3*VDD voltage level.

The voltage doubler circuit 100 operates as follows in the high negative voltage mode:

With the ground reference voltage GND applied to node B, when the clock signal CKH transitions to the 2*VDD voltage level, the clock signal CK is simultaneously at the VDD voltage level, and the n-channel MOS transistor MN 5 turns on and node NA 1 is charged to the 0 (GND) voltage level. During the next clock cycle, the clock signal CKH switches from the 2*VDD voltage level to the 0 voltage level, with the clock signal CK changing state from the VDD voltage level to 0 voltage level, and the node NA 1 accordingly transitions from the 0 voltage level to the −VDD voltage level. Also, the node NB 1 discharges to the −VDD voltage level via the transistor MN 3 and the switch off of the transistor MN 5 . In this way, the node NA 1 also goes to the −VDD voltage level. Due to effect of the clock signals CKN and CKHN, the node NA 2 is charged to the 0 (GND) voltage level via transistor MN 6 . As the NA 2 is at the 0 voltage level, and the NA 1 is at the −VDD voltage level, this configuration causes the transistor MN 1 to turn on and pass the −VDD voltage level voltage to the node A. During this negative high voltage mode of operation, the nodes NA 1 and NA 2 switch between the 0 voltage level and the −VDD voltage level, and vice versa. Similarly, the nodes NB 1 and NB 2 switch between the VDD voltage level and the −VDD voltage level, and vice versa.

It will be noted that the foregoing voltage levels in the positive and negative operating modes are mentioned with the assumption of an ideal operating situation when there is no current load at the output and there is no charge loss.

Implementation of the circuit 100 as an integrated circuit utilizes three different isolated P-type wells (PWELLS) for the bulk (body) of the transistors. Those PWELLS include: a first PWELL associated with node A for the bulk of transistors MN 1 and MN 2 ; a second PWELL associated with node NA 1 for the bulk of transistors MN 3 and MN 5 ; and a third PWELL associated with node NA 2 for bulk of transistors MN 4 and MN 6 . Those skilled in the art recognize that the provision of three different isolated PWELL structures will occupy a significant amount of integrated circuit area. Additionally, because of the local connection of the isolated bulk to the source terminals of the transistors, the bulk becomes capacitive due to associated capacitance on the source node (this being specifically a concern at nodes NA 1 and NA 2 due to the large capacitance provided by capacitors C 1 and C 2 ).

There is a need in the art to address the foregoing concerns.

In an embodiment, a circuit comprises: a voltage multiplier circuit including: a first node configured to receive a first voltage when said voltage multiplier circuit is configured for operation in a positive voltage boosting mode and configured to output a negative voltage when said circuit is configured for operation in a negative voltage boosting mode; a second node configured to output a positive voltage in excess of said first voltage when said voltage multiplier circuit is configured for operation in the positive voltage boosting mode and configured to receive a second voltage in excess of said negative voltage when said circuit is configured for operation in a negative voltage boosting mode; and a plurality of transistors of a same conductivity type and sharing a common bulk that is not tied to a source of any transistor in said plurality of transistors; and a bias generator circuit coupled to receive a first voltage from the first node and second voltage from the second node, said bias generator circuit configured to apply a lower one of the first and second voltages to the common bulk.

In an embodiment, a circuit comprises: a first node; a second node; a first transistor and second transistor connected in a cross-coupled configuration, wherein the first transistor is coupled between the first node and a first intermediate node and the second transistor is coupled between the first node and a second intermediate node; a third transistor and fourth transistor connected in a cross-coupled configuration, wherein the third transistor is coupled between the first intermediate node and a third intermediate node and the fourth transistor is coupled between the second intermediate node and a fourth intermediate node; a fifth transistor coupled between the first intermediate node and the second node and having a control terminal coupled to the third intermediate node; a sixth transistor coupled between the second intermediate node and the second node and having a control terminal coupled to the fourth intermediate node; wherein the first through sixth transistors share a common bulk that is not tied to a source of any transistor in said first through sixth transistors; and a bias generator circuit coupled to receive a first voltage from the first node and second voltage from the second node, said bias generator circuit configured to apply a lower one of the first and second voltages to the common bulk; wherein the first and second intermediate nodes are capacitively coupled to receive opposite phases of a first clock signal, respectively; and wherein the third and fourth intermediate nodes are capacitively coupled to receive opposite phases of a second clock signal, respectively.

In an embodiment, a circuit comprises: a first node; a second node; a first transistor and second transistor, wherein the first transistor is coupled between the first node and the first intermediate node and wherein the second transistor is coupled between the first node and the second intermediate node; a third transistor and fourth transistor, wherein the third transistor is coupled between the first intermediate node and the third intermediate node and wherein the fourth transistor is coupled between the second intermediate node and the fourth intermediate node, with gates of the first and fourth transistors coupled to the third intermediate node and with gates of the second and third transistors coupled to the fourth intermediate node; a fifth transistor coupled between the first intermediate node and the second node and having a control terminal coupled to the fourth intermediate node; a sixth transistor coupled between the second intermediate node and the second node and having a control terminal coupled to the third intermediate node; wherein the first through sixth transistors share a common bulk that is not tied to a source of any transistor in said first through sixth transistors; and a bias generator circuit coupled to receive a first voltage from the first node and second voltage from the second node, said bias generator circuit configured to apply a lower one of the first and second voltages to the common bulk; wherein the first and second intermediate nodes are capacitively coupled to receive opposite phases of a first clock signal, respectively; and wherein the third and fourth intermediate nodes are capacitively coupled to receive opposite phases of a second clock signal, respectively.

In an embodiment, a circuit comprises: a first node; a second node; a first transistor and second transistor, wherein the first transistor is coupled between the first node and the first intermediate node and wherein the second transistor is coupled between the first node and the second intermediate node; a third transistor and fourth transistor, wherein the third transistor is coupled between the first intermediate node and the third intermediate node and wherein the fourth transistor is coupled between the second intermediate node and the fourth intermediate node, with gates of the first and fourth transistors coupled to the third intermediate node and with gates of the second and third transistors coupled to the fourth intermediate node; a fifth transistor coupled between the first intermediate node and the second node and having a control terminal coupled to the fourth intermediate node; and a sixth transistor coupled between the second intermediate node and the second node and having a control terminal coupled to the third intermediate node; wherein the first and second intermediate nodes are capacitively coupled to receive opposite phases of a first clock signal, respectively; and wherein the third and fourth intermediate nodes are capacitively coupled to receive opposite phases of a second clock signal, respectively.

In an embodiment, a circuit, comprises: a voltage multiplier circuit including: first and second intermediate nodes that are capacitively coupled to receive opposite phases of a first clock signal, respectively; and a first transistor and a second transistor connected in a cross-coupled configuration, wherein a first conduction terminal of the first transistor and a gate terminal of the second transistor are connected to the first intermediate node and wherein a first conduction terminal of the second transistor and a gate terminal of the first transistor are connected to the second intermediate node; wherein said first and second transistors have a same conductivity type and share a common bulk that is not tied to a source of either of said first and second transistors; and a bias generator circuit configured to apply a bias voltage to the common bulk of the first and second transistors.

In an embodiment, a circuit comprises: a first node; a second node; a first transistor and second transistor connected in a cross-coupled configuration, wherein the first transistor is coupled between the first node and a first intermediate node and the second transistor is coupled between the first node and a second intermediate node; wherein the first and second intermediate nodes are capacitively coupled to receive opposite phases of a first clock signal, respectively; a third transistor coupled between the first intermediate node and the second node; a fourth transistor coupled between the second intermediate node and the second node; wherein the first through fourth transistors share a common bulk that is not tied to a source of any transistor in said first through fourth transistors; and a bias generator circuit coupled to receive a first voltage from the first node and a second voltage from the second node, said bias generator circuit configured to apply a lower one of the first and second voltages to the common bulk.

For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:

FIG. 1 is a circuit diagram for a voltage doubler;

FIG. 2 is a circuit diagram for a clock voltage boosting circuit;

FIGS. 3A and 3B show clock signal waveforms;

FIG. 4 is a circuit diagram for a voltage doubler;

FIG. 5 is a cross-section diagram of a triple well technology implementation of the circuit of FIG. 4 ;

FIG. 6 is a circuit diagram for a voltage doubler; and

FIG. 7 is a circuit diagram for a voltage doubler.

Reference is now made to FIG. 4 showing a circuit diagram for a voltage doubler circuit 200 . Like references refer to like or similar components in FIG. 1 . The voltage doubler circuit 200 differs from the voltage doubler circuit 100 that each of the n-channel transistors MN 1 -MN 6 for the circuit 200 are formed to share a common bulk (body) 202 . A further difference is that the source terminals of the n-channel MOS transistors MN 1 -MN 6 are not tied to the common bulk 202 . The common bulk 202 is not, however, a floating node. Yet another difference is that the circuit 200 further includes a circuit 204 to bias the common bulk 202 .

The bias circuit 204 is formed by a pair of n-channel MOS transistors MN 7 and MN 8 whose source-drain paths are connected in series between node A and node B. More specifically, the drain of transistor MN 7 is connected to node A and the drain of transistor MN 8 is connected to node B. The sources of transistors MN 7 and MN 8 are connected to each other and output the bulk bias voltage that is applied to the common bulk 202 . The gate of transistor MN 7 is connected to the drain of transistor MN 8 at node B and the gate of transistor MN 8 is connected to the drain of transistor MN 7 at node A. The transistors MN 7 and MN 8 thus have a cross-coupled circuit configuration.

The effect of the cross-coupled circuit configuration of transistors MN 7 and MN 8 between nodes A and B is that the output bulk bias voltage applied to the common bulk 202 will always remain at a lower voltage among the voltages present at nodes A and B, regardless of operation of the circuit 200 in the high positive voltage mode or high negative voltage mode. This ensures that in the static case there is no forward biasing of the common bulk 202 . So, in the case of operation in the high positive voltage mode (for example, VDD applied to node A and 2*VDD output from node B), the voltage at node A is lower than the voltage at node B and the bias circuit 204 will bias the common bulk 202 at the VDD voltage at node A. In the case of operation in the high negative voltage mode (for example, GND applied to node B and −VDD output from node A), the voltage at node A is lower than the voltage at node B, the bias circuit 204 biases the common bulk 202 at the voltage at node A.

Reference is now made to FIG. 5 . Fabrication of the circuit 200 may take advantage of triple well technology where the circuit 200 is fabricated using an isolated p-type substrate 210 . An n-type well 212 is formed within the p-type substrate 210 . The p-type common bulk 202 is then formed by a p-type well 214 within the n-type well 212 . The n-type source and drain regions (generally referenced as 216 ) for the transistors MN 1 -MN 6 are then formed within the p-type well 214 of the common bulk 202 . The sources of the transistors MN 1 -MN 6 are not tied to the p-type well 214 of the common bulk 202 . Transistors MN 7 and MN 8 for the bias circuit 204 are also formed in the p-type well 214 of the common bulk 202 and differ in construction from the transistors MN 1 -MN 6 in that the sources 218 of transistors MN 7 and MN 8 are tied to their bulk in the p-type substrate 210 through highly doped p-type region 220 .

The triple well technology structure forms two parasitic diodes 230 and 232 . A first parasitic diode 230 is formed between the isolated p-type well 214 and the n-type well 212 . A second parasitic diode 232 is formed between the p-type substrate 210 and the n-type well 212 . In this implementation, the p-type substrate 210 is biased at the ground voltage and the bulk of all transistors MN 1 -MN 8 is at the same potential. In order to ensure that neither of the parasitic diodes 230 and 232 becomes forward biased, a bias signal 226 for the n-type well 212 applies a most positive voltage of the integrated circuit (of course, respecting a safe operating area limit of the integrated circuit) through the highly doped n-type region 228 .

The implementation of the circuit 200 addresses the concerns with the circuit 100 of FIG. 1 . Occupied area is reduced because only a single isolated PWELL is used by all of the transistors MN 1 -MN 8 . Parasitic capacitance is addressed because the common bulk 202 is less capacitive as a result of it not being connected to any capacitor associated with the nodes NA 1 or NA 2 . As a result, the bulk will be first to charge/discharge and this means that there is a reduced probability of bulk current in any operating condition.

Reference is made to FIG. 6 showing a circuit diagram for a voltage doubler circuit 300 . The circuit 300 includes an n-channel MOS transistor MN 11 having a source terminal coupled to node A and a drain terminal coupled to node NA 11 and an n-channel MOS transistor MN 12 having a source terminal coupled to node A and a drain terminal coupled to node NA 12 . The gate terminal of transistor MN 11 is coupled to node NB 12 and the gate terminal of transistor MN 12 is coupled to node NB 11 .

The circuit 300 further includes an n-channel MOS transistor MN 13 having a source terminal coupled to node NA 11 and a drain terminal coupled to node NB 12 and an n-channel MOS transistor MN 14 having a source terminal coupled to node NA 12 and a drain terminal coupled to node NB 11 . The gate terminal of transistor MN 13 is coupled to node NB 11 and the gate terminal of transistor MN 14 is coupled to node NB 12 .

The circuit 300 still further includes an n-channel MOS transistor MN 15 having a drain terminal coupled to node B and a source terminal coupled to node NA 11 and an n-channel MOS transistor MN 16 having a drain terminal coupled to node B and a source terminal coupled to node NA 12 . The gate terminal of transistor MN 15 is coupled to node NB 11 and the gate terminal of transistor MN 16 is coupled to node NB 12 .

A capacitor C 11 has one terminal coupled to node NA 11 and another terminal coupled to receive a clock signal CK. A capacitor C 12 has one terminal coupled to node NA 12 and another terminal coupled to receive a clock signal CKN (which is a logical inversion of the clock signal CK). A bootstrap capacitor Cbs 11 has one terminal coupled to node NB 12 and another terminal coupled to receive a clock signal CKHN. A bootstrap capacitor Cbs 12 has one terminal coupled to node NB 11 and another terminal coupled to receive a clock signal CKH (which is a logical inversion of the clock signal CKHN).

The clock signals CKH and CKHN are generated from the clock signals CK and CKN using a clock voltage boosting circuit 110 shown in FIG. 2 .

The voltage doubler circuit 300 of FIG. 6 is operable to generate either a positive voltage or a negative voltage. When the voltage doubler circuit 300 is to be used as a positive voltage doubler (i.e., operating in a high positive voltage mode), an input voltage such as the supply voltage VDD is connected to node A and an output voltage such as a high positive voltage of 2*VDD is generated at node B. Conversely, when the voltage doubler circuit 200 is to be used as a negative voltage doubler (i.e., operating in a high negative voltage mode), an input voltage such as the ground supply voltage GND is connected to node B and an output voltage such as a high negative voltage of −VDD is generated at node A.

The voltage doubler circuit 300 advantageously operates from just two clocks (CK/CKH and CKN/CKHN).

The voltage doubler circuit 300 operates as follows in the high positive voltage mode:

When circuit is used for positive voltage generation, supply voltage VDD is applied to “A” node and with no clock condition, nodes NA 11 and NA 12 will be charged to “VDD−Vtn” voltage levels. As soon as clock is enabled, assuming CK is “VDD”, CKN is “0”, CKH is “2*VDD” and CKHN is “0”. With this configuration, node NA 11 will be charged to “2*VDD−Vtn” and NA 12 will be charged to “VDD”. Due to cross coupled MN 13 and MN 14 , NB 11 and NB 12 will be charged to “3*VDD” and “VDD” respectively. As NB 11 is at “3*VDD” and NA 11 is at “2*VDD” so NMOS MN 15 has sufficient Vgs to pass 2*VDD voltage from node NA 1 to “B”. In this way, a positive voltage (higher than input supply voltage) is generated and passed on to output node to drive capacitive and current load. During different clock cycles, node NA 11 and NA 12 switches between “VDD” and “2*VDD”. Similarly NB 11 and NB 12 switches between “VDD” and “3*VDD” voltage level.

The voltage doubler circuit 300 operates as follows in the high negative voltage mode:

When the same circuit is used as negative voltage generator, then clock configuration remains same, but input is applied at “B” node and output is taken from “A” node. During negative voltage configuration, “B” node is connected to “GND” and in no clock condition, NA 11 and NA 12 will be charged to “Vtn” voltage level. When CKH goes to “2*VDD” (at this time CK is “VDD”) it switch ON the NMOS MN 15 and charges node NA 11 to “0”. During next clock cycle, when CKH switches from “2*VDD” to “0” and CK changes state from “VDD” to “0” then node NA 11 moves from “0” to “−VDD”. Also node NB 11 discharges to “−VDD” via transistor MN 14 and switch-OFF the transistor MN 15 . In this way, node NA 11 reaches to −VDD voltage level. Due to effect of CKN and CKHN, node NA 12 is charged to “0” via MN 16 . As NA 11 is at “−VDD” and NB 12 is at “VDD” so this configuration switch-ON the transistor “MN 11 ” and pass “−VDD” voltage to “A” node. In this way a negative voltage is generated and passed to “A” node. During negative voltage configuration, node NA 11 and NA 12 switches between “0/−VDD” and vice versa. Similarly nodes NB 11 and NB 12 switches between “VDD/−VDD” and vice versa.

It will be noted that the foregoing voltage levels for positive and negative operation are mentioned with the assumption of an ideal operating situation when there is no current load at the output and there is no charge loss.

In an embodiment, an implementation of the circuit 300 as an integrated circuit utilizes three different isolated P-type wells (PWELLS) for the bulk (body) of the transistors. Those PWELLS include: a first PWELL associated with node A for the bulk of transistors MN 11 and MN 12 ; a second PWELL associated with node NA 11 for the bulk of transistors MN 13 and MN 15 ; and a third PWELL associated with node NA 12 for bulk of transistors MN 14 and MN 16 . In this implementation, the sources of the various transistors MN 11 -MN 16 are tied to their respective bulks.

In an alternative implementation, as shown in FIG. 7 , the circuit 300 ′ differs from the voltage doubler circuit 300 that each of the n-channel transistors MN 11 -MN 16 for the circuit 300 ′ are formed to share a common bulk (body) 202 . A further difference is that the source terminals of the n-channel MOS transistors MN 11 -MN 16 are not tied to the common bulk 202 . The common bulk 202 is not, however, a floating node. Yet another difference is that the circuit 200 ′ further includes a circuit 204 to bias the common bulk 202 .

The bias circuit 204 is formed by a pair of n-channel MOS transistors MN 7 and MN 8 whose source-drain paths are connected in series between node A and node B. More specifically, the drain of transistor MN 7 is connected to node A and the drain of transistor MN 8 is connected to node B. The sources of transistors MN 7 and MN 8 are connected to each other and output the bulk bias voltage that is applied to the common bulk 202 . The gate of transistor MN 7 is connected to the drain of MN 8 at node B and the gate of transistor MN 8 is connected to the drain of MN 7 at node A. The transistors MN 7 and MN 8 thus have a cross-coupled circuit configuration.

The effect of the cross-coupled circuit configuration of transistors MN 7 and MN 8 between nodes A and B is that the output bulk bias voltage applied to the common bulk 202 will always remain at a lower voltage among the voltages present at nodes A and B, regardless of operation of the circuit 300 in the high positive voltage mode or high negative voltage mode. This ensures that in the static case there is no forward biasing of the common bulk 202 . So, in the case of operation in the high positive voltage mode (for example, with VDD applied to node A and 2*VDD output from node B), the voltage at node A is lower than the voltage at node B and the bias circuit 204 will bias the common bulk 202 at the VDD voltage at node A. In the case of operation in the high negative voltage mode (for example, with GND applied to node B and −VDD output from node A), the voltage at node A is lower than the voltage at node B, the bias circuit 204 biases the common bulk 202 at the voltage at node A.

Fabrication of the circuit 300 ′ may take advantage of triple well technology as shown in FIG. 5 and previously described.

The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.