Communication system

The present invention relates to a communications system.

Vehicles such as passenger cars and freight cars are equipped with various loads such as lamps and power windows. Then, there has been proposed a technique of controlling the loads using communication between a plurality of slave devices to which a plurality of loads is connected and a master device controlling the plurality of slave devices.

In the above-described master device and slave devices, when a function addition or a design change occurs, it is necessary to replace the entire master device and slave devices, which causes a problem in cost.

Further, Patent Literature 1 proposes an integrated circuit in which blocks having different functions are provided in a circuit layer, and a wiring layer for wiring the blocks is provided on the upper side of the circuit layer. This integrated circuit also needs to replace the entire circuit layer if a function addition occurs in the circuit layer.

Patent Literature

Patent Literature 1: JP 2010-136452 A

Technical Problem

The present invention has been made in view of the above background, and it is an object of the present invention to provide a communication system capable of performing function addition and design change inexpensively.

Solution to Problem

According to a first aspect of the present invention, there is provided a communication system including:

a plurality of slave devices;

a master device communicating with the plurality of slave devices; and

a plurality of types of circuit blocks, each with different functions and formed on separate substrates,

wherein the slave devices and the master device are configured by combining the plurality of types of circuit blocks.

Preferably, the circuit blocks include:

a control block for controlling the slave devices or the master device;

an input block connected to an input port of the control block for inputting an input signal to the input port; and

an output block having an output switch connected to an output port of the control block and turned on and off according to an output signal.

Preferably, the circuit blocks further include:

a power supply block for supplying power to the control block; and

a communication block having a communication interface.

Preferably, the communication system further includes:

a writing device for writing an ID to the slave devices and the master device,

wherein after transmitting the ID of the master device, the writing device sequentially transmits the IDs of the plurality of slave devices,

wherein the master device includes:

a plurality of output switches provided for each of the plurality of slave devices and for supplying power to the corresponding slave devices;

a first setting unit that receives the ID of the master device from the writing device and sets it as its own ID; and

a switch control unit that turns on the output switch in order each time the ID of the plurality of slave devices is received from the writing device after setting its own ID, and

wherein the plurality of slave devices has a second setting unit that sets the ID received after power supply as its own ID.

Preferably, the master device is installed in a vehicle, the plurality of slave devices is connected to a plurality of loads, the plurality of loads is classified into a load that can be driven at all times, a load that can be driven at accessory time, and a load that can be driven at ignition time, and the same type of load is connected to one of the slave devices.

Preferably, a plurality of the master devices is installed in a vehicle, and the ID of the master device includes installation information indicating the installation position of the master device in the vehicle.

Effect of the Invention

As described above, according to the aspect, the slave devices and the master device are configured by combining the plurality of types of circuit blocks. Therefore, when a function change or a design change occurs, the circuit block can be replaced or added in circuit block units, and the cost can be reduced.

FIG. 1 is a block diagram showing an in-vehicle network as a communication system of the present invention;

FIG. 2 is a view showing blocks which constitute the in-vehicle network shown in FIG. 1 ;

FIG. 3 is a view showing blocks which constitute the in-vehicle network shown in FIG. 1 ;

FIG. 4 is a block diagram showing an example of the in-vehicle network shown in FIG. 1 configured by combining the blocks shown in FIG. 2 and FIG. 3 ;

FIG. 5 is a view showing a configuration of a flash ROM of a microcomputer control block shown in FIG. 3 ;

FIG. 6 is flowcharts showing operation processing procedures of a writing device, a master device and a slave device shown in FIG. 1 ; and

FIG. 7 is flowcharts showing operation processing procedures of a writing device, a master device and a slave device shown in FIG. 1 .

Hereinafter, an embodiment of the present invention will be described based on FIGS. 1 and 2 . FIG. 1 is a block diagram showing an in-vehicle network 1 as a communication system of the present invention. FIGS. 2 and 3 are views showing blocks which constitute the in-vehicle network 1 shown in FIG. 1 . FIG. 4 is a block diagram showing an example of the in-vehicle network 1 shown in FIG. 1 configured by combining the blocks shown in FIG. 2 and FIG. 3 .

The in-vehicle network 1 shown in FIG. 1 is mounted on a vehicle 4 . The in-vehicle network 1 includes a plurality of master devices 2 and a plurality of slave devices 3 (sometimes described as slave devices 301 to 303 as shown in FIG. 4 ). The plurality of master devices 2 is disposed in each area of the vehicle 4 . In this embodiment, the master devices 2 are arranged at five places, that is, front right (FR-RH), front left (FR-LH), front center (FR-CENTER), rear right (RR-RH), rear left (RR-LH) of vehicle 4 .

The five master devices 2 are communicably connected to each other by a communication line L 1 . The master devices 2 are connected to each other by a +B power supply line L 2 connected to a battery (not shown), and are supplied with power via the +B power supply line L 2 .

Further, each of the five master devices 2 is communicably connected to the plurality of slave devices 3 disposed in their own area by the communication line L 1 . The master device 2 and the slave devices 3 are connected in a one-to-multiple manner. The master device 2 controls the operations of the plurality of slave devices 3 by communicating with the plurality of slave devices 3 . The slave device 3 is connected to a plurality of loads 5 ( FIG. 4 ) such as a lamp, a seat motor, and a door motor disposed in its own area, and controls driving of the load 5 according to communication with the master device 2 .

The slave devices 3 in respective areas are provided separately for +B connected to the loadable drive 5 at all times, for ACC connected to the loadable drive 5 at the time of accessory, and for IG connected to the loadable drive 5 at ignition.

In the present embodiment, the above-described master device 2 and slave device 3 are respectively configured by combining a power supply block 6 , a communication block 7 , control blocks 8 and 9 , input blocks 10 A and 10 B, and output blocks 11 A and 11 B shown in FIGS. 2 and 3 . The blocks 6 to 11 A and 11 B (circuit blocks) are provided on separate substrates, respectively, and can be combined to form various types of in-vehicle networks 1 .

The power supply block 6 shown in FIG. 2 is a block that converts a power supply Vp (for example, 12V) to generate a 5V power supply capable of supplying power to control blocks 8 and 9 described later. The substrate of the power supply block 6 is provided with a power supply terminal T 61 , a ground terminal T 62 , a power supply circuit 63 , and a 5V power supply terminal T 64 .

The power supply terminal T 61 and the ground terminal T 62 are terminals connected to the power supply and the ground respectively. The power supply circuit 63 is a circuit that converts the power supply Vp connected to the power supply terminal T 61 to generate a predetermined voltage (5V in the present embodiment). The 5V power supply terminal T 64 is a terminal connected to the 5V power supply generated by the power supply circuit 63 .

A communication block 7 shown in FIG. 2 is a block for performing communication between control blocks 8 and 9 described later. A plurality of communication terminals T 71 and T 72 , a communication IF circuit 73 , a power supply terminal T 74 , and a ground terminal T 75 are provided on the substrate of the communication block 7 . In the present embodiment, the communication block 7 is provided with two types of a LIN communication terminal T 71 and a CAN communication terminal T 72 . The communication IF circuit 73 is an interface circuit that enables input and output of signals corresponding to various types of communication (in this embodiment, CAN and LIN) from the communication terminals T 71 and T 72 . The power supply terminal T 74 and the ground terminal T 75 are terminals connected to the power supply and the ground respectively. The power supply Vp and the ground connected to the terminals T 74 and T 75 are supplied to the communication IF circuit 73 .

Control blocks 8 and 9 shown in FIG. 3 are blocks that control the entire control of the master device 2 and the slave devices 3 . In the present embodiment, there are two types of control blocks 8 and 9 : a microcomputer-control block 8 in which a microcomputer 84 is mounted, and an IC-control block 9 in which an IC 94 is mounted.

The substrate of the microcomputer-control block 8 is provided with a power supply terminal T 81 , a ground terminal T 82 , a 5V power supply terminal T 83 , a microcomputer 84 , a plurality of input terminals T 85 , a plurality of output terminals T 86 , a plurality of input terminals T 87 , and communication terminals T 88 and T 89 . The power supply terminal T 81 , the ground terminal T 82 , and the 5V power supply terminal T 83 are terminals connected to the power supply, the ground, and the 5V power supply respectively. The microcomputer 84 incorporates input ports P 11 to P 18 , output ports P 21 to P 28 , AD ports P 31 to P 33 , PWM output (not shown), timer, communication function, RAM, CPU (central processing unit) 84 A, flash ROM (Read Only Memory) 84 B etc.

The CPU 84 A controls the entire master device 2 and slave devices 3 and performs various processes in accordance with a processing program. In the flash ROM 84 B, as shown in FIG. 5 , a non-writing object area A 1 not to be written by a writing device 14 described later and a writing object area A 2 to be written by the writing device 14 described later are formed.

In the non-writing object area A 1 , a basic control area A 11 , a setting value area A 12 , and a writing control area A 13 are formed. In the basic control area A 11 , settings of functions such as communication and a basic operation program are stored. Various setting values are stored in the setting value area A 12 . In the writing control area A 13 , a program for writing in the write object area A 2 described later is stored.

In the writing object area A 2 , an input control area A 21 , an application control area A 22 , an output control area A 23 , and an ID area A 24 are formed. The input control area A 21 stores a program for determining input based on input signals from the input ports P 11 to P 18 . The application control area A 22 stores a program for transmitting an input determination result as input determination data by communication, and a program for determining a load operation based on input determination data received by communication. The output control area A 23 stores a program for outputting an output signal from the output ports P 21 to P 28 based on a load operation determination result. An ID required for communication is stored in the ID area A 24 .

Further, in the present embodiment, eight input terminals T 85 shown in FIG. 3 are provided and connected to input ports P 11 to P 18 of the microcomputer 84 . In the present embodiment, eight output terminals T 86 are provided and connected to output ports P 21 to P 28 of the microcomputer 84 . In the present embodiment, eight input terminals T 87 are provided and connected to AD ports P 31 to P 38 of the microcomputer 84 . The communication terminals T 88 and T 89 are terminals for inputting and outputting communication signals, and in the present embodiment, two types of communication terminals T 88 for LIN and T 89 for CAN are provided.

The IC control block 9 is a block that controls control of the slave device 3 . The substrate of the IC control block 9 is provided with a power terminal T 91 , a ground terminal T 92 , a 5V power terminal T 93 , an IC 94 , a plurality of input terminals T 95 , a plurality of output terminals T 96 , a plurality of input terminals T 97 , and a communication terminal T 98 .

The power supply terminal T 91 , the ground terminal T 92 , and the 5V power supply terminal T 93 are terminals connected to the power supply, the ground, and the 5V power supply respectively. Incidentally, when the power supply function is built in the IC 94 described later, the 5V power supply terminal T 93 is not necessary. The IC 94 incorporates input ports P 11 to P 18 , output ports P 21 to P 28 , AD ports P 31 to P 38 and a CPU 94 A. The IC 94 incorporates a well-known CPU 94 A, and the presence or absence of the communication function and the power supply function differs depending on the IC used. Therefore, the IC control block 9 may be used alone, or the IC control block 9 and the communication block 7 or the power supply block 6 may be used in combination. The IC 94 is a custom IC or a dedicated IC, and control specifications cannot be written in the IC.

Further, in the present embodiment, eight input terminals T 95 are provided, and connected to input ports P 11 to P 18 of the IC 94 . The plurality of output terminals T 96 are connected to output ports P 21 to P 28 of the IC 94 . The input terminals T 97 are connected to AD ports P 31 to P 38 of the IC 94 . The communication terminal T 98 is a terminal for inputting and outputting a communication signal, and in the present embodiment, a communication terminal T 98 for LIN is provided.

Input blocks 10 A and 10 B shown in FIG. 2 are blocks connected to input ports P 11 to P 18 of the control blocks 8 and 9 for inputting input signals to the input ports P 11 to P 18 . A power supply terminal T 101 , a ground terminal T 102 , a plurality of local switches SW, and a plurality of output terminals T 103 are formed on substrates of the input blocks 10 A and 10 B. The power supply terminal T 101 and the ground terminal T 102 are terminals connected to the power supply and the ground respectively. The plurality of local switches SW is switches for operating the load 5 by the user. In the present embodiment, four local switches SW are provided, which are smaller than the number of input terminals T 85 and T 95 of the control blocks 8 and 9 .

The output terminal T 103 is a terminal for outputting the on/off state of the local switch SW, and is provided in the same number as the local switch SW. In this embodiment, as the input blocks 10 A and 10 B, two types are illustrated of the block 10 A in which Low (ground) is output from the output terminal T 103 when the local switch SW is turned on, and the block 10 B in which High (power supply) is output. Note that the present invention is not limited to this, and the output terminal T 103 for outputting High and the output terminal T 103 for outputting Low may be mixed.

The output blocks 11 A and 11 B are connected to the output ports P 21 to P 28 of the control blocks 8 and 9 , respectively, and semiconductor relays CH 1 to CH 4 (output switches) which are turned on and off according to output signals are formed on each of the output blocks 11 A and 11 B. A power terminal T 111 , a ground terminal T 112 , a plurality of semiconductor relays CH 1 to CH 4 , a plurality of input terminals T 113 , and a plurality of output terminals T 114 and T 115 are provided on each substrate of the output blocks 11 A and 11 B. The power supply terminal T 111 and the ground terminal T 112 are terminals connected to the power supply and the ground respectively. The plurality of semiconductor relays CH 1 to CH 4 is formed of, for example, an IPD capable of current detection. Incidentally, the plurality of semiconductor relays CH 1 to CH 4 is not limited to this, and may be composed of a mechanical relay or a general-purpose MOSFET and a shunt resistor, or may be composed of a sense MOSFET.

The plurality of input terminals T 113 is provided in one-to-one correspondence with the semiconductor relays CH 1 to CH 4 , and output signals from the microcomputer 84 and the IC 94 are input to the input terminals T 113 . The semiconductor relays CH 1 to CH 4 are turned on and off according to the input output signal. The plurality of output terminals T 114 is provided in one-to-one correspondence with the semiconductor relays CH 1 to CH 4 , and the power supply or the ground is output to the output terminals T 114 when the corresponding semiconductor relays CH 1 to CH 4 are turned on. The output terminal T 115 is provided in one-to-one correspondence with the semiconductor relays CH 1 to CH 4 , and is a terminal from which the current flowing through the semiconductor relays CH 1 to CH 4 is output as detection current.

In the present embodiment, two types of output blocks 11 A and 11 B are exemplified: block 11 A in which the power supply is output from output terminal T 115 , and block 11 B in which ground is output when semiconductor relays CH 1 to CH 4 are turned on.

FIG. 4 is a block diagram showing an example of the in-vehicle network 1 configured by combining the blocks described above. As shown in FIG. 4 , the master device 2 includes the power supply block 6 , the communication block 7 , the microcomputer control block 8 , two input blocks 10 A and 10 B, and the output block 11 A.

The semiconductor relays CH 1 to CH 3 constituting the master device 2 are connected to the +B, ACC, and IG slave devices 301 to 303 via the +B power supply line L 3 , the ACC power supply line L 4 , and the IG power supply line L 5 respectively. The slave device 3 is not connected to the semiconductor relay CH 4 . The semiconductor relays CH 1 to CH 3 are turned on according to the output signal from the microcomputer 84 , and supply power from the +B power supply line L 2 to the corresponding slave devices 301 to 303 through the +B power supply line L 3 , the ACC power supply line L 4 , and the IG power supply line L 5 respectively.

The slave device 301 for +B includes the power supply block 6 , the IC control block 9 , the input block 10 A, and the output blocks 11 A and 11 B. The IC control block 9 used in the slave device 301 incorporates a communication function, and the communication block 7 is not necessary.

The slave device 302 for ACC includes the communication block 7 , the IC control block 9 , the input block 10 A, and the output block 11 A. The IC control block 9 incorporates a power supply function, and the power supply block 6 is not necessary.

The slave device 303 for IG includes the IC control block 9 , the input block 10 A, and the output block 11 A. The IC control block 9 incorporates a power supply function and a communication function, and the power supply block 6 and the communication block 7 are not necessary.

The semiconductor relays CH 1 to CH 4 constituting these slave devices 301 to 303 are connected to the loads 5 , are turned on in response to the output signals from the control blocks 8 and 9 , and supply power to the loads 5 .

Next, bit assignments of signals transmitted and received between the master device 2 and the slave device 3 will be described with reference to Table 1 below.

As shown in Table 1 above, the first bit7 to bit0 represent the IDs of the master devices 2 and the slave devices 3 . The ID is information that is assigned to all the master devices 2 and slave devices 3 disposed in the vehicle 4 without duplication. The ID is composed of installation information, type information, transmission/reception information, and slave information.

Bit7 to bit4 are assigned to the installation information. Bit7 to bit6 indicate the installation position in the traveling direction of the vehicle 4 ; “01” if the installation position of the slave device 3 is on the front side of the vehicle 4 ; “10” if on the rear side; and “11” if in the center of the traveling direction. Bit5 to bit4 indicate the installation position of the vehicle 4 ; “01” if the installation position of the slave device 3 is the right side of the vehicle 4 ; “10” if the left side; and “11” if in the center of the left-right direction.

As type information, bit3 is assigned, and becomes “0” in the case of the slave device 3 and becomes “1” in the case of the master device 2 .

As transmission/reception information, bit2 is assigned, and becomes “1” when the slave device 3 transmits to the master device 2 and becomes “0” when the slave device 3 receives data from the master device 2 .

As slave information, bit1 to bit0 are assigned. The slave information is information that is allocated without duplication to a plurality of slave devices 3 connected to the same master device 2 (the slave devices 3 connected to different master devices 2 may overlap). Although the slave information is represented by 2 bits in the present embodiment, the number of bits may be increased according to the number of slave devices 3 connected to the master device 2 .

BYTE1 of bit7 to bit0 following the ID represents input judgement data after setting the ID. Each of bit7 to bit0 is assigned to a plurality of output ports P 21 to P 28 respectively. Then, if each bit-n (n is an arbitrary integer of 0 to 7) is “0”, it indicates that the semiconductor relays CH 1 to CH 4 connected to the output port P 2 (n+1) assigned to the bit-n are off. If each bit-n is “1”, it indicates that the semiconductor relays CH 1 to CH 4 connected to the output port P 2 (n+1) assigned to the bit n are on.

Next, the ID setting operation of the in-vehicle network 1 configured as described above will be described with reference to the flowcharts of FIGS. 6 and 7 . Incidentally, in the initial state (when ID is not set), the same initial ID (initial reception ID, initial transmission ID) is set in all the microcomputer control blocks 8 . Further, since the IC control block 9 confirms the state of an external switch (not shown) and recognizes the ID, it is not necessary to set the ID by the writing device 14 .

In the writing device 14 , the ID of the master device 2 in each area and the ID of the slave device 3 are set. Further, in the writing device 14 , it is set in advance whether each slave device 3 is configured by the microcomputer control block 8 or the IC control block 9 .

First, the user connects the writing device 14 ( FIG. 1 ) to the communication line L 1 . In the writing device 14 , the order of the areas where the ID is desired to be set is set. For example, in the example shown in FIG. 1 , FR-RH→RR-RH→RR-LH→FR-LH→FR-CENTER, or FR-CENTER→FR-LH→RR-LH→RR-RH→FR-RH according to the connection order of the communication line L 1 is set.

After being activated, the writing device 14 executes an ID setting process of the FR-RH area. In the ID setting process, the writing device 14 transmits an ID setting request signal a predetermined number of times (step S 101 ). The bit assignment of the ID setting request signal is shown in Table 2 below.

As shown in Table 2, in the ID setting request signal, bit7 to bit0 of the ID become “0”, and in the following BYTE1, the device that needs ID setting is set. In the present embodiment, bit7 of BYTE1 is assigned to the master device 2 . In bit7 of BYTE1, “1” is stored when the ID setting of the master device 2 is requested, and “0” is stored when the ID setting is not requested.

Now, slave devices 3 connected to the output ports P 21 to P 24 of the master device 2 are referred to as slave devices 301 to 304 . Note that in the example shown in FIG. 4 , the slave device 304 is not shown. Bit3 to bit0 of BYTE1 are assigned to the slave devices 301 to 304 connected to the output ports P 21 to P 24 of the master device 2 . In bit3 to bit0 of BYTE1, “1” is stored when requesting the ID setting of the slave devices 301 to 304 , and “0” is stored when not requesting the ID setting. Also, bit6 to bit4 of BYTE1 are reserves.

In step S 101 , in order to set the ID of the master device 2 , the writing device 14 transmits an ID setting request signal in which only bit7 of BYTE1 is “1” and the other bits bit6 to bit0 are “0”.

Thereafter, the writing device 14 waits for a predetermined time T 1 to elapse (Y in step S 102 ), and transmits a setting signal indicating the IDs of the master device 2 and slave devices 301 to 304 in the input area (step S 103 ). Table 3 below shows the bit assignment of the setting signal.

In the setting signal, one of the transmission ID and the reception ID of the master device 2 (in the embodiment, the transmission ID) is set in bit7 to bit0 of the ID, and the IDs of the slave devices 301 to 304 connected to the output ports P 21 to P 24 of the master device 2 are set in the subsequent BYTE1 to BYTE4. That is, if there are four slave devices 3 connected to the master device 2 , the first ID and the four BYTEs BYTE1 to BYTE4 are sequentially transmitted as setting signals. Note that in the example shown in FIG. 3 , since there are three slave devices 301 to 303 connected to the master device 2 , unlike Table 3, the BYTE4 corresponding to the slave device 304 is set to an initial value “0”.

In the example shown in Table 3, “0101” indicating the front and the right is set to bit7 to bit4 of the ID. Further, “1” indicating the master device 2 is stored in bit3 of the ID. Further, “1” indicating that it is a transmission ID is stored in bit2 of the ID. Also, “0” is stored in bit1 to bit0. Further, “0101” indicating the front and the right is stored in bits bit7 to bit4 of BYTE1 to BYTE4. Further, “0” indicating the slave device 3 is stored in bit3 of BYTE1 to BYTE4. Different values are stored in bit1 to bit0 of BYTE1 to BYTE4, respectively.

Also, the user activates the master device 2 in the order of the areas where the user wants to set the ID. At first, the master device 2 in the FR-RH area is activated. After activated, the CPU 84 A of the master device 2 (hereinafter, also simply referred to as the master device 2 ) executes the processes shown in FIG. 6 , and first performs power-on reset and initialization process (steps S 201 and S 202 ).

Then, the master device 2 determines whether or not an ID setting request signal in which the bit7 of the byte allocated to the master device 2 is “1” and the others are “0” within the predetermined time T 2 is received or not (step S 203 ). If the ID setting request has not been received (N in step S 203 ), the master device 2 executes the normal process (step S 204 ), and ends the process.

On the other hand, when the master device 2 receives the ID setting request signal (Y in step S 203 ), the master device 2 next determines whether a setting signal has been received or not (step S 205 ).

When the setting signal is received (Y in step S 205 ), the master device 2 writes the ID portion of the setting signal as its own ID in the flash ROM 84 B (step S 206 ). At this time, the master device 2 inverts bit2 of the ID and writes both the transmission ID and the reception ID in the flash ROM 84 B. Thereby, ID authentication of the master device 2 is performed.

Next, the master device 2 writes BYTE1 to BYTE4 as the IDs of the slave devices 301 to 304 in the flash ROM 84 B (step S 207 ). Similarly, the master device 2 inverts bit2 of BYTE and writes both the transmission ID and the reception ID in the flash ROM 84 B.

In the example illustrated in FIG. 4 , the master device 2 receives the setting signal including the ID and BYTE1 to BYTE4 from the writing device 14 , and writes BYTE1 to BYTE3 as the IDs of the slave devices 301 to 303 connected to the output ports P 21 to P 23 in the flash ROM 84 B. Since BYTE4 is the initial value, it is not written.

Thereafter, the master device 2 transmits an ID setting end signal (step S 208 ). After the transmission of the ID setting signal (step S 103 ), if the ID setting end signal cannot be received within the predetermined time T 3 (N in step S 104 of FIG. 7 ), the writing device 14 cancels the process (step S 114 ). On the other hand, after transmitting the setting signal (step S 103 ), if the writing device 14 can receive the ID setting end signal within the predetermined time T 3 (Y in step S 104 ), the writing device 14 determines whether there is a slave device 3 for which ID setting is required (step S 105 ).

As described above, whether the slave device 3 is configured by the microcomputer control block 8 or the IC control block 9 is input to the writing device 14 by the user in advance. If there is a slave device 3 composed of the microcomputer control block 8 among the slave devices 3 in the area for which an ID is to be set, the writing device 14 determines in step S 105 that there is a slave device 3 for which ID setting is required.

As shown in FIG. 4 , when all the slave devices 301 to 303 are configured from the IC control block 9 , the writing device 14 determines that there is no slave device 3 for which ID setting is required (N in step S 105 ), and the process immediately proceeds to step S 113 .

On the other hand, when it is determined that there is a slave device 3 for which ID setting is required (Y in step S 105 ), the writing device 14 determines whether it is necessary to set the ID of the slave device 30 n (n is an arbitrary integer and is set to 1 in the initial state) connected to the output port P 2 n of the master device 2 (step S 106 ). If the slave device 30 n is configured by the IC control block 9 , the writing device 14 determines that the setting of the ID is not necessary (N in step S 106 ), and the process proceeds to step S 111 .

If the slave device 30 n is configured by the microcomputer control block 8 , the writing device 14 determines that the setting of the ID is necessary (Y in step S 106 ), and transmits the ID setting request signal a predetermined number of times (Step S 107 ). The ID setting request signal is a signal in which only the bit-n corresponding to the slave device 30 n of BYTE1 is set to “1” according to the bit assignment in Table 2 above. After a predetermined time T 4 has elapsed (Y in step S 108 ), the writing device 14 transmits a setting signal in which an ID corresponding to the slave device 30 n is set and BYTE1 to BYTE4 are set to “0” in the ID area (step S 109 ). Note that the setting signal for the slave device 301 is as shown in Table 4 below.

After transmitting the ID setting end signal (step S 208 in FIG. 6 ), if the master device 2 cannot receive the ID setting request signal (N in Step S 209 in FIG. 7 ), after turning off all the semiconductor relays CH 1 to CH 4 (step S 210 ), the process proceeds to step S 212 .

When receiving the ID setting request signal (Y in step S 209 ), the master device 2 turns on the semiconductor relay CH-n corresponding to bit-n which is “1” (step S 211 ), and then proceeds to step S 212 .

As a result, power is supplied to the slave device 30 n connected to the semiconductor relay CH-n, and the slave device 30 n is activated. After activated, the slave device 30 n executes power on reset and initialization process (steps S 301 and S 302 ), and determines whether the ID setting request signal has been received within a predetermined time T 5 (step S 303 ). If the ID setting request cannot be received within the predetermined time T 5 (N in step S 303 ), the slave device 30 n executes the normal process (step S 304 ), and ends the process.

On the other hand, if the ID setting request can be received within the predetermined time T 5 (Y in step S 303 ), the slave device 30 n determines whether the setting signal can be received (step S 305 ). If the slave device 30 n can receive the setting signal (Y in step S 305 ), the slave device 30 n writes the ID portion of the setting signal as its own ID in the flash ROM 84 B (step S 306 ). Then, the slave device 30 n transmits an ID setting end signal (step S 307 ), and ends the process.

If the writing device 14 cannot receive the ID setting end signal from the slave device 30 n within a predetermined time T 6 after transmitting the setting signal (step S 109 ) (N in step S 110 ), the writing device 14 ends the process (step S 114 ). On the other hand, when the writing device 14 receives an ID setting end signal from the slave device 30 n within the predetermined time T 6 (Y in step S 110 ), the writing device 14 proceeds to step S 111 .

In step S 111 , the writing device 14 determines whether or not the ID setting for all slave devices 3 requiring the ID setting has been completed. If the writing device 14 determines that the process has not ended (N in Step S 111 ), the writing device 14 increments n (Step S 112 ), and then returns to step S 106 immediately.

On the other hand, when the writing device 14 determines that the process has been completed (Y in step S 111 ), after transmitting the ID setting completion signal (step S 113 ), the writing device 14 ends the process. When the master device 2 receives the ID setting completion signal (Y in step S 212 ), the master device 2 ends the process immediately. On the other hand, if the master device 2 has not received the ID setting completion signal (N in step S 212 ), the process returns to step S 209 .

After executing the above-described steps S 101 to S 114 corresponding to the FR-RH area, the writing device 14 sequentially executes the above-described steps S 101 to S 114 corresponding to the next area. In response to this, the user activates the slave device 3 corresponding to the area. Thereby, the IDs can be set to the master device 2 and the slave devices 3 .

According to the above-described embodiment, the master device 2 and the plurality of slave devices 3 are configured by combining plural types of blocks 6 to 11 A and 11 B. Therefore, when a function change or design change occurs, it can be replaced or added in units of blocks 6 to 11 A and 11 B, and cost reduction can be achieved.

According to the embodiment described above, the blocks include: control blocks 8 and 9 which control the slave device 3 or the master device 2 ; input blocks 10 A and 10 B connected to input ports P 11 to P 18 of control blocks 8 and 9 for inputting input signals to the input ports P 11 to P 18 ; and output blocks 11 A and 11 B connected to output ports P 21 to P 28 of control blocks 8 and 9 and having semiconductor relays CH 1 to CH 4 turned on and off according to output signals.

As a result, when a function change or a design change occurs, cost reduction can be achieved by replacing or adding the control blocks 8 and 9 , the input blocks 10 A and 10 B, and the output blocks 11 A and 11 B. Further, the number of elements for inputting an input signal and the number of semiconductor relays CH 1 to CH 4 can be minimized.

Further, according to the embodiment described above, the blocks include the power supply block 6 for supplying power to the control blocks 8 and 9 , and the communication block 7 having the communication interface. Thereby, control blocks 8 and 9 which do not have a power supply function or a communication function can also be used, and design assets developed with other products can be diverted.

Also, according to the embodiment described above, the master device 2 receives the ID of the master device 2 from the writing device 14 and sets it as its own ID. Also, after setting the ID of its own, the master device 2 turns on the semiconductor relays CH 1 to CH 4 in order each time it receives the IDs of the plurality of slave devices 3 from the writing device 14 . The plurality of slave devices 3 set the ID received after power supply as their own ID. As a result, since it is not necessary to set the ID every time the slave device 3 is connected (assembled), the setting time of the ID can be shortened and erroneous setting can be reduced.

Further, according to the embodiment described above, the master device 2 is installed in the vehicle 4 , and the plurality of slave devices 3 are connected to the plurality of loads 5 . The plurality of loads 5 are classified into a load 5 that can be driven at all times, a load 5 that can be driven at the time of an accessory, and a load 5 that can be driven at the time of ignition. Then, the same type of load 5 is connected to one slave device 3 . As a result, power can be supplied to the slave device 3 and the setting of the ID can be performed using the semiconductor relays CH 1 to CH 4 for enabling the load 5 to be driven.

According to the embodiment described above, a plurality of master devices 2 are installed in the vehicle 4 , and the ID stored in the flash ROM 24 B includes installation information indicating the installation position of the master device 2 in the vehicle 4 . As a result, it is possible to easily set different IDs for the slave devices 3 set in the vehicle 4 .

Although the input blocks 10 A and 10 B are configured of the local switches SW according to the above-described embodiment, the present invention is not limited to this. The input blocks 10 A and 10 B may be any one as long as they can input an input signal to the control blocks 8 and 9 , and may be constituted by, for example, a sensor.

Further, according to the above-described embodiment, the slave device 3 and the master device 2 are configured by combining the power supply block 6 , the communication block 7 , the control blocks 8 , 9 , the input blocks 10 A, 10 B, and the output blocks 11 A, 11 B. However, the present invention is not limited to this. If one having a power supply function and a communication function is used as the control blocks 8 and 9 , only the control blocks 8 and 9 , the input blocks 10 A and 10 B, and the output blocks 11 A and 11 B may be combined.

Further, according to the above-described embodiment, the writing device 14 transmits the IDs of the slave devices 301 to 30 n, but the present invention is not limited to this. The master device 2 may sequentially transmit the IDs of the slave devices 301 to 30 n.

Note that the present invention is not limited to the above embodiment. That is, various modifications can be made without departing from the scope of the present invention.

1 in-vehicle network (communication system)

2 master device

3 , 301 to 303 slave devices

4 vehicle

5 load

6 power supply block (circuit block)

7 communication block (circuit block)

8 , 9 control block (circuit block)

10 A, 10 B input block (circuit block)

11 A, 11 B output block (circuit block)

14 writing device

84 A CPU (first setting unit, switch control unit, second setting unit)

CH 1 to CH 4 semiconductor relay (output switch)

P 11 to P 18 input port

P 21 to P 28 output port