Driving circuit for power switch

This application is a Continuation Application of U.S. patent application Ser. No. 15/332,623 filed on Oct. 24, 2016 and entitled “DRIVING CIRCUIT FOR POWER SWITCH”, which claims priority to China patent application No. 201510867765.X filed on Dec. 1, 2015 and entitled “DRIVING CIRCUIT FOR POWER SWITCH”, the entirety of which is hereby incorporated by reference.

The present invention relates to a driving circuit, and more particularly to a driving circuit for a power switch.

A switching power supply is widely used in an electronic device. For reducing the size and weight of the switching power supply, the frequency of the switching power supply is gradually increased. Consequently, the volumes of the passive components (e.g., inductors or capacitors) of the switching power supply are reduced. FIG. 1 is a plot illustrating the relationship between the driving loss and the switching frequency of a switching power supply. The driving loss of the switch element of the switching power supply is positively correlated with the switching frequency. As the switching frequency of the switching power supply is gradually increased, the driving loss gradually increases. In views of power-saving efficacy, the switching power supply of the electronic device should have enhanced efficiency even if the volume of the switching power supply is reduced. Consequently, it is important to reduce the driving loss of the switch element.

FIG. 2 is a schematic circuit diagram illustrating a driving circuit for a switch element according to the prior art. As shown in FIG. 2 , the driving circuit comprises driving switches S 11 and S 12 and a resistor R. The capacitor Ciss is an input capacitor of a power switch (not shown). When the driving switch S 11 is turned on, the input capacitor of the power switch is charged. When the driving switch S 12 is turned on, the input capacitor of the power switch is discharged. The resistor R is a parasitic resistor of the charge/discharge loop.

FIG. 3 is a schematic circuit diagram illustrating a conventional metal oxide semiconductor field effect transistor (MOSFET). The voltage difference between the gate terminal G and the source terminal S of the MOSFET is Vgs. The voltage difference between the gate terminal G and the source terminal D of the MOSFET is Vgd. The capacitance of the input capacitor Ciss is expressed as: Ciss=Cgs+Cgd×(Vgd/Vgs). In the above formula, Cgs is the capacitance between the gate terminal and the source terminal S, and Cgd is the capacitance between the gate terminal G and the drain terminal D. Generally, the magnitude of the input capacitor Ciss corresponding to the voltage difference Vgs is provided from the specifications of the MOSFET.

The operations of the driving circuit will be described as follows. For charging the input capacitor Ciss, the driving switch S 11 is turned on and the driving switch S 12 is turned off. Consequently, the input capacitor Ciss is charged to a supply voltage Vcc through the driving switch S 11 and the resistor R. The driving switch S 11 is maintained in the on state and the driving switch S 12 is maintained in the off state until the charging procedure of the input capacitor Ciss is completed. In the charging procedure, the energy consumed by the resistor R is equal to 0.5×Ciss×Vcc 2 . For discharging the input capacitor Ciss, the driving switch S 11 is turned off and the driving switch S 12 is turned on. Consequently, the input capacitor Ciss is discharged to OV through the driving switch S 12 and the resistor R. The driving switch S 11 is maintained in the off state and the driving switch S 12 is maintained in the on state until the discharging procedure of the input capacitor Ciss is completed. In the discharging procedure, the energy consumed by the resistor R is also equal to 0.5×Ciss×Vcc 2 .

For reducing the total consumed energy of the resistor R in the charging/discharging procedures, another driving circuit for the power switch is disclosed. FIG. 4 is a schematic circuit diagram illustrating another driving circuit for a switch element according to the prior art. FIG. 5 is schematic timing waveform diagram illustrating associated signals of the components of the driving circuit of FIG. 4 . In this driving circuit, a constant current source is used for charging or discharging the input capacitor Ciss. For charging the input capacitor Ciss, the driving switches S 21 and S 23 are turned on in the time interval between t 0 and t 1 . Consequently, the current flowing through the inductor L reaches a nearly-constant value I 1 . Then, the driving switches S 21 and S 23 are turned off. Consequently, in the time interval between t 1 and t 2 , the inductor L provides the nearly-constant value I 1 to charge the input voltage Ciss to the supply voltage Vcc. When the input voltage Ciss is charged to the supply voltage Vcc (i.e., at the time point t 2 ), the driving switches S 22 and S 24 are turned on. Meanwhile, the charging procedure of the input voltage Ciss is completed. Since the current flowing through the resistor R is nearly constant in the charging procedure, the energy consumed by the resistor R is lower. For discharging the input capacitor Ciss, the driving switches S 22 and S 25 are turned on in the time interval between t 2 and t 3 . Consequently, the current flowing through the inductor L reaches a nearly-constant value I 2 . Then, the driving switches S 22 and S 24 are turned off. Consequently, in the time interval between t 3 and t 4 , the inductor L provides the nearly-constant value I 2 to discharge the input voltage Ciss to 0V. When the input voltage Ciss is discharged to 0V (i.e., at the time point t 4 ), the driving switches S 21 and S 23 are turned on. Meanwhile, the discharging procedure of the input voltage Ciss is completed. Since the current flowing through the resistor R is nearly constant in the discharging procedure, the energy consumed by the resistor R is lower.

However, since the inductor L has to provide the nearly-constant current in the charging procedure and the discharging procedure of the input capacitor Ciss of the power switch, lager inductance of the inductor L is required. That is, the inductor L has bulky volume. Moreover, since the current flows through the inductor L whenever the input capacitor Ciss is charged or discharged, the energy loss of the inductor L is larger.

Therefore, there is a need of providing an improved driving circuit for a power switch in order to overcome the above drawbacks.

The present invention provides a driving circuit for a power switch. The inductor of the driving circuit does not need to provide the constant current. Under this circumstance, smaller inductance of the inductor is required, and thus the volume of the inductor is reduced. Moreover, the energy loss of the driving circuit is reduced when compared with the conventional driving circuit.

In accordance with an aspect of the present invention, there is provided a driving circuit for driving a power switch. The driving circuit includes an inductor and at least one driving circuit. The at least one driving circuit is electrically connected with the inductor. The driving circuit and the power switch are collaboratively defined as an equivalent circuit. The equivalent circuit includes a first equivalent capacitor, an equivalent inductor and a second equivalent capacitor. The first equivalent capacitor corresponds to an input capacitor of the power switch. The equivalent inductor comprises the inductor. The equivalent inductor is connected with the first equivalent capacitor in series. The second equivalent capacitor corresponds to a parasitic parameter of at least one driving switch. The first equivalent capacitor, the equivalent inductor and the equivalent resistor are serially connected with each other to define a charge/discharge loop. Moreover, a charging procedure or a discharging procedure of the first equivalent capacitor is performed through the charge/discharge loop. While a voltage of the input capacitor is changed from a voltage corresponding to no inductor current to a first set voltage in the charging procedure of the first equivalent capacitor, or while the voltage of the input capacitor is changed from the voltage corresponding to no inductor current to a second set voltage in the discharging procedure of the first equivalent capacitor, the first equivalent capacitor has a first change amount of charges. While the voltage of the input capacitor is changed from the voltage corresponding to no inductor current to a steady voltage, the second equivalent capacitor has a second change amount of charges. The first change amount of charges is larger than or equal to the second change amount of charges. The first set voltage is higher than a maximum threshold of a gate terminal of the power switch, and the second set voltage is lower than a minimum threshold of the gate terminal of the power switch.

The above contents of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

FIG. 1 is a plot illustrating the relationship between the driving loss and the switching frequency of a switching power supply;

FIG. 2 is a schematic circuit diagram illustrating a driving circuit for a switch element according to the prior art;

FIG. 3 is a schematic circuit diagram illustrating a conventional metal oxide semiconductor field effect transistor;

FIG. 4 is a schematic circuit diagram illustrating another driving circuit for a switch element according to the prior art;

FIG. 5 is schematic timing waveform diagram illustrating associated signals of the components of the driving circuit of FIG. 4 ;

FIG. 6 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a first embodiment of the present invention;

FIG. 7 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 6 in the charging procedure of the input capacitor;

FIG. 8 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 6 in the discharging procedure of the input capacitor;

FIG. 9 is a schematic circuit diagram illustrating the equivalent circuit of the driving circuit of FIG. 6 ;

FIG. 10 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a second embodiment of the present invention;

FIG. 11 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 10 in the charging procedure of the input capacitor;

FIG. 12 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a third embodiment of the present invention;

FIG. 13 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 12 in the charging procedure and the discharging procedure of the input capacitor;

FIG. 14 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a fourth embodiment of the present invention;

FIG. 15 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 14 in the charging procedure of the input capacitor;

FIG. 16 is another schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 14 in the charging procedure of the input capacitor;

FIG. 17 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a fifth embodiment of the present invention;

FIG. 18 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 17 in the charging procedure of the input capacitor;

FIG. 19 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a sixth embodiment of the present invention;

FIG. 20 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 19 in the discharging procedure of the input capacitor;

FIG. 21 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a seventh embodiment of the present invention;

FIG. 22 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 21 in the charging procedure of the input capacitor;

FIG. 23 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 21 in the discharging procedure of the input capacitor;

FIG. 24 is a schematic circuit diagram illustrating a driving circuit for a power switch according to an eighth embodiment of the present invention;

FIG. 25 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 24 in the charging procedure of the input capacitor;

FIG. 26 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a ninth embodiment of the present invention;

FIG. 27 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 26 in the charging procedure of the input capacitor;

FIG. 28 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a tenth embodiment of the present invention;

FIG. 29 is a schematic circuit diagram illustrating a driving circuit for a power switch according to an eleventh embodiment of the present invention;

FIG. 30 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a twelfth embodiment of the present invention;

FIG. 31 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 30 in the charging procedure of the input capacitor;

FIG. 32 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 30 in the discharging procedure of the input capacitor;

FIG. 33 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a thirteenth embodiment of the present invention;

FIG. 34 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 33 in the charging procedure of the input capacitor; and

FIG. 35 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 33 in the discharging procedure of the input capacitor.

The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.

The present invention provides a driving circuit for driving a power switch. The driving circuit comprises an inductor, at least one driving switch and a resistor. The inductor, the driving switch and the resistor are electrically connected with each other. Moreover, the driving switch comprises a parasitic parameter.

FIG. 6 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a first embodiment of the present invention. As shown in FIG. 6 , the driving circuit 1 comprises an inductor L 31 , a first driving switch S 31 , a second driving switch S 32 and a resistor R. The capacitor Ciss is an input capacitor of the power switch (not shown). The first terminal of the first driving switch S 31 is electrically connected with an input power source. The second terminal of the first driving switch S 31 is electrically connected with the first terminal of the second driving switch S 32 and the first terminal of the inductor L 31 . The second terminal of the second driving switch S 32 is connected with a ground terminal. The second terminal of the inductor L 31 is electrically connected with the first terminal of the resistor R. The second terminal of the resistor R is electrically connected with the input capacitor Ciss. Moreover, the parasitic parameter of the first driving switch S 31 is a first parasitic capacitor Coss 31 , and the parasitic parameter of the second driving switch S 32 is a second parasitic capacitor Coss 32 .

The operations of charging and discharging the input capacitor Ciss will be described as follows. In this embodiment, the first driving switch S 31 and the second driving switch S 32 are selectively turned on or turned off to control the charging and discharging procedures of the input capacitor Ciss.

FIG. 7 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 6 in the charging procedure of the input capacitor. Firstly, the first driving switch S 31 is turned on in the time interval between t 0 and t 1 . Consequently, the electric energy of the supply voltage Vcc of the input power source charges the inductor L 31 and the input capacitor Ciss through the first driving switch S 31 . At the time point t 1 , the first driving switch S 31 is turned off and the second driving switch S 32 is turned on. Consequently, the input capacitor Ciss is continuously charged by the current of the inductor L 31 until the current of the inductor L 31 is zero (i.e., at the time point t 2 ). Meanwhile, the input capacitor Ciss is charged to the voltage Vp 1 . The voltage Vp 1 must be lower than the supply voltage Vcc. Moreover, at the time point t 2 , the first parasitic capacitor Coss 31 is charged to the supply voltage Vcc, and the second parasitic capacitor Coss 32 is 0V. Consequently, in the time interval between t 2 and t 3 , the first parasitic capacitor Coss 31 and the second parasitic capacitor Coss 32 resonate with the input capacitor Ciss through the inductor L 31 . Due to the resonant oscillation, the voltage of the input capacitor Ciss gradually fluctuates from Vp 1 to a first steady voltage Vo 1 , the voltage of the second parasitic capacitor Coss 32 gradually fluctuates from 0V to the first steady voltage Vo 1 , and the voltage of the first parasitic capacitor Coss 31 gradually fluctuates from Vcc to the voltage (Vcc−Vo 1 ). The input capacitor Ciss is serially connected with the first parasitic capacitor Coss 31 of the first driving switch S 31 and the second parasitic capacitor Coss 32 of the second driving switch S 32 . Consequently, in the time interval between t 2 and t 3 , the amount of charges discharged from the input capacitor Ciss (i.e., from Vp 1 to Vo 1 ) is Q 1 . Moreover, Q 1 is equal to the change amount of charges in the first parasitic capacitor Coss 31 while the voltage is changed from Vcc to (Vcc−Vo 1 ) plus the change amount of charges in the second parasitic capacitor Coss 32 while the voltage is changed from 0V to Vo 1 . For assuring that the on-resistance or the voltage drop of the on-state power switch is very low, the first steady voltage Vo 1 must be higher than a first set voltage VH, wherein the first set voltage VH is higher than the maximum threshold Vmax of the gate terminal of the power switch according to the specifications of the power switch. Consequently, in the time interval between t 2 and t 3 , the change amount of charges of the input capacitor Ciss from Vp 1 to VH is Q 2 . Especially, Q 2 is higher than Q 1 . That is, in the charging procedure of the input capacitor Ciss, the relationships between Q 1 , Q 2 , Coss 31 , Coss 32 , Ciss, Vp 1 , VH and Vo 1 satisfy the following formulae (1), (2) and (3):

Q 1=Coss31 ×Vo 1 +Coss32× Vo 1   (1)

Q 2=Ciss×( Vp 1− VH )   (2)

Q 1≤ Q 2   (3)

As mentioned above, the resonant oscillation occurs in the time interval between t 2 and t 3 . If the resistance of the resistor R is higher, the oscillation circuit is in an overdamping condition. Under this circumstance, the voltage of the input capacitor Ciss does not fluctuate to the level under the first steady voltage Vo 1 (e.g., the solid line of FIG. 7 ). If the resistance of the resistor R is lower, the oscillation circuit is in an underdamping condition. Under this circumstance, the voltage of the input capacitor Ciss fluctuates up and down with respect to the first steady voltage Vo 1 and finally maintained at the first steady voltage Vo 1 (e.g., the dotted line of FIG. 7 ). For avoiding erroneously turning off the on-state power switch, the voltage of the input capacitor Ciss during the resonant oscillation must be higher than the maximum threshold Vmax of the gate terminal of the power switch according to the specifications of the power switch. Consequently, if the resistance of the resistor R is lower and many oscillation cycles are required, the first steady voltage Vo 1 must be higher than 0.5×(Vp 1 +Vmax). Preferably, the resistor R is selected such that the oscillation circuit is in a critical damping condition between the underdamping condition and the overdamping condition.

FIG. 8 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 6 in the discharging procedure of the input capacitor. Firstly, the second driving switch S 32 is turned on in the time interval between t 4 and t 5 . Consequently, the input capacitor Ciss discharges electricity, and the current flowing through the inductor L 31 increases. At the time point t 5 when the current of the inductor L 31 reaches a predetermined value, the second driving switch S 32 is turned off and the first driving switch S 31 is turned on. Consequently, the input capacitor Ciss discharges electricity to the input power source through the inductor L 31 , and the current of the inductor L 31 gradually decreases until the current of the inductor L 31 is zero (i.e., at the time point t 6 ). Meanwhile, the voltage of the input capacitor Ciss is reduced to the voltage Vp 2 . Moreover, at the time point t 6 , the first parasitic capacitor Coss 31 is discharged to 0V, and the second parasitic capacitor Coss 32 is charged to the supply voltage Vcc. Consequently, in the time interval between t 6 and t 7 , the first parasitic capacitor Coss 31 and the second parasitic capacitor Coss 32 resonate with the input capacitor Ciss through the inductor L 31 . Due to the resonant oscillation, the voltage of the input capacitor Ciss gradually fluctuates from Vp 2 to a second steady voltage Vo 2 , the voltage of the second parasitic capacitor Coss 32 gradually fluctuates to the second steady voltage Vo 2 , and the voltage of the first parasitic capacitor Coss 31 gradually fluctuates to the voltage (Vcc−Vo 2 ). The input capacitor Ciss is serially connected with the first parasitic capacitor Coss 31 of the first driving switch S 31 and the second parasitic capacitor Coss 32 of the second driving switch S 32 . Consequently, in the time interval between t 6 and t 7 , the amount of charges charged into the input capacitor Ciss (i.e., from Vp 2 to Vo 2 ) is Q 3 . Moreover, Q 3 is equal to the change amount of charges in the first parasitic capacitor Coss 31 while the voltage is changed from 0V to (Vcc−Vo 2 ) plus the change amount of charges in the second parasitic capacitor Coss 32 while the voltage is changed from Vcc to Vo 2 . For assuring that the on-resistance of the on-state power switch is high or the leakage current is low, the second steady voltage Vo 2 must be lower than a second set voltage VL, wherein the second set voltage VL is lower than the minimum threshold Vmin of the gate terminal of the power switch according to the specifications of the power switch. Consequently, in the time interval between t 6 and t 7 , the change amount of charges of the input capacitor Ciss from Vp 2 to VL is equal to Q 4 . Especially, Q 4 is higher than or equal to Q 3 . That is, in the discharging procedure of the input capacitor Ciss, the relationships between Q 3 , Q 4 , Coss 31 , Coss 32 , Ciss, Vp 2 , VL, Vcc and Vo 2 satisfy the following formulae (4), (5) and (6):

Q 3=(Coss31+Coss32)×( Vcc−Vo 2 )   (4)

Q 4=Ciss×( Vp 2− VL )   (5)

Q 3≤ Q 4   (6)

Preferably, the voltage Vp 2 is 0V. If the on duration of the first driving switch S 31 is too long, the input capacitor Ciss is inversely charged. Under this circumstance, the voltage Vp 2 is lower than 0V, the oscillation extent of the voltage of the input capacitor Ciss is too large, and the energy loss increases. As mentioned above, the resonant oscillation occurs in the time interval between t 6 and t 7 . If the resistance of the resistor R is higher, the oscillation circuit is in an overdamping condition. Under this circumstance, the voltage of the input capacitor Ciss does not fluctuate to the level over the second steady voltage Vo 2 (e.g., the solid line of FIG. 8 ). If the resistance of the resistor R is lower, the oscillation circuit is in an underdamping condition. Under this circumstance, the voltage of the input capacitor Ciss fluctuates up and down with respect to the second steady voltage Vo 2 and finally maintained at the second steady voltage Vo 2 (e.g., the dotted line of FIG. 8 ). For avoiding erroneously turning on the off-state power switch, the voltage of the input capacitor Ciss during the resonant oscillation must be lower than the minimum threshold Vmin. Consequently, if the resistance of the resistor R is lower and many oscillation cycles are required, the second steady voltage Vo 2 must be lower than 0.5×(Vp 2 +Vmin). Preferably, the resistor R is selected such that the oscillation circuit is in a critical damping condition between the underdamping condition and the overdamping condition.

As mentioned above, specified mathematic formulae are satisfied in the charging procedure and discharging procedure of the input capacitor Ciss of the driving circuit 1 and the inductor L 31 of the driving circuit 1 may not need to provide the constant current. Under this circumstance, smaller inductance of the inductor L 31 is required, and thus the volume of the inductor L 31 is reduced. Moreover, the energy loss of the driving circuit 1 may be reduced when compared with the conventional driving circuit. In an embodiment, the inductor L 31 is a physical inductor. In some other embodiments, the inductor L 31 is a parasitic inductor that is formed in a wire between the driving switch and the input capacitor Ciss.

FIG. 9 is a schematic circuit diagram illustrating the equivalent circuit of the driving circuit of FIG. 6 . As shown in FIG. 9 , the equivalent circuit 2 comprises a first equivalent capacitor Ci, an equivalent inductor L, an equivalent resistor R 1 and a second equivalent capacitor Coss. The first equivalent capacitor Ci is related to the input capacitor Ciss of the power switch. The equivalent inductor L comprises the inductor L 31 . The equivalent resistor R 1 comprises the resistor R. Moreover, the equivalent resistor R 1 is connected with the first equivalent capacitor Ci in series. The second equivalent capacitor Coss is related to the parasitic parameter of at least one driving switch. For example, the parasitic parameter of at least one driving switch comprises the first parasitic capacitor Coss 31 of the first driving switch S 31 and the second parasitic capacitor Coss 32 of the second driving switch S 32 . That is, the second equivalent capacitor Coss is related to the first parasitic capacitor Coss 31 of the first driving switch S 31 and the second parasitic capacitor Coss 32 of the second driving switch S 32 . Moreover, the first equivalent capacitor Ci, the equivalent inductor L, the equivalent resistor R 1 and the second equivalent capacitor Coss 32 are serially connected with each other to define a charge/discharge loop (i.e., the equivalent circuit 2 ). The charging operation or the discharging operation of the first equivalent capacitor Ci is performed by the charge/discharge loop.

Please refer to the equivalent circuit 2 and the charging procedure of the driving circuit 1 . In the charging procedure of the first equivalent capacitor Ci, the voltage of the input capacitor Ciss is changed from the voltage Vp 1 (i.e., no current flowing through the inductor or no inductor current) to the first set voltage VH. The change amount of charges in the first equivalent capacitor Ci is equal to Q 2 . While the voltage of the input capacitor Ciss is changed from Vp 1 to Vo 1 , the change amount of charges in the second equivalent capacitor Coss is Q 1 . Especially, Q 2 is higher than or equal to Q 1 . Please refer to the equivalent circuit 2 and the discharging procedure of the driving circuit 1 . In the discharging procedure of the first equivalent capacitor Ci, the voltage of the input capacitor Ciss is changed from the voltage Vp 2 (i.e., no current flowing through the inductor or no inductor current) to the second set voltage VL. The change amount of charges in the first equivalent capacitor Ci is equal to Q 4 . While the voltage of the input capacitor Ciss is changed from Vp 2 to Vo 2 , the change amount of charges in the second equivalent capacitor Coss is Q 3 . Especially, Q 4 is higher than or equal to Q 3 .

FIG. 10 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a second embodiment of the present invention. Component parts and elements corresponding to those of the first embodiment are designated by identical numeral references, and detailed descriptions thereof are omitted. In comparison with the driving circuit 1 of FIG. 6 , the driving circuit 1 A of the present invention further comprises a third driving switch S 33 . The third driving switch S 33 has a third parasitic capacitor Coss 33 . The first terminal of the third driving switch S 33 is electrically connected with the second terminal of the inductor L 31 and the first terminal of the resistor R. The second terminal of the third driving switch S 33 is electrically connected with a ground terminal. The driving circuit 1 A is substantially equivalent to the equivalent circuit 2 of FIG. 9 . However, the first equivalent capacitor Ci of this embodiment is related to the input capacitor Ciss of the power switch and the third parasitic capacitor Coss 33 of the third driving switch S 33 .

FIG. 11 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 10 in the charging procedure of the input capacitor. Please refer to FIGS. 9, 10 and 11 . In this embodiment, the first driving switch S 31 and the second driving switch S 32 are selectively turned on or turned off to control the charging procedure of the input capacitor Ciss. However, the discharging procedure of the input capacitor Ciss is controlled when the third driving switch S 33 is turned on. That is, after the voltage of the input capacitor Ciss reaches the first steady voltage Vo 1 for a specified time period (e.g., at the time point t 3 ′), the third driving switch S 33 is turned on. Since the voltage of the input capacitor Ciss reduces to zero, the speed of turning off the power switch (not shown) is increased. As mentioned above, the first equivalent capacitor Ci is related to the input capacitor Ciss of the power switch and the third parasitic capacitor Coss 33 of the third driving switch S 33 . Consequently, in the charging procedure of the first equivalent capacitor Ci, the relationships between Q 1 , Q 2 , Coss 31 , Coss 32 , Coss 33 , Ciss, Vp 1 , VH and Vo 1 satisfy the following formulae (7), (8) and (9):

Q 1=(Coss31+Coss32)× Vo 1   (7)

Q 2=(Ciss+Coss33)×( Vp 1− VH )   (8)

Q 1 ≤Q 2   (9)

FIG. 12 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a third embodiment of the present invention. Component parts and elements corresponding to those of the first embodiment are designated by identical numeral references, and detailed descriptions thereof are omitted. In comparison with the driving circuit 1 of FIG. 6 , the driving circuit 1 B of the present invention further comprises a first clamping circuit C 35 and a second clamping circuit C 34 . The first clamping circuit C 35 comprises a third parasitic capacitor Coss 35 . The second clamping circuit C 34 comprises a fourth parasitic capacitor Coss 34 . The first terminal of the first clamping circuit C 35 is connected with the first terminal of the first driving switch S 31 and the input power source. The second terminal of the first clamping circuit C 35 is connected with the second terminal of the inductor L 31 , the first terminal of the second clamping circuit C 34 and the first terminal of the resistor R. The second terminal of the second clamping circuit C 34 is connected with the ground terminal. The driving circuit 1 B is substantially equivalent to the equivalent circuit 2 of FIG. 9 . However, the first equivalent capacitor Ci of this embodiment is related to the input capacitor Ciss of the power switch, the third parasitic capacitor Coss 35 of the first clamping circuit C 35 and the fourth parasitic capacitor Coss 34 of the second clamping circuit C 34 .

FIG. 13 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 12 in the charging procedure and the discharging procedure of the input capacitor. Please refer to FIGS. 9, 12 and 13 . The charging and discharging procedures of this embodiment are distinguished from those of the first embodiment. When the voltage of the input capacitor Ciss is charged to the voltage exceeding an over-voltage value in the time interval between t 1 ′ and t 2 , the voltage of the input capacitor Ciss is clamped to the over-voltage value by the first clamping circuit C 35 . In this embodiment, the over-voltage value is the supply voltage Vcc. In other words, the voltage Vp 1 is very close to the supply voltage Vcc in the charging procedure of the input capacitor Ciss. When the voltage of the input capacitor Ciss is discharged to the voltage below an under-voltage value in the time interval between t 5 ′ and t 6 , the voltage of the input capacitor Ciss is clamped to the under-voltage value by the second clamping circuit C 34 . In this embodiment, the under-voltage value is the 0V. In other words, the voltage Vp 2 is very close to 0V in the discharging procedure of the input capacitor Ciss.

Consequently, in the charging procedure of the input capacitor Ciss, it is not necessary to precisely control the voltage of the input capacitor Ciss in the on period of the second driving switch S 32 (i.e., from t 1 to t 2 ). Moreover, in the discharging procedure of the input capacitor Ciss, it is not necessary to precisely control the voltage of the input capacitor Ciss in the on period of the first driving switch S 31 (i.e., from t 5 to t 6 ). In this embodiment, the first equivalent capacitor Ci is related to the input capacitor Ciss of the power switch, the third parasitic capacitor Coss 35 of the first clamping circuit C 35 and the fourth parasitic capacitor Coss 34 of the second clamping circuit C 34 . Consequently, in the charging procedure of the first equivalent capacitor Ci, the relationships between Q 1 , Q 2 , Coss 31 , Coss 32 , Coss 34 , Coss 35 , Ciss, Vp 1 , VH and Vo 1 satisfy the following formulae (10), (11) and (12):

Q 1=(Coss31+Coss32)× Vo 1   (10)

Q 2=(Ciss+Coss34+Coss35)×( Vp 1− VH )   (11)

Q 1 ≤Q 2   (12)

In the discharging procedure of the first equivalent capacitor Ci, the relationships between Q 3 , Q 4 , Coss 31 , Coss 32 , Coss 34 , Coss 35 , Ciss, Vp 2 , VL, Vcc and Vo 2 satisfy the following formulae (13), (14) and (15):

Q 3=(Coss31+Coss32)×( Vcc−Vo 2 )   (13)

Q 4=(Ciss+Coss34+Coss35)×( Vp 2− VL )   (14)

Q 3 ≤Q 4   (15)

FIG. 14 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a fourth embodiment of the present invention. Component parts and elements corresponding to those of the first embodiment are designated by identical numeral references, and detailed descriptions thereof are omitted. In comparison with the driving circuit 1 of FIG. 6 , the driving circuit 1 C of the present invention further comprises a first clamping circuit C 35 and a third driving switch C 33 . The first clamping circuit C 35 comprises a third parasitic capacitor Coss 35 . The third driving switch C 33 comprises a fourth parasitic capacitor Coss 33 . The first terminal of the first clamping circuit C 35 is connected with the first terminal of the first driving switch S 31 and the input power source. The second terminal of the first clamping circuit C 35 is connected with the second terminal of the inductor L 31 , the first terminal of the third driving switch C 33 and the first terminal of the resistor R. The second terminal of the third driving switch C 33 is connected with the ground terminal.

The driving circuit 1 C is substantially equivalent to the equivalent circuit 2 of FIG. 9 . However, the first equivalent capacitor Ci of this embodiment is related to the input capacitor Ciss of the power switch, the third parasitic capacitor Coss 35 of the first clamping circuit C 35 and the fourth parasitic capacitor Coss 33 of the third driving switch C 33 .

FIG. 15 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 14 in the charging procedure of the input capacitor. Please refer to FIGS. 9, 14 and 15 . The charging and discharging procedures of this embodiment are distinguished from those of the first embodiment. When the voltage of the input capacitor Ciss is charged to the voltage exceeding an over-voltage value in the time interval between t 1 ′ and t 2 , the voltage of the input capacitor Ciss is clamped to the over-voltage value by the first clamping circuit C 35 . In this embodiment, the over-voltage value is the supply voltage Vcc. In other words, the voltage Vp 1 is very close to the supply voltage Vcc in the charging procedure of the input capacitor Ciss. After the voltage of the input capacitor Ciss reaches the first steady voltage Vo 1 for a specified time period (e.g., at the time point t 3 ′), the third driving switch S 33 is turned on. Since the voltage of the input capacitor Ciss reduces to zero, the speed of turning off the power switch (not shown) is increased. As mentioned above, the first equivalent capacitor Ci is related to the input capacitor Ciss of the power switch, the third parasitic capacitor Coss 35 of the first clamping circuit C 35 and the fourth parasitic capacitor Coss 33 of the third driving switch C 33 . Consequently, in the charging procedure of the first equivalent capacitor Ci, the relationships between Q 1 , Q 2 , Coss 31 , Coss 32 , Coss 33 , Coss 35 , Ciss, Vp 1 , VH and Vo 1 satisfy the following formulae (16), (17) and (18):

Q 1=(Coss31+Coss32)× Vo 1   (16)

Q 2=(Ciss+Coss33+Coss35)×( Vp 1− VH )   (17)

Q 1≤ Q 2   (18)

FIG. 16 is another schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 14 in the charging procedure of the input capacitor. The charging procedure of FIG. 16 is distinguished from the charging procedure of FIG. 15 . For charging the input capacitor Ciss, the first driving switch S 31 and the third driving switch S 33 are turned on in the time interval between t 0 and t 1 . Consequently, the electric energy from the input power source charges the inductor L 31 and the input capacitor Ciss through the first driving switch S 31 , the inductor L 31 and the third driving switch S 33 until the current flowing the inductor L 31 reaches a predetermined value. At the time point t 1 , the first driving switch S 31 and the third driving switch S 33 are turned off and the second driving switch S 32 is turned on. Consequently, the input capacitor Ciss is continuously charged by the current of the inductor L 31 . Since the current of the inductor L 31 has been previously charged to the predetermined value, a larger charging current provides to the input capacitor Ciss. In other words, the input capacitor Ciss is charged at a faster speed. The charging procedure in the interval between t 1 and t 3 is similar to that of the first embodiment, and is not redundantly described herein.

FIG. 17 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a fifth embodiment of the present invention. Component parts and elements corresponding to those of the driving circuit of FIG. 14 are designated by identical numeral references, and detailed descriptions thereof are omitted. In comparison with the driving circuit 1 C of FIG. 14 , the driving circuit 1 D of this embodiment further comprises a DC clamping power source Vclamp. Moreover, the first terminal of the first clamping circuit C 35 is electrically connected with the DC clamping power source Vclamp.

FIG. 18 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 17 in the charging procedure of the input capacitor. When the voltage of the input capacitor Ciss is charged to the voltage exceeding an over-voltage value in the time interval between t 1 ′ and t 2 , the voltage of the input capacitor Ciss is clamped to the over-voltage value by the DC clamping power source Vclamp. In this embodiment, the over-voltage value is the supply voltage of the DC clamping power source Vclamp. In other words, the voltage of the input capacitor Ciss is very close to the supply voltage of the DC clamping power source Vclamp in the charging procedure of the input capacitor Ciss.

FIG. 19 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a sixth embodiment of the present invention. Component parts and elements corresponding to those of the driving circuit of FIG. 17 are designated by identical numeral references, and detailed descriptions thereof are omitted. In comparison with the driving circuit 1 D of FIG. 17 , the driving circuit 1 E of this embodiment further comprises a fourth driving switch S 35 in replace of the first clamping circuit C 35 .

FIG. 20 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 19 in the discharging procedure of the input capacitor. For discharging the input capacitor Ciss, the second driving switch S 32 and the fourth driving switch S 35 are turned on in the time interval between t 0 and t 1 . Consequently, the electric energy of the DC clamping power source Vclamp charges the inductor L 31 through the fourth driving switch S 35 , the inductor L 31 and the second driving switch S 32 until the current flowing through the inductor L 31 reaches a predetermined value. At the time point t 1 when the current of the inductor L 31 reaches the predetermined value, the second driving switch S 32 and the fourth driving switch S 35 are turned off, and the first driving switch S 31 is turned on. Since the current of the inductor L 31 has been previously charged to the predetermined value, the input capacitor Ciss is discharged at a faster speed. At the time point t 1 ′ when the voltage of the input capacitor Ciss is discharged to 0V, the third driving switch is turned on. Consequently, the voltage of the input capacitor Ciss is clamped to 0V.

FIG. 21 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a seventh embodiment of the present invention. As shown in FIG. 21 , the driving circuit 2 A comprises an inductor L 41 , a first driving switch S 41 , a second driving switch S 42 and a resistor R. The capacitor Ciss is an input capacitor of the power switch (not shown). The first terminal of the inductor L 41 is electrically connected with an input power source. The second terminal of the inductor L 41 is electrically connected with the first terminal of the first driving switch S 41 and the first terminal of the second driving switch S 42 . The second terminal of the second driving switch S 42 is electrically connected with the first terminal of the resistor R. The second terminal of the resistor R is electrically connected with the input capacitor Ciss. The second terminal of the first driving switch S 41 is electrically connected with a ground terminal. Moreover, the parasitic parameter of the first driving switch S 41 is a first parasitic capacitor Coss 41 , and the parasitic parameter of the second driving switch S 42 is a second parasitic capacitor Coss 42 .

The operations of charging and discharging the input capacitor Ciss will be described as follows. In this embodiment, the first driving switch S 41 and the second driving switch S 42 are selectively turned on or turned off to control the charging and discharging procedures of the input capacitor Ciss.

FIG. 22 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 21 in the charging procedure of the input capacitor. For charging the input capacitor Ciss, the first driving switch S 41 is turned on in the time interval between t 0 and t 1 . Consequently, the electric energy of the supply voltage Vcc of the input power source charges the inductor L 41 through the first driving switch S 41 . At the time point t 1 , the first driving switch S 41 is turned off and the second driving switch S 42 is turned on. Consequently, the input capacitor Ciss is charged by the current of the inductor L 41 until the current of the inductor L 41 is zero (i.e., at the time point t 2 ). Meanwhile, the input capacitor Ciss is charged to the voltage Vp 1 . The first steady voltage Vo 1 is higher than or equal to the supply voltage Vcc of the input power source. Moreover, at the time point t 2 , the first parasitic capacitor Coss 41 is charged to the voltage Vp 1 , and the second parasitic capacitor Coss 42 is 0V. Consequently, in the time interval between t 2 and t 3 , the second parasitic capacitor Coss 42 resonates with the input capacitor Ciss through the inductor L 41 . Due to the resonant oscillation, the voltage of the input capacitor Ciss gradually fluctuates from Vp 1 to a first steady voltage Vo 1 , the voltage of the second parasitic capacitor Coss 42 gradually fluctuates from 0V to the voltage (Vo 1 -Vcc), and the voltage of the first parasitic capacitor Coss 41 is equal to the supply voltage Vcc. The input capacitor Ciss is serially connected with the second parasitic capacitor Coss 42 of the second driving switch S 42 . Consequently, in the time interval between t 2 and t 3 , the amount of charges discharged from the input capacitor Ciss (i.e., from Vp 1 to Vo 1 ) is Q 1 . Moreover, Q 1 is equal to the change amount of charges in the second parasitic capacitor Coss 42 while the voltage is changed from 0V to the voltage (Vo 1 -Vcc). When the voltage of the input capacitor Ciss reaches the first steady voltage Vo 1 , the first steady voltage Vo 1 must be higher than the first set voltage VH. Consequently, in the time interval between t 2 and t 3 , the change amount of charges of the input capacitor Ciss from Vp 1 to VH is equal to Q 2 . Especially, Q 2 is higher than or equal to Q 1 . That is, in the charging procedure of the input capacitor Ciss, the relationships between Q 1 , Q 2 , Coss 42 , Ciss, Vp 1 , VH and Vol satisfy the following formulae (19), (20) and (21):

Q 1=Coss42×( Vo 1 −Vcc )   (19)

Q 2=Ciss×( Vp 1− VH )   (20)

Q 1≤ Q 2   (21)

FIG. 23 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 21 in the discharging procedure of the input capacitor. For discharging the input capacitor Ciss, the second driving switch S 42 is turned on in the time interval between t 4 and t 5 . Consequently, the input capacitor Ciss discharges electricity, and the current flowing through the inductor L 41 increases. At the time point t 5 when the current of the inductor L 41 reaches a predetermined value, the second driving switch S 42 is turned off and the first driving switch S 41 is turned on. Consequently, the input inductor L 41 discharges electricity to the input power source, and the current of the inductor L 41 gradually decreases until the current of the inductor L 41 is zero (i.e., at the time point t 6 ). Meanwhile, the voltage of the input capacitor Ciss is reduced to the voltage Vp 2 . Moreover, at the time point t 6 , the first parasitic capacitor Coss 41 is discharged to 0V, and the second parasitic capacitor Coss 42 is charged to Vp 2 . Consequently, in the time interval between second parasitic capacitor Coss 42 resonates with the input capacitor Ciss through the inductor L 41 . Due to the resonant oscillation, the voltage of the input capacitor Ciss gradually fluctuates from Vp 2 to a second steady voltage Vo 2 , the voltage of the second parasitic capacitor Coss 42 gradually fluctuates to (Vcc-Vo 2 ), and the voltage of the first parasitic capacitor Coss 41 gradually fluctuates to Vcc. The input capacitor Ciss is serially connected with the second parasitic capacitor Coss 42 of the second driving switch S 42 . Consequently, in the time interval between t 6 and t 7 , the amount of charges charged into the input capacitor Ciss (i.e., from Vp 2 to Vo 2 ) is Q 3 . Moreover, Q 3 is equal to the change amount of charges in the second parasitic capacitor Coss 42 while the voltage is changed from Vp 2 to (Vcc-Vo 2 ). When the voltage of the input capacitor Ciss reaches the second steady voltage Vo 2 , the second steady voltage Vo 2 must be lower than the second set voltage VL. Consequently, in the time interval between t 6 and t 7 , the change amount of charges of the input capacitor Ciss from Vp 2 to VL is equal to Q 4 . Especially, Q 4 is higher than or equal to Q 3 . That is, in the discharging procedure of the input capacitor Ciss, the relationships between Q 3 , Q 4 , Coss 42 , Ciss, Vp 2 , VL, Vcc and Vol satisfy the following formulae (22), (23) and (24):

Q 3=Coss42×( Vp 2+ Vcc−Vo 2 )   (22)

Q 4=Ciss×( Vp 2− VL )   (23)

Q 3≤ Q 4   (24)

In the above embodiment, the first driving switch S 41 may be a MOSFET with a parallel-connected body diode and the second driving switch S 42 may be a bidirectional switch. Preferably, the voltage Vp 2 is 0V. If the on duration of the second driving switch S 42 is too long, the body diode of the first driving switch S 41 is turned on or the input capacitor Ciss is inversely charged. Under this circumstance, the voltage Vp 2 is lower than 0V, the oscillation extent of the voltage of the input capacitor Ciss is too large, and the energy loss increases.

The driving circuit 2 A is substantially equivalent to the equivalent circuit 2 of FIG. 9 . However, the first equivalent capacitor Ci of this embodiment is related to the input capacitor Ciss of the power switch, the equivalent inductor L comprises the inductor L 41 , and the second equivalent capacitor Coss is related to the second parasitic capacitor Coss 42 of the second driving switch S 42 .

FIG. 24 is a schematic circuit diagram illustrating a driving circuit for a power switch according to an eighth embodiment of the present invention. Component parts and elements corresponding to those of the driving circuit of FIG. 21 are designated by identical numeral references, and detailed descriptions thereof are omitted. In comparison with the driving circuit 2 A of FIG. 21 , the driving circuit 2 B of this embodiment further comprises a third driving switch S 43 and a DC clamping power source Vclamp. The third driving switch S 43 has a third parasitic capacitor Coss 43 . The first terminal of the third driving switch S 43 is electrically connected with the second terminal of the second driving switch S 42 and the first terminal of the resistor R. The DC clamping power source Vclamp is connected between the second terminal of the third driving switch S 43 and the ground terminal.

The driving circuit 2 B is substantially equivalent to the equivalent circuit 2 of FIG. 9 . However, the first equivalent capacitor Ci of this embodiment is related to the input capacitor Ciss of the power switch and the third parasitic capacitor Coss 43 of the third driving switch S 43 .

FIG. 25 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 24 in the charging procedure of the input capacitor. Please refer to FIGS. 9, 24 and 25 . In the charging procedure, the third driving switch S 43 is turned on in the time interval between t 0 and t 1 . Consequently, the DC clamping power source Vclamp releases electric energy to charge the input capacitor Ciss. Consequently, the input capacitor Ciss is charged at a faster speed. The discharging procedure is similar to that of the seventh embodiment, and is not redundantly described herein. As mentioned above, the first equivalent capacitor Ci of this embodiment is related to the input capacitor Ciss of the power switch and the third parasitic capacitor Coss 43 of the third driving switch S 43 . Consequently, the discharging procedure of the first equivalent capacitor Ci, the relationships between Q 3 , Q 4 , Coss 42 , Coss 43 , Ciss, Vp 2 , VL, Vcc and Vo 2 satisfy the following formulae (25), (26) and (27):

Q 3=Coss42×( Vp 2+ Vcc−Vo 2 )   (25)

Q 4=(Ciss+Coss43)×( Vp 2− VL )   (26)

Q 3≤ Q 4   (27)

FIG. 26 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a ninth embodiment of the present invention. Component parts and elements corresponding to those of the driving circuit of FIG. 21 are designated by identical numeral references, and detailed descriptions thereof are omitted. In comparison with the driving circuit 2 A of FIG. 21 , the driving circuit 2 C of this embodiment further comprises a first clamping circuit C 43 and a DC clamping power source Vclamp. The first clamping circuit C 43 has a third parasitic capacitor Coss 43 . The first terminal of the first clamping circuit C 43 is electrically connected with the second terminal of the second driving switch S 42 and the first terminal of the resistor R. The DC clamping power source Vclamp is connected between the second terminal of the first clamping circuit C 43 and the ground terminal.

The driving circuit 2 C is substantially equivalent to the equivalent circuit 2 of FIG. 9 . However, the first equivalent capacitor Ci of this embodiment is related to the input capacitor Ciss of the power switch and the third parasitic capacitor Coss 43 of the first clamping circuit C 43 .

FIG. 27 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 26 in the charging procedure of the input capacitor. Please refer to FIGS. 9, 26 and 27 . The charging procedure of this embodiment is distinguished from that of the seventh embodiment. When the voltage of the input capacitor Ciss is charged to the voltage exceeding the voltage of the DC clamping power source Vclamp in the time interval between t 1 ′ and t 2 , the voltage of the input capacitor Ciss is clamped to the voltage of the DC clamping power source Vclamp by the first clamping circuit C 43 . Since the voltage of the input capacitor Ciss is not too high, the power switch is not damaged and the ease of controlling the second driving switch S 42 in the charging procedure is enhanced. As mentioned above, the first equivalent capacitor Ci is related to the input capacitor Ciss of the power switch and the third parasitic capacitor Coss 43 of the first clamping circuit C 43 . Consequently, in the charging procedure of the first equivalent capacitor Ci, the relationships between Q 1 , Q 2 , Coss 42 , Coss 43 , Ciss, Vclamp, Vcc, VH and Vo 1 satisfy the following formulae (28), (29) and (30):

Q 1=Coss42×( Vo 1 −Vcc )   (28)

Q 2=(Ciss+Coss43)×(Vclamp− VH )   (29)

Q 1≤ Q 2   (30)

FIG. 28 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a tenth embodiment of the present invention. Component parts and elements corresponding to those of the driving circuit of FIG. 21 are designated by identical numeral references, and detailed descriptions thereof are omitted. In comparison with the driving circuit 2 A of FIG. 21 , the driving circuit 2 D of this embodiment further comprises a third driving switch S 43 . The third driving switch S 43 has a third parasitic capacitor Coss 43 . The first terminal of the third driving switch S 43 is electrically connected with the second terminal of the second driving switch S 42 and the first terminal of the resistor R. The second terminal of the third driving switch S 43 is electrically connected with the ground terminal. The third driving switch S 43 is turned on to control the discharging procedure of the input capacitor Ciss. Consequently, the input capacitor Ciss is discharged at a faster speed.

The driving circuit 2 D is substantially equivalent to the equivalent circuit 2 of FIG. 9 . However, the first equivalent capacitor Ci of this embodiment is related to the input capacitor Ciss of the power switch and the third parasitic capacitor Coss 43 of the third driving switch S 43 .

FIG. 29 is a schematic circuit diagram illustrating a driving circuit for a power switch according to an eleventh embodiment of the present invention. Component parts and elements corresponding to those of the driving circuit of FIG. 26 are designated by identical numeral references, and detailed descriptions thereof are omitted. In comparison with the driving circuit 2 C of FIG. 26 , the driving circuit 2 E of this embodiment further comprises a third driving switch S 43 . The third driving switch S 43 has a fourth parasitic capacitor Coss 44 . The first terminal of the third driving switch S 43 is electrically connected with the first terminal of the first clamping circuit C 43 , the second terminal of the second driving switch S 42 and the first terminal of the resistor R. The second terminal of the third driving switch S 43 is electrically connected with the ground terminal. In comparison with the driving circuit 2 C of FIG. 26 , the voltage of the input capacitor Ciss is not too high by the driving circuit 2 E. Consequently, the possibility of causing damage of the power switch is reduced. The third driving switch S 43 is turned on to control the discharging procedure of the input capacitor Ciss. Consequently, the input capacitor Ciss is discharged at a faster speed.

The driving circuit 2 E is substantially equivalent to the equivalent circuit 2 of FIG. 9 . However, the first equivalent capacitor Ci of this embodiment is related to the input capacitor Ciss of the power switch, the third parasitic capacitor Coss 43 of the first clamping circuit C 43 and the fourth parasitic capacitor Coss 44 of the third driving switch S 43 .

As mentioned above, the first equivalent capacitor Ci is related to the input capacitor Ciss of the power switch, the third parasitic capacitor Coss 43 of the first clamping circuit C 43 and the fourth parasitic capacitor Coss 44 of the third driving switch S 43 . Consequently, in the charging procedure of the first equivalent capacitor Ci, the relationships between Q 1 , Q 2 , Coss 42 , Coss 43 , Coss 44 , Ciss, Vclamp, Vcc, VH and Vo 1 satisfy the following formulae (28), (29) and (30):

Q 1=Coss42×( Vo 1 −Vcc )   (31)

Q 2=(Ciss+Coss43+Coss44)×(Vclamp− VH )   (32)

Q 1≤ Q 2   (33)

FIG. 30 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a twelfth embodiment of the present invention. As shown in FIG. 30 , the driving circuit 3 A comprises an inductor L 51 , a first driving switch S 51 , a second driving switch S 52 , a third driving switch S 53 , a fourth driving switch S 54 and a resistor R. The capacitor Ciss is an input capacitor of the power switch (not shown). The first terminal of the first driving switch S 51 is electrically connected with an input power source. The second terminal of the first driving switch S 51 is electrically connected with the first terminal of the second driving switch S 52 and the first terminal of the inductor L 51 . The second terminal of the second driving switch S 52 is connected with a ground terminal. The first terminal of the fourth driving switch S 54 is electrically connected with the first terminal of the resistor R. The second terminal of the fourth driving switch S 54 is electrically connected with the second terminal of the inductor L 51 and the first terminal of the third driving switch S 53 . The second terminal of the third driving switch S 53 is connected with the ground terminal. The second terminal of the resistor R is electrically connected with the input capacitor Ciss. Moreover, the parasitic parameter of the first driving switch S 51 is a first parasitic capacitor Coss 51 , the parasitic parameter of the second driving switch S 52 is a second parasitic capacitor Coss 52 , the parasitic parameter of the third driving switch S 53 is a third parasitic capacitor Coss 53 , and the parasitic parameter of the fourth driving switch S 54 is a fourth parasitic capacitor Coss 54 .

The operations of charging and discharging the input capacitor Ciss will be described as follows. In this embodiment, the first driving switch S 51 , the second driving switch S 52 , the third driving switch S 53 and the fourth driving switch S 54 are selectively turned on or turned off to control the charging and discharging procedures of the input capacitor Ciss.

FIG. 31 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 30 in the charging procedure of the input capacitor. In the time interval between t 0 and t 1 , the first driving switch S 51 and the third driving switch S 53 are turned on. Consequently, the electric energy of the supply voltage Vcc of the input power source charges the inductor L 51 through the first driving switch S 51 and the third driving switch S 53 . At the time point t 1 , the first driving switch S 51 and the third driving switch S 53 are turned off, and the second driving switch S 52 and the fourth driving switch S 54 are turned on. Consequently, the input capacitor Ciss is charged by the current of the inductor L 51 until the current of the inductor L 51 is zero (i.e., at the time point t 2 ). Meanwhile, the input capacitor Ciss is charged to the voltage Vp 1 . At the time point t 2 , the voltages of the first parasitic capacitor Coss 51 and the third parasitic capacitor Coss 53 are 0V, the voltage of the second parasitic capacitor Coss 52 is Vcc, and the voltage of the fourth parasitic capacitor Coss 54 is Vp 1 . Consequently, in the time interval between t 2 and t 3 , the first parasitic capacitor Coss 51 and the second parasitic capacitor Coss 52 resonate with the input capacitor Ciss, the third parasitic capacitor Coss 53 and the fourth parasitic capacitor Coss 54 through the inductor L 51 . Due to the resonant oscillation, the voltage of the input capacitor Ciss gradually fluctuates from Vp 1 to a first steady voltage Vo 1 , the voltage of the second parasitic capacitor Coss 52 gradually fluctuates to the voltage of the third parasitic capacitor Coss 53 . The input capacitor Ciss is connected in series with the fourth parasitic capacitor Coss 54 of the fourth driving switch S 54 , and then connected in parallel with the third parasitic capacitor Coss 53 of the third driving switch S 53 , and then connected in series with the first parasitic capacitor Coss 51 of the first driving switch S 51 and the second parasitic capacitor Coss 52 of the second driving switch S 52 . Consequently, in the time interval between t 2 and t 3 , the amount of charges discharged from the input capacitor Ciss (i.e., from Vp 1 to Vo 1 ) plus the amount of charges discharged from the third parasitic capacitor Coss 53 (i.e., in response to the voltage change) is Q 1 . Moreover, Q 1 is equal to the change amount of charges in the first parasitic capacitor Coss 51 while the voltage is changed from Vcc to the first steady voltage Vo 1 plus the change amount of charges in the second parasitic capacitor Coss 52 while the voltage is changed from 0V to first steady voltage Vo 1 . When the voltage of the input capacitor Ciss reaches the first steady voltage Vo 1 , the first steady voltage Vo 1 must be higher than the first set voltage VH. Consequently, in the time interval between t 2 and t 3 , the change amount of charges of the input capacitor Ciss from Vp 1 to VH plus the change amount of charges of the third parasitic capacitor Coss 53 is equal to Q 2 . Especially, Q 2 is higher than or equal to Q 1 . That is, in the charging procedure of the input capacitor Ciss, the relationships between Q 1 , Q 2 , Coss 51 , Coss 52 , Coss 53 , Coss 54 , Ciss, Vp 1 , VH and Vo 1 satisfy the following formulae (34), (35) and (36):

Q 1=(Coss51+Coss52)×[ VH −( Vp 1− Vo 1 )×(Ciss/Coss54)]  (34)

Q 2=(Coss53+Coss54)×( Vp 1− VH )×(Ciss/Coss54)+Coss53×( Vp 1− VH )   (35)

Q 1≤ Q 2   (36)

In case that the first driving switch S 51 , the second driving switch S 52 , the third driving switch S 53 and the fourth driving switch S 54 are MOSFET with body diodes, the precision of controlling the second driving switch S 52 and the fourth driving switch S 54 may be reduced. After the charging procedure of the input capacitor Ciss is completed, the voltages of the second parasitic capacitor Coss 52 and the third parasitic capacitor Coss 53 in the steady state are lower than Vcc. In other words, Vo 1 −(Vp 1 −Vo 1 )×(Ciss/Coss 54 )<Vcc. In the charging procedure of the input capacitor Ciss, the relationships between Q 1 , Q 2 , Coss 51 , Coss 52 , Coss 53 , Coss 54 , Ciss, Vp 1 , VH and Vo 1 satisfy the following formulae (37), (38) and (39):

Q 1=(Coss51+Coss52)×[ Vo 1 −( Vp 1 −Vo 1 )×(Ciss/Coss54)]  (37)

Q 2=(Coss53+Coss54)×( Vp 1× VH )×(Ciss/Coss54)+Coss53×( Vp 1− VH )   (38)

Q 1≤ Q 2   (39)

After the charging procedure of the input capacitor Ciss is completed, if the voltages of the second parasitic capacitor Coss 52 and the third parasitic capacitor Coss 53 in the steady state are clamped to Vcc by the body diode of the first driving switch S 51 , the relationships between Q 1 , Q 2 , Coss 54 , Ciss, Vp 1 and VH satisfy the following formulae (40), (41) and (42):

Q 1=Coss54×( VH−Vcc )   (40)

Q 2=Ciss×( Vp 1− VH )   (41)

Q 1≤ Q 2   (42)

FIG. 32 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 30 in the discharging procedure of the input capacitor. Firstly, the second driving switch S 52 and the fourth driving switch S 54 are turned on in the time interval between t 4 and t 5 . Consequently, the input capacitor Ciss discharges electricity, and the current flowing through the inductor L 51 increases. At the time point t 5 when the voltage of the input capacitor Ciss reaches Vp 2 , the second driving switch S 52 and the fourth driving switch S 54 are turned off, and the first driving switch S 51 and the third driving switch S 53 are turned on. Consequently, the input capacitor Ciss discharges electricity to the input power source through the inductor L 51 , and the current of the inductor L 51 gradually decreases until the current of the inductor L 51 is zero (i.e., at the time point t 6 ). Meanwhile, the first driving switch S 51 and the third driving switch S 53 are turned off. At the time point t 6 , the first parasitic capacitor Coss 51 is discharged to 0V, and the voltage of the second parasitic capacitor Coss 52 is Vcc. Consequently, in the time interval between t 6 and t 7 , the first parasitic capacitor Coss 51 and the second parasitic capacitor Coss 52 resonate with the input capacitor Ciss, the third parasitic capacitor Coss 53 and the fourth parasitic capacitor Coss 54 through the inductor L 51 . Due to the resonant oscillation, the voltage of the input capacitor Ciss gradually fluctuates from Vp 2 to a second steady voltage Vo 2 , and the voltage of the second parasitic capacitor Coss 32 gradually fluctuates to the voltage of the third parasitic capacitor Coss 53 . The input capacitor Ciss is connected in series with the fourth parasitic capacitor Coss 54 of the fourth driving switch S 54 , and then connected in parallel with the third parasitic capacitor Coss 53 of the third driving switch S 53 , and then connected in series with the first parasitic capacitor Coss 51 of the first driving switch S 51 and the second parasitic capacitor Coss 52 of the second driving switch S 52 . Consequently, in the time interval between t 6 and t 7 , the amount of charges charged into the input capacitor Ciss (i.e., from Vp 2 to Vo 2 ) is Q 3 . Moreover, Q 3 is equal to the change amount of charges in the first parasitic capacitor Coss 51 while the voltage is changed from 0V to second steady voltage Vo 2 plus the change amount of charges in the second parasitic capacitor Coss 52 while the voltage is changed from Vcc to the second steady voltage Vo 2 . When the voltage of the input capacitor Ciss reaches the second steady voltage Vo 2 , the second steady voltage Vo 2 must be lower than the second set voltage VL. Consequently, in the time interval between t 6 and t 7 , the change amount of charges of the input capacitor Ciss from Vp 2 to VL plus the change amount of charges of the third parasitic capacitor Coss 53 is equal to Q 4 . Especially, Q 4 is higher than or equal to Q 3 . That is, in the discharging procedure of the input capacitor Ciss, the relationships between Q 3 , Q 4 , Coss 51 , Coss 52 , Coss 53 , Coss 54 , Ciss, Vp 2 , VL, Vcc and Vo 2 satisfy the following formulae (43), (44) and (45)

Q 3=(Coss51+Coss52)×[ Vcc− ( Vo 2 −Vp 2)×(Ciss/Coss54)]  (43)

Q 4=(Coss53+Coss54)×( VL−Vp 2)×(Ciss/Coss54)+Coss53×( VL−Vp 2)   (44)

Q 3≤ Q 4   (45)

Preferably, the voltage Vp 2 is 0V. If the on duration of the second driving switch S 52 or the fourth driving switch S 54 is too long, the input capacitor Ciss is inversely charged. Under this circumstance, the voltage Vp 2 is lower than 0V, the oscillation extent of the voltage of the input capacitor Ciss is too large, and the energy loss increases.

In case that the first driving switch S 51 , the second driving switch S 52 , the third driving switch S 53 and the fourth driving switch S 54 are MOSFET with body diodes, the precision of controlling the first driving switch S 51 and the third driving switch S 53 may be reduced. After the discharging procedure of the input capacitor Ciss is completed, the voltages of the second parasitic capacitor Coss 52 and the third parasitic capacitor Coss 53 are lower than the second steady voltage Vo 2 of the input capacitor Ciss. In other words, (Vo 2 −Vp 2 )×(1+Ciss/Coss 54 )<Vo 2 . In the discharging procedure of the input capacitor Ciss, the relationships between Q 3 , Q 4 , Coss 51 , Coss 52 , Coss 53 , Coss 54 , Ciss, Vp 2 , VL and Vo 2 satisfy the following formulae (46), (47) and (48):

Q 3=(Coss51+Coss52)×[ Vcc −( Vo 2 −Vp 2)×(Ciss/Coss54)]  (46)

Q 4=(Coss53+Coss54)×( VL−Vp 2)×(Ciss/Coss54)+Coss53×( VL−Vp 2)   (47)

Q 3≤ Q 4   (48)

After the discharging procedure of the input capacitor Ciss is completed, if the voltages of the second parasitic capacitor Coss 52 and the third parasitic capacitor Coss 53 are clamped to Vo 2 by the body diode of the fourth driving switch S 54 , the relationships between Q 3 , Q 4 , Coss 51 , Coss 52 , Ciss, Vp 2 , VL and Vcc satisfy the following formulae (49), (50) and (51):

Q 3=(Coss51+Coss52)×( Vcc−VL )   (49)

Q 4=Ciss×( VL−Vp 2)   (50)

Q 3≤ Q 4   (51)

The driving circuit 3 A is substantially equivalent to the equivalent circuit 2 of FIG. 9 . However, the first equivalent capacitor Ci of this embodiment is related to the input capacitor Ciss of the power switch, the third parasitic capacitor Coss 53 of the first clamping circuit C 53 and the fourth parasitic capacitor Coss 54 of the third driving switch S 54 . The equivalent inductor L comprises the inductor L 51 of the driving circuit 3 A. The second equivalent capacitor Coss is related to the first parasitic capacitor Coss 51 of the first driving circuit S 51 and the second parasitic capacitor Coss 52 of the second driving circuit S 52 .

FIG. 33 is a schematic circuit diagram illustrating a driving circuit for a power switch according to a thirteenth embodiment of the present invention. As shown in FIG. 33 , the driving circuit 4 A comprises an inductor L 61 , a first driving switch S 61 and a resistor R. The capacitor Ciss is an input capacitor of the power switch (not shown). The first terminal of the first driving switch S 61 is electrically connected with the second terminal of the inductor L 61 . The second terminal of the first driving switch S 31 is electrically connected with the first terminal of the resistor R. The first terminal of the inductor L 61 is electrically connected with an input power source. The second terminal of the resistor R is electrically connected with the input capacitor Ciss. Moreover, the parasitic parameter of the first driving switch S 61 is a parasitic capacitor Coss 61 .

The operations of charging and discharging the input capacitor Ciss will be described as follows. In this embodiment, the first driving switch S 61 is selectively turned on or turned off to control the charging and discharging procedures of the input capacitor Ciss.

FIG. 34 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 33 in the charging procedure of the input capacitor. Firstly, the first driving switch S 61 is turned on in the time interval between t 0 and t 1 . Consequently, the electric energy of the supply voltage Vcc of the input power source charges the input capacitor Ciss through the first driving switch S 61 . The current flowing through the inductor L 61 increases and then gradually decreases. At the time point t 1 , the first driving switch S 31 is turned off, and the current of the inductor L 61 decreases to zero. Meanwhile, the input capacitor Ciss is charged to the voltage Vp 1 . The voltage Vp 1 is higher than the supply voltage Vcc but lower than or equal to 2×Vcc. In the time interval between t 1 and t 2 , the first parasitic capacitor Coss 61 resonates with the input capacitor Ciss through the inductor L 61 . Due to the resonant oscillation, the voltage of the input capacitor Ciss gradually fluctuates from Vp 1 to a first steady voltage Vo 1 , and the the parasitic capacitor Coss 61 fluctuates until the sum of the voltage of the parasitic capacitor Coss 61 and the supply voltage Vcc is equal to the voltage of the input capacitor Ciss. The input capacitor Ciss is serially connected with the parasitic capacitor Coss 61 of the first driving switch S 61 . Consequently, in the time interval between t 1 and t 2 , the amount of charges discharged from the input capacitor Ciss (i.e., from Vp 1 to Vo 1 ) is Q 1 . Moreover, Q 1 is equal to the change amount of charges in first parasitic capacitor Coss 61 while the voltage is changed from 0V to (Vo 1 -Vcc). When the voltage of the input capacitor Ciss reaches the first steady voltage Vo 1 , the first steady voltage Vo 1 must be higher than the first set voltage VH. Consequently, in the time interval between t 1 and t 2 , the change amount of charges of the input capacitor Ciss from Vp 1 to VH is equal to Q 2 . Especially, Q 2 is higher than or equal to Q 1 . That is, in the charging procedure of the input capacitor Ciss, the relationships between Q 1 , Q 2 , Coss 42 , Ciss, Vp 1 , VH and Vo 1 satisfy the following formulae (52), (53) and (54):

Q 1=Coss61×( Vo 1 −Vcc )   (52)

Q 2=Ciss×( Vp 1− VH )   (53)

Q 1 ≤Q 2   (54)

FIG. 35 is a schematic timing waveform diagram illustrating associated voltage signals of the driving circuit of FIG. 33 in the discharging procedure of the input capacitor. Firstly, the first driving switch S 61 is turned on in the time interval between t 0 and t 1 . Consequently, the input capacitor Ciss discharges electricity, and the current flowing through the inductor L 61 increases and then gradually decreases. At the time point t 1 when the voltage of the input capacitor Ciss reaches the voltage Vp 2 and the current of the inductor L 61 decreases to zero, the first driving switch S 61 is turned off. At the time point t 1 , the voltage of the input capacitor Ciss is Vp 2 . Preferably, the voltage Vp 2 is 0V, and the voltage of the input capacitor Ciss is 0V. Consequently, in the time interval between t 1 and t 2 , the first parasitic capacitor Coss 61 resonates with the input capacitor Ciss through the inductor L 61 . Due to the resonant oscillation, the voltage of the input capacitor Ciss gradually fluctuates from Vp 2 to a second steady voltage Vo 2 , and the voltage of the parasitic capacitor Coss 61 gradually fluctuates to the voltage (Vcc−Vo 2 ). The input capacitor Ciss is serially connected with the parasitic capacitor Coss 361 of the first driving switch S 61 . Consequently, in the time interval between t 1 and t 2 , the amount of charges charged into the input capacitor Ciss (i.e., from Vp 2 to Vo 2 ) is Q 3 . Moreover, Q 3 is equal to the change amount of charges in the parasitic capacitor Coss 61 while the voltage is changed from 0V to (Vcc−Vo 2 ). When the voltage of the input capacitor Ciss reaches the second steady voltage Vo 2 , the second steady voltage Vo 2 must be lower than the second set voltage VL. Consequently, in the time interval between t 1 and t 2 , the change amount of charges of the input capacitor Ciss from Vp 2 to VL is equal to Q 4 . Especially, Q 4 is higher than or equal to Q 3 . That is, in the discharging procedure of the input capacitor Ciss, the relationships between Q 3 , Q 4 , Coss 61 , Ciss, Vp 2 , VL, Vcc and Vo 2 satisfy the following formulae (55), (56) and (57)

Q 3=Coss61×( Vcc−Vo 2 )   (55)

Q 4=Ciss×( Vp 2− VL )   (56)

Q 3≤ Q 4   (57)

The driving circuit 4 A is substantially equivalent to the equivalent circuit 2 of FIG. 9 . However, the first equivalent capacitor Ci of this embodiment is related to the input capacitor Ciss of the power switch. The equivalent inductor L comprises the inductor L 61 of the driving circuit 4 A. The second equivalent capacitor Coss is related to the parasitic capacitor Coss 61 of the first driving circuit S 61 .

From the above descriptions, the present invention provides a driving circuit for a power switch. The inductor of the driving circuit does not need to provide the constant current. Under this circumstance, smaller inductance of the inductor may be required, and thus the volume of the inductor may be reduced. Moreover, the energy loss of the driving circuit may be reduced when compared with the conventional driving circuit.

While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.