Active device substrate and manufacturing method thereof

This application claims the priority benefit of Taiwan application serial no. 107134629, filed on Oct. 1, 2018. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

The present invention is related to an active device substrate, and more particularly to an active device substrate including a first active device and a second active device, and a method of manufacturing the same.

In recent years, with the advancement of display technology, the improvement of display resolution, computer computing technology and network speed has led to the rapid development of augmented reality (AR) and virtual reality (VR) technologies. In the foreseeable future, augmented reality and virtual reality technologies will be widely applied in education, logistics, medical, military and manufacturing, especially with the aid of Industry 4.0.

The display panel required for augmented reality and virtual reality applications is mainly loaded in a head-mounted display. The user's immersion is enhanced when the screen resolution of the display panel is improved. Therefore, the improvement of display panel resolution technology is the key to accelerate the development of augmented reality and virtual reality applications.

The present invention provides an active device substrate capable of improving insufficient screen resolution of a display panel.

The present invention provides a method of manufacturing an active device substrate, by which insufficient screen resolution of a display panel can be improved.

At least one embodiment of the present invention provides an active device substrate including a substrate, a first scan line, a second scan line, a data line, a first active device, a first pixel electrode, a second active device and a second pixel electrode. The first scan line, the second scan line and the data line are disposed on the substrate. The first active device includes a first semiconductor channel layer, a first gate, a first source and a first drain. The first gate is overlapped with the first semiconductor channel layer and electrically connected to the first scan line. The first source is electrically connected to the data line and the first semiconductor channel layer. The first drain is electrically connected to the first semiconductor channel layer. The first pixel electrode is electrically connected to the first drain. The second active device includes a second semiconductor channel layer, a second gate and a second drain. The first semiconductor channel layer is connected to a source region of the second semiconductor channel layer. The first semiconductor channel layer and the second semiconductor channel layer belong to the same layer. The second gate is overlapped with the second semiconductor channel layer and electrically connected to the second scan line. The second drain is electrically connected to the second semiconductor channel layer. The second pixel electrode is electrically connected to the second drain.

At least one embodiment of the present invention provides a method of manufacturing an active device substrate that includes the following steps. A substrate is provided. A semiconductor layer is formed on the substrate. A gate insulating layer is formed on the substrate. A treatment process is performed on the semiconductor layer to form a first semiconductor channel layer and a second semiconductor channel layer. The first semiconductor channel layer is connected to a source region of the second semiconductor channel layer. A first scan line, a second scan line, a first gate and a second gate are formed on the gate insulating layer. The first gate is electrically connected to the first scan line, and the second gate is electrically connected to the second scan line. An interlayer dielectric layer is formed on the first scan line, the second scan line, the first gate and the second gate. A first source, a data line, a first drain and a second drain are formed on the interlayer dielectric layer. The first source is electrically connected to the data line and the first semiconductor channel layer. The first drain and the second drain are electrically connected to the first semiconductor channel layer and the second semiconductor channel layer, respectively. A first insulating layer is formed on the first source, the first drain, the second drain, the data line and the interlayer dielectric layer. A first pixel electrode and a second pixel electrode are formed on the first insulating layer. The first pixel electrode and the second pixel electrode are electrically connected to the first drain and the second drain, respectively.

Several exemplary embodiments accompanied with figures are described in detail below to further describe the disclosure in details.

The accompanying drawings are included to provide further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments and, together with the description, serve to explain the principles of the disclosure.

FIG. 1A to FIG. 1F are schematic top views of a method of manufacturing an active device substrate in accordance with an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of an active device substrate in accordance with an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of an active device substrate in accordance with an embodiment of the present invention.

FIG. 4 is a schematic top view of an active device substrate in accordance with an embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of an active device substrate in accordance with an embodiment of the present invention.

FIG. 6A to FIG. 6D are schematic top views of a method of manufacturing an active device substrate in accordance with an embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of an active device substrate in accordance with an embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view of an active device substrate in accordance with an embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view of an active device substrate in accordance with an embodiment of the present invention.

FIG. 10 is a cross-sectional view of an active device substrate in accordance with an embodiment of the present invention.

FIG. 11A to FIG. 11G are schematic top views of a method of manufacturing an active device substrate in accordance with an embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view of an active device substrate in accordance with an embodiment of the present invention.

FIG. 13 is a schematic cross-sectional view of an active device substrate in accordance with an embodiment of the present invention.

FIG. 1A to FIG. 1F are schematic top views of a method of manufacturing an active device substrate in accordance with an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of an active device substrate in accordance with an embodiment of the present invention. FIG. 2 corresponds to a cross-sectional view taken along the line AA′ of FIG. 1F .

Referring to FIG. 1A and FIG. 2 , a substance SB is provided. The material of the substrate SB can be glass, quartz, an organic polymer, or an opaque/reflective material (e.g., a conductive material, metal, wafer, ceramics or the like), or another suitable material. If a conductive material or metal is used, an insulating layer (not shown) is overlaid on the substrate SB to prevent a short circuit from occurring. In some embodiments, a light shielding layer SM is optionally formed on the substrate SB. The light shielding layer SM is beneficial to improve the leakage issue of an active device substrate.

Referring to FIG. 1B and FIG. 2 , a semiconductor layer SC is formed on the substrate SB. The semiconductor layer SC can be overlapped with the light shielding layer SM. In the present embodiment, a buffer layer BL is formed before the formation of the semiconductor layer SC. The buffer layer BL can be located between the semiconductor layer SC and the light shielding layer SM, but the invention is not limited thereto. The material of the buffer layer BL includes an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, another suitable material or a stacked layer of at least two of the above materials), an organic material, another suitable material or a combination thereof.

The semiconductor layer SC has a single-layer or multi-layer structure, and includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single-crystalline silicon, an organic semiconductor material, an oxide semiconductor material (e.g., indium zinc oxide, indium gallium zinc oxide, another suitable material or a combination thereof), another suitable material or a combination thereof, or contains a dopant in the above materials. In the present embodiment, the semiconductor layer SC includes polycrystalline silicon, for example.

Referring to FIG. 1C , FIG. 1D and FIG. 2 , a gate insulating layer GI is formed on the substrate SB.

A first metal layer M 1 is formed on the gate insulating layer GI. The first metal layer M 1 is overlapped with a portion of the semiconductor layer SC. A heavily doping process is performed on the semiconductor layer SC by using the first metal layer M 1 as a mask, so as to form a heavily doped region P 1 in the semiconductor layer SC.

The first metal layer M 1 is patterned to form a first scan line SL 1 , a second scan line SL 2 , a first gate G 1 and a second gate G 2 . The first scan line SL 1 , the second scan line SL 2 , the first gate G 1 and the second gate G 2 are located on the gate insulating layer GI. The first gate G 1 is electrically connected to the first scan line SL 1 , and the second gate G 2 is electrically connected to the second scan line SL 2 .

In some embodiments, a lightly doping process is optionally performed on the semiconductor layer SC. For example, a lightly doping process is performed on the semiconductor layer SC by using the first scan line SL 1 , the second scan line SL 2 , the first gate G 1 and the second gate G 2 as a mask, so as to form a lightly doped region P 2 in the semiconductor layer SC.

A treatment process is performed on the semiconductor layer SC to form a first semiconductor channel layer SC 1 and a second semiconductor channel layer SC 2 . In some embodiments, the first semiconductor channel layer SC 1 and the second semiconductor channel layer SC 2 are, for example, P-type doped semiconductor materials or N-type doped semiconductor materials. In the present embodiment, the treatment process is the heavily doping process of FIG. 1C , and the heavily doping process ( FIG. 1C ) and the lightly doping process ( FIG. 1D ) are performed on the semiconductor layer SC to form the first semiconductor channel layer SC 1 and the second semiconductor channel layer SC 2 . However, the invention is not limited thereto. In another embodiment, the material of the semiconductor layer SC includes metal oxide, and the treatment process is a plasma treatment process.

The first semiconductor channel layer SC 1 includes a source region R 1 , a channel region R 2 and a drain region R 3 connected in sequence. The second semiconductor channel layer SC 2 includes a source region R 4 , a channel region R 5 and a drain region R 6 connected in sequence.

In the present embodiment, the channel region R 2 and the channel region R 5 have portions (i.e., the portions overlapped with the first gate G 1 and the second gate G 2 ) that are not subjected to the heavily doping process and the lightly doping process and belong to active regions P 3 , portions at two sides of the active regions P 3 that belong to the lightly doped region P 2 , and portions at two sides of the lightly doped regions P 2 that belong to the heavily doped region P 1 .

The first gate G 1 includes a first extending part X 1 and a first branch part Y 1 . The first extending part X 1 is connected to the first scan line SL 1 . The first branch part Y 1 is connected to the first extending part X 1 , and has an included angle θ 1 with the first extending part X 1 . The included angle θ 1 is, for example, less than 180 degrees and greater than 0 degrees. In this embodiment, the included angle is about 90 degrees. The first extending part X 1 and the first branch part Y 1 are respectively overlapped with the first semiconductor channel layer SC 1 . Therefore, the channel region R 2 has two separate active regions P 3 which are respectively overlapped with the first extending part X 1 and the first branch part Y 1 , thereby reducing the leakage current.

The second gate G 2 includes a second extending part X 2 and a second branch part Y 2 . The second extending part X 2 is connected to the second scan line SL 2 . The second branch part Y 2 is connected to the second extending part X 2 and has an included angle θ 2 with the second extending part X 2 . The second extending part X 2 and the second branch part Y 2 are respectively overlapped with the second semiconductor channel layer SC 2 . Therefore, the channel region R 5 has two separate active regions P 3 which are respectively overlapped with the second extending part X 2 and the second branch part Y 2 , thereby reducing the leakage current.

The source region R 1 , the drain region R 3 , the source region R 4 and the drain region R 6 are subjected to the heavily doping process, so the source region R 1 , the drain region R 3 , the source region R 4 and the drain region R 6 belong to the heavily doped region P 1 . In some embodiments, the heavily doped region P 1 has a dopant concentration of 10 18 -10 20 atoms/cm3. In some embodiments, the heavily doped region P 1 has a sheet resistance of ≤10 4 Ω/Square.

The drain region R 3 of the first semiconductor channel layer SC 1 is connected to the source region R 4 of the second semiconductor channel layer SC 2 .

Referring to FIG. 1E and FIG. 2 , an interlayer dielectric layer ILD is formed on the first scan line SL 1 , the second scan line SL 2 , the first gate G 1 and the second gate G 2 .

The first source S 1 , the data line DL, the first drain D 1 and the second drain D 2 are formed on the interlayer dielectric layer ILD. The first source S 1 is electrically connected to the data line DL and the first semiconductor channel layer SC 1 . The first drain D 1 and the second drain D 2 are electrically connected to the first semiconductor channel layer SC 1 and the second semiconductor channel layer SC 2 , respectively. In the present embodiment, the interlayer dielectric layer ILD has openings H 1 , H 2 and H 3 . The first dielectric S 1 is electrically connected to the source region R 1 of the first semiconductor channel layer SC 1 through the opening H 1 . The first drain D 1 and the second drain D 2 are respectively electrically connected to the drain region R 3 of the first semiconductor channel layer SC 1 and the drain region R 6 of the second semiconductor channel layer SC 2 through the opening H 2 and the opening H 3 .

At this point, a first active device T 1 and a second active device T 2 are substantially completed. The first active device T 1 and the second active device T 2 are located between the first scan line SL 1 and the second scan line SL 2 . The first active device T 1 includes a first semiconductor channel layer SC 1 , a first gate G 1 , a first source S 1 and a first drain D 1 . The first gate G 1 is overlapped with the first semiconductor channel layer SC 1 and electrically connected to the first scan line SL 1 . The first source S 1 is electrically connected to the data line DL and the first semiconductor channel layer SC 1 . The first drain D 1 is electrically connected to the first semiconductor channel layer SC 1 . The second active device T 2 includes a second semiconductor channel layer SC 2 , a second gate G 2 and a second drain D 2 . The first semiconductor channel layer SC 1 is connected to the source region R 4 of the second semiconductor channel layer SC 2 . The first semiconductor channel layer SC 1 and the second semiconductor channel layer SC 2 belong to the same layer. The second gate G 2 is overlapped with the second semiconductor channel layer SC 2 and electrically connected to the second scan line SL 2 . The second drain D 2 is electrically connected to the second semiconductor channel layer SC 2 .

Referring to FIG. 1F and FIG. 2 , a first insulating layer I 1 is formed on the first source S 1 , the first drain D 1 , the second drain D 2 , the data line DL and the interlayer dielectric layer ILD. A first common electrode C 1 and a second common electrode C 2 are formed on the first insulating layer I 1 .

In the present embodiment, a second insulating layer I 2 is optionally formed after the formation of the first common electrode C 1 and the second common electrode C 2 . A first pixel electrode PE 1 and a second pixel electrode PE 2 are formed on the second insulating layer I 2 . A first opening OP 1 and a second opening OP 2 are formed through the first insulating layer I 1 and the second insulating layer I 2 . The first pixel electrode PE 1 and the second pixel electrode PE 2 are electrically connected to the first drain D 1 and the second drain D 2 through the first opening OP 1 and the second opening OP 2 , respectively. In other words, the present embodiment is exemplified by a structure in which a common electrode is located between a substrate SB and a pixel electrode, but the present invention is not limited thereto. In another embodiment, the pixel electrode is located between the substrate SB and the common electrode.

At this point, an active device substrate 10 is substantially completed. The active device substrate 10 includes a substrate SB, a first scan line SL 1 , a second scan line SL 2 , a data line DL, a first active device T 1 , a first common electrode C 1 , a second common electrode C 2 , a first pixel electrode PE 1 , a second active device T 2 , and a second pixel electrode PE 2 .

Based on the above, the first semiconductor channel layer SC 1 of the first active device T 1 is connected to the second semiconductor channel layer SC 2 of the second active device T 2 , so both the first active device T 1 and the second active device T 2 can be driven by the same data line DL. As compared with the conventional active device substrate in which each active device is connected to a data line, the active device substrate 10 of the embodiment can be provided with less data lines, so the design space of the first active device T 1 and the second active device T 2 can be improved, and the aperture ratio of the pixels and the design limit of the resolution can be enhanced.

FIG. 3 is a schematic cross-sectional view of an active device substrate in accordance with an embodiment of the present invention. It is noted that the reference numbers of the components and a part of contents of FIG. 2 are also used in the embodiment of FIG. 3 , wherein the same reference numbers denote the same or like components, and descriptions of the same technical contents are omitted. The aforementioned embodiment can be referred for descriptions of the omitted parts, and detailed descriptions thereof are not repeated in the following embodiment.

The main difference between the active device substrate 20 of FIG. 3 and the active device substrate 10 of FIG. 2 lies in that, the material of the first semiconductor channel layer SC 1 and the second semiconductor channel layer SC 2 of the active device substrate 20 includes metal oxide.

In the present embodiment, a heavily doping process and a lightly doping process are not performed on the semiconductor layer. Rather, a plasma treatment process is performed on the semiconductor layer SC to form a first semiconductor channel layer SC 1 and a second semiconductor channel layer SC 2 .

The plasma treatment process can be performed by using a first gate G 1 and a second gate G 2 as a mask. For example, an insulating layer and a conductive material layer are formed on the semiconductor layer SC. The conductive material layer is etched to form a first scan line SL 1 , a second scan line SL 2 , a first gate G 1 and a second gate G 2 , and the insulating layer is etched to form a gate insulating layer GI. The gate insulating layer GI exposes the semiconductor layer SC, and the gate insulating layer GI is aligned with each of the first gate G 1 and the second gate G 2 , for example. Thereafter, the semiconductor layer SC is subjected to a plasma treatment process by using the first scan line SL 1 , the second scan line SL 2 , the first gate G 1 and the second gate G 2 as a mask. In another embodiment, a plasma treatment process is performed before the first gate G 1 and the second gate G 2 are formed, and the plasma treatment process is performed by using a mask pattern (not shown) additionally formed on the semiconductor layer SC as a mask.

The first semiconductor channel layer SC 1 includes a channel region R 2 overlapped with the first gate G 1 , and a source region R 1 and a drain region R 3 respectively located at two sides of the channel region R 2 . The resistivity of the source region R 1 and the drain region R 3 is smaller than the resistivity of the channel region R 2 .

The second semiconductor channel layer SC 2 includes a channel region R 5 overlapped with the second gate G 2 , and a source region R 4 and a drain region R 6 respectively located at two sides of the channel region R 5 . The resistivity of the source region R 4 and the drain region R 6 is smaller than the resistivity of the channel region R 5 .

Based on the above, the first semiconductor channel layer SC 1 of the first active device T 1 is connected to the second semiconductor channel layer SC 2 of the second active device T 2 , so both the first active device T 1 and the second active device T 2 can be driven by the same data line DL. As compared with the conventional active device substrate in which each active device is connected to a data line, the active device substrate 20 of the embodiment can be provided with less data lines, so the design space of the first active device T 1 and the second active device T 2 can be improved, and the aperture ratio of the pixels and the design limit of the resolution can be enhanced.

FIG. 4 is a schematic top view of an active device substrate in accordance with an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of an active device substrate in accordance with an embodiment of the present invention. FIG. 5 corresponds to a cross-sectional view taken along the line BB′ of FIG. 4 . It is noted that the reference numbers of the components and a part of contents of FIG. 2 are also used in the embodiments of FIG. 4 and FIG. 5 , wherein the same reference numbers denote the same or like components, and descriptions of the same technical contents are omitted. The aforementioned embodiment can be referred for descriptions of the omitted parts, and detailed descriptions thereof are not repeated in the following embodiment.

The main difference between the active device substrate 30 of FIG. 4 and the active device substrate 10 of FIG. 2 lies in that, the active device substrate 30 further includes a third scan line SL 3 and a third active device T 3 , the third active device T 3 includes a third semiconductor channel layer SC 3 , a third gate G 3 and a third drain D 3 .

In the present embodiment, the first metal layer M 1 is patterned to form a first scan line SL 1 , a second scan line SL 2 , a third scan line SL 3 , a first gate G 1 , a second gate G 2 and a third gate G 3 . The first scan line SL 1 , the second scan line SL 2 , the third scan line SL 3 , the first gate G 1 , the second gate G 2 and third gate G 3 are located on gate insulating layer GI. The first gate G 1 is electrically connected to the first scan line SL 1 , the second gate G 2 is electrically connected to the second scan line SL 2 , and the third gate G 3 is electrically connected to the third scan line SL 3 .

Each of the first scan line SL 1 , the second scan line SL 2 and the third scan line SL 3 includes a first conductive line L 1 and a second conductive line L 2 parallel to each other. Each of the first gate G 1 , the second gate G 2 and the third gate G 3 includes a first part Z 1 and a second part Z 2 separated from each other. The first part Z 1 and the second part Z 2 are electrically connected to the first conductive line L 1 and the second conductive line L 2 , respectively.

A treatment process is performed on the semiconductor layer SC to form a first semiconductor channel layer SC 1 , a second semiconductor channel layer SC 2 and a third semiconductor channel layer SC 3 . In the present embodiment, the treatment process a similar to the heavily doping process of FIG. 1C , and the heavily doping process ( FIG. 1C ) and the lightly doping process ( FIG. 1D ) are performed on the semiconductor layer SC to form the first semiconductor channel layer SC 1 , the second semiconductor channel layer SC 2 and the third semiconductor channel layer SC 3 . However, the invention is not limited thereto. In another embodiment, the material of the semiconductor layer SC includes metal oxide, and the treatment process is a plasma treatment process. In the present embodiment, the first semiconductor channel layer SC 1 , the second semiconductor channel layer SC 2 and the third semiconductor channel layer SC 3 belong to the same layer. The third semiconductor channel layer SC 3 includes a source region R 7 , a channel region R 8 and a drain region R 9 connected in sequence. The third gate G 3 is overlapped with the channel region R 8 of the third semiconductor channel layer SC 3 .

The first semiconductor channel layer SC 1 , the second semiconductor channel layer SC 2 and the third semiconductor channel layer SC 3 are sequentially connected. For example, the drain region R 3 of the first semiconductor channel layer SC 1 is connected to the source region R 4 of the second semiconductor channel layer SC 2 , and the drain region R 6 of the second semiconductor channel layer SC 2 is connected to the source region R 7 of the third semiconductor channel layer SC 3 .

The third drain D 3 is electrically connected to the drain region R 9 of the third semiconductor channel layer SC 3 through the opening H 4 . The third pixel electrode PE 3 is electrically connected to the third drain D 3 through the opening OP 3 . A first common electrode C 1 , a second common electrode C 2 and a third common electrode C 3 are overlapped with the first pixel electrode PE 1 , the second pixel electrode PE 2 and the third pixel electrode PE 3 .

Based on the above, the first semiconductor channel layer SC 1 of the first active device T 1 is connected to the second semiconductor channel layer SC 2 of the second active device T 2 , and the second semiconductor channel layer SC 2 of the second active device T 2 is connected to the third semiconductor channel layer SC 3 of the third active device T 3 , and therefore, the first active device T 1 , the second active device T 2 and the third active device T 3 can all be driven by the same data line DL. As compared with the conventional active device substrate in which each active device is connected to a data line, the active device substrate 30 of the embodiment can be provided with less data lines, so the design space of the first active device T 1 , the second active device T 2 and the third active device T 3 can be improved, and the aperture ratio of the pixels and the design limit of the resolution can be enhanced.

The present embodiment is exemplified by semiconductor channel layers of three active devices that are connected in sequence, but the present invention is not limited thereto. In another embodiment, semiconductor channel layers of more than three active devices can be connected in sequence.

FIG. 6A to FIG. 6D are schematic top views of a method of manufacturing an active device substrate in accordance with an embodiment of the present invention. FIG. 7 is a schematic cross-sectional view of an active device substrate in accordance with an embodiment of the present invention. FIG. 7 corresponds to a cross-sectional view taken along the line CC′ of FIG. 6D .

It is noted that the reference numbers of the components and a part of contents of FIG. 1A to FIG. 1F and FIG. 2 are also used in the embodiments of FIG. 6A to FIG. 6D and FIG. 7 , wherein the same reference numbers denote the same or like components, and descriptions of the same technical contents are omitted. The aforementioned embodiment can be referred for descriptions of the omitted parts, and detailed descriptions thereof are not repeated in the following embodiment.

The main difference between the embodiment of FIG. 6A to FIG. 6D and the embodiment of FIG. 1A to FIG. 1F lies in that, in the manufacturing method of active device substrate 40 of FIG. 6A to FIG. 6D , a treatment process is performed before the first scan line SL 1 , the second scan line SL 2 , the first gate G 1 and the second gate G 2 are formed on the gate insulating layer GI.

The step of FIG. 6A follows the manufacturing step of FIG. 1B . Referring to FIG. 6A and FIG. 7 , a treatment process is performed on the semiconductor layer SC to form a heavily doped region P 1 in the semiconductor layer SC. The treatment process is a heavily doping process, for example.

In the present embodiment, for example, a mask pattern (not shown) is formed on the semiconductor layer SC to define a region in the semiconductor layer SC where the heavily doped region P 1 is to be formed, and then the mask pattern is removed. The mask pattern can be formed before the formation of the gate insulating layer GI or after the formation of the gate insulating layer GI, and the forming sequence is not particularly limited by the present invention.

Referring to FIG. 6B and FIG. 7 , a first scan line SL 1 , a second scan line SL 2 , a first gate G 1 and a second gate G 2 are formed on gate insulating layer GI. The first gate G 1 and the second gate G 2 are overlapped with the semiconductor layer SC, and the overlapped area is smaller than the area where the semiconductor layer SC is not subjected to the heavily doping process. After the first scan line SL 1 , the second scan line SL 2 , the first gate G 1 and the second gate G 2 are formed on the gate insulating layer GI, a lightly doping process is performed on the semiconductor layer SC by using the first scan line SL 1 , the second scan line SL 2 , the first gate G 1 and the second gate G 2 as a mask, so as to form a lightly doped region P 2 in the semiconductor layer SC.

In the present embodiment, while the first scan line SL 1 , the second scan line SL 2 , the first gate G 1 and the second gate G 2 are formed on the gate insulating layer GI, a capacitor electrode CE is simultaneously formed on the gate insulating layer GI. In other words, the capacitor electrode CE, the first scan line SL 1 , the second scan line SL 2 , the first gate G 1 and second gate G 2 belong to the same layer. The extending direction of the capacitor electrode CE, the extending direction of the first scan line SL 1 , and the extending direction of the second scan line SL 2 are substantially the same, but the invention is not limited thereto.

In the present embodiment, the capacitor electrode CE, the first scan line SL 1 , the second scan line SL 2 , the first gate G 1 and the second gate G 2 belong to the same layer. Besides, the capacitor electrode CE is overlapped with the semiconductor layer SC; that is, the capacitor electrode CE is overlapped with the first semiconductor channel layer SC 1 and/or the second semiconductor channel layer SC 2 . Therefore, the lightly doping process is performed by using the capacitor electrode CE, the first scan line SL 1 , the second scan line SL 2 , the first gate G 1 and the second gate G 2 as a mask. In the present embodiment, the capacitor electrode CE can constitute a capacitor with the first semiconductor channel layer SC 1 and/or the second semiconductor channel layer SC 2 .

Referring to FIG. 6C and FIG. 7 , an interlayer dielectric layer ILD is formed on the first scan line SL 1 , the second scan line SL 2 , the first gate G 1 , the second gate G 2 and the capacitor electrode CE.

A first source S 1 , a data line DL, a first drain D 1 and a second drain D 2 are formed on the interlayer dielectric layer ILD. The first source S 1 is electrically connected to the data line DL and the first semiconductor channel layer SC 1 . The first drain D 1 and the second drain D 2 are electrically connected to the first semiconductor channel layer SC 1 and the second semiconductor channel layer SC 2 , respectively. In the present embodiment, the interlayer dielectric layer ILD has openings H 1 , H 2 and H 3 . The first source S 1 is electrically connected to the source region R 1 of the first semiconductor channel layer SC 1 through the opening H 1 . The first drain D 1 and the second drain D 2 are respectively electrically connected to the drain region R 3 of the first semiconductor channel layer SC 1 and the drain region R 6 of the second semiconductor channel layer SC 2 through the opening H 2 and opening H 3 .

At this point, a first active device T 1 and a second active device T 2 are substantially completed.

Refer to FIG. 6D and FIG. 7 , a first insulating layer I 1 is formed on the first source S 1 , the first drain D 1 , the second drain D 2 , the data line DL and the interlayer dielectric layer ILD. A first common electrode C 1 and a second common electrode C 2 are formed on the first insulating layer I 1 .

In the present embodiment, a second insulating layer I 2 is optionally formed after the formation of the first common electrode C 1 and the second common electrode C 2 . A first pixel electrode PE 1 and a second pixel electrode PE 2 are formed after the formation of the second insulating layer I 2 . The first pixel electrode PE 1 and the second pixel electrode PE 2 are located on the second insulating layer I 2 . A first opening OP 1 and a second opening OP 2 are formed through the first insulating layer I 1 and the second insulating layer I 2 . In other words, the present embodiment is exemplified by a structure in which a common electrode is located between a substrate SB and a pixel electrode, but the present invention is not limited thereto. In another embodiment, the pixel electrode is located between the substrate SB and the common electrode.

At this point, an active device substrate 40 is substantially completed. The active device substrate 40 includes a substrate SB, a first scan line SL 1 , a second scan line SL 2 , a data line DL, a first active device T 1 , a first common electrode C 1 , a second common electrode C 2 , a first pixel electrode PE 1 , a second active device T 2 , a second pixel electrode PE 2 and capacitor electrode CE.

Based on the above, the first semiconductor channel layer SC 1 of the first active device T 1 is connected to the second semiconductor channel layer SC 2 of the second active device T 2 , so both the first active device T 1 and the second active device T 2 can be driven by the same data line DL. As compared with the conventional active device substrate in which each active device is connected to a data line, the active device substrate 40 of the embodiment can be provided with less data lines, so the design space of the first active device T 1 and the second active device T 2 can be improved, and the aperture ratio of the pixels and the design limit of the resolution can be enhanced.

FIG. 8 is a schematic cross-sectional view of an active device substrate in accordance with an embodiment of the present invention. It is noted that the reference numbers of the components and a part of contents of FIG. 7 are also used in the embodiment of FIG. 8 , wherein the same reference numbers denote the same or like components, and descriptions of the same technical contents are omitted. The aforementioned embodiment can be referred for descriptions of the omitted parts, and detailed descriptions thereof are not repeated in the following embodiment.

The main difference between the active device substrate 50 of FIG. 8 and the active device substrate 40 of FIG. 7 lies in that, the material of the first semiconductor channel layer SC 1 and the second semiconductor channel layer SC 2 of the active device substrate 50 includes metal oxide.

In the present embodiment, the gate insulating layer GI exposes the semiconductor layer, and the gate insulating layer GI is aligned with each of the first gate G 1 , the second gate G 2 and the capacitor electrode CE, for example. In the present embodiment, a heavily doping process and a lightly doping process are not performed on the semiconductor layer. Rather, a plasma treatment process is performed on the semiconductor layer SC to form a first semiconductor channel layer SC 1 and a second semiconductor channel layer SC 2 .

In the present embodiment, the plasma treatment process can be performed by using a mask pattern (not shown) additionally formed on the semiconductor layer SC as a mask. For example, before the first gate G 1 , the second gate G 2 and the capacitor electrode CE are formed, a mask pattern is formed on the semiconductor layer SC to define regions (i.e., source regions R 1 and R 4 , and drain region R 3 and R 6 ) to be subjected to a plasma treatment process. A first gate G 1 , a second gate G 2 and a capacitor electrode CE are formed after the plasma treatment process. The aforementioned mask pattern is removed after the plasma treatment process is performed.

The first semiconductor channel layer SC 1 includes a channel region R 2 overlapped with the first gate G 1 , and a source region R 1 and a drain region R 3 respectively located at both sides of the channel region R 2 . The resistivity of the source region R 1 and the drain region R 3 is smaller than the resistivity of the channel region R 2 .

The second semiconductor channel layer SC 2 includes a channel region R 5 overlapped with the second gate G 2 , and a source region R 4 and a drain region R 6 respectively located at both sides of the channel region R 5 . The resistivity of the source region R 4 and the drain region R 6 is smaller than the resistivity of the channel region R 5 .

Based on the above, the first semiconductor channel layer SC 1 of the first active device T 1 is connected to the second semiconductor channel layer SC 2 of the second active device T 2 , so both the first active device T 1 and the second active device T 2 can be driven by the same data line DL. As compared with the conventional active device substrate in which each active device is connected to a data line, the active device substrate 50 of the embodiment can be provided with less data lines, so the design space of the first active device T 1 and the second active device T 2 can be improved, and the aperture ratio of the pixels and the design limit of the resolution can be enhanced.

FIG. 9 is a schematic cross-sectional view of an active device substrate in accordance with an embodiment of the present invention. It must be note that the reference numbers of the components and a part of contents of FIG. 7 are also used in the embodiment of FIG. 9 , and the same reference numbers denote the same or like components, and descriptions of the same technical contents are omitted. The aforementioned embodiment can be referred for descriptions of the omitted parts, and detailed descriptions thereof are not repeated in the following embodiment.

The main difference between the active device substrate 60 of FIG. 9 and the active device substrate 40 of FIG. 7 lies in that, the first drain D 1 is overlapped with the capacitor electrode CE.

In the preset embodiment, the capacitor electrode CE can not only constitute a capacitor with the first semiconductor channel layer SC 1 and/or the second semiconductor channel layer SC 2 , but also constitute a capacitor with the first drain D 1 .

Based on the above, the capacitor electrode CE of this embodiment can provide a higher storage capacitance.

FIG. 10 is a cross-sectional view of an active device substrate in accordance with an embodiment of the present invention. It must be note that the reference numbers of the components and a part of contents of FIG. 8 are also used in the embodiment of FIG. 10 , and the same reference numbers denote the same or like components, and descriptions of the same technical contents are omitted. The aforementioned embodiment can be referred for descriptions of the omitted parts, and detailed descriptions thereof are not repeated in the following embodiment.

The main difference between the active device substrate 70 of FIG. 10 and the active device substrate 50 of FIG. 8 lies in that, the first drain D 1 is overlapped with the capacitor electrode CE.

In the preset embodiment, the capacitor electrode CE can not only constitute a capacitor with the first semiconductor channel layer SC 1 and/or the second semiconductor channel layer SC 2 , but also constitute a capacitor with the first drain D 1 .

Based on the above, the capacitor electrode CE of this embodiment can provide a higher storage capacitance.

FIG. 11A to FIG. 11G are schematic top views of a method of manufacturing an active device substrate in accordance with an embodiment of the present invention. FIG. 12 is a schematic cross-sectional view of an active device substrate in accordance with an embodiment of the present invention. FIG. 12 corresponds to a cross-sectional view taken along the line DD′ of FIG. 11G .

It is noted that the reference numbers of the components and a part of contents of FIG. 1A to FIG. 1F and FIG. 2 are also used in the embodiments of FIG. 11A to FIG. 11G and FIG. 12 , wherein the same reference numbers denote the same or like components, and descriptions of the same technical contents are omitted. The aforementioned embodiment can be referred for descriptions of the omitted parts, and detailed descriptions thereof are not repeated in the following embodiment.

The main difference between the active device substrate 80 of FIG. 11 and FIG. 12 and the active device substrate 10 of FIG. 1F and FIG. 2 lies in that, the active device substrate 80 further includes a first island structure IS 1 and a second island structure IS 2 .

The step of FIG. 11A follows the manufacturing step of FIG. 1D . Referring to FIG. 11A and FIG. 12 , an interlayer dielectric layer ILD is formed on the first scan line SL 1 , the second scan line SL 2 , the first gate G 1 and the second gate G 2 . The interlayer dielectric layer ILD has openings H 1 , H 2 and H 3 . A second metal layer M 2 is formed on the interlayer dielectric layer ILD.

Referring to FIG. 11B and FIG. 11C , a first photosensitive material RS 1 is formed on the second metal layer M 2 . The first photosensitive material RS 1 is patterned, and then the patterned first photosensitive material RS 1 is cured to form a first island structure IS 1 and a second island structure IS 2 on the second metal layer M 2 . In other words, the material of the first island structure IS 1 and the second island structure IS 2 includes a cured photosensitive material. The first island structure IS 1 and the second island structure IS 2 are configured to correspond to the opening H 2 and opening H 3 , respectively.

Referring to FIG. 11D and FIG. 12 , a patterned second photosensitive material RS 2 is formed on the second metal layer M 2 . The patterned second photosensitive material RS 2 is configured to correspond to the opening H 1 . In the present embodiment, the curing degree of the first island structure IS 1 and the second island structure IS 2 can be greater than the curing degree of the patterned second photosensitive material RS 2 , and therefore, the first island structure IS 1 and the second island structure IS 2 are less susceptible to damage during the process (e.g., a developing process) of forming the patterned second photosensitive material RS 2 .

Referring to FIG. 11E , FIG. 11F and FIG. 12 , the second metal layer M 2 is patterned by using the second source material RS 2 , the first island structure IS 1 and the second island structure IS 2 as a mask, so as to form a first source S 1 , a data line DL, a first drain D 1 and a second drain D 2 . The first source S 1 is electrically connected to the source region R 1 of the first semiconductor channel layer SC 1 through the opening H 1 . The first drain D 1 and the second drain D 2 are respectively electrically connected to the drain region R 3 of the first semiconductor channel layer SC 1 and the drain region R 6 of the second semiconductor channel layer SC 2 through the opening H 2 and the opening H 3 . The first island structure IS 1 and the second island structure IS 2 are located above the first drain D 1 and the second drain D 2 , respectively. The patterned second photosensitive material RS 2 is located above the data line DL. The vertical projection area of the first island structure IS 1 on the substrate SB is substantially the same as the vertical projection area of the first drain D 1 on the substrate SB. The vertical projection area of the second island structure IS 2 on the substrate SB is substantially the same as the vertical projection area of the second drain D 2 on the substrate SB. The vertical projection area of the patterned second photosensitive material RS 2 on the substrate SB is substantially the same as the vertical projection area of the data line DL on the substrate SB.

The patterned second photosensitive material RS 2 is removed (or stripped). The curing degree of the first island structure IS 1 and the second island structure IS 2 can be greater than the curing degree of the patterned second photosensitive material RS 2 , and thus, the first island structure IS 1 and the second island structure IS 2 remain after the patterned second photosensitive material RS 2 is removed.

In the present embodiment, the process of forming the first island structure IS 1 , the second island structure IS 2 and the patterned second photosensitive material RS 2 includes two patterning steps, so that the resolution limit of forming the first source S 1 , the data line DL, the first drain D 1 and the second drain D 2 is improved. In other words, the distance between any two of the first source S 1 , the data line DL, the first drain D 1 and second drain D 2 can be reduced.

Referring to FIG. 11G and FIG. 12 , a first insulating layer I 1 is formed on the first source S 1 , the first drain D 1 , the second drain D 2 , the data line DL, the interlayer dielectric layer ILD, the first island structure IS 1 and the second island structure IS 2 . The first insulating layer I 1 covers the first island structure IS 1 , the second island structure IS 2 and the data line DL.

A first common electrode C 1 and a second common electrode C 2 are formed on the first insulating layer I 1 .

In the present embodiment, a second insulating layer I 2 is optionally formed after the formation of the first common electrode C 1 and the second common electrode C 2 . A first pixel electrode PE 1 and a second pixel electrode PE 2 are formed after the formation of the second insulating layer I 2 . The first pixel electrode PE 1 is electrically connected to the first drain D 1 through the first opening OP 1 , and the second pixel electrode PE 2 is electrically connected to the second drain D 2 through the second opening OP 2 . The first opening OP 1 penetrates through the first island structure IS 1 and the first insulating layer I 1 , and the second opening OP 2 penetrates through the second island structure IS 2 and the first insulating layer I 1 . In other words, the present embodiment is exemplified by a structure in which a common electrode is located between a substrate SB and a pixel electrode, but the present invention is not limited thereto. In another embodiment, the pixel electrode is located between the substrate SB and the common electrode.

At this point, an active device substrate 80 is substantially complete. The active device substrate 80 includes a substrate SB, a first scan line SL 1 , a second scan line SL 2 , a data line DL, a first active device T 1 , a first pixel electrode PE 1 , a second active device T 2 , a second pixel electrode PE 2 , a first island structure IS 1 and a second island structure IS 2 .

Based on the above, the first semiconductor channel layer SC 1 of the first active device T 1 is connected to the second semiconductor channel layer SC 2 of the second active device T 2 , so both the first active device T 1 and the second active device T 2 can be driven by the same data line DL. As compared with the conventional active device substrate in which each active device is connected to a data line, the active device substrate 80 of the embodiment can be provided with less data lines, so the design space of the first active device T 1 and the second active device T 2 can be improved, and the aperture ratio of the pixels and the design limit of the resolution can be enhanced.

FIG. 13 is a schematic cross-sectional view of an active device substrate in accordance with an embodiment of the present invention. It is noted that the reference numbers of the components and a part of contents of FIG. 12 are also used in the embodiment of FIG. 13 , wherein the same reference numbers denote the same or like components, and descriptions of the same technical contents are omitted. The aforementioned embodiment can be referred for descriptions of the omitted parts, and detailed descriptions thereof are not repeated in the following embodiment.

The main difference between the active device substrate 90 of FIG. 13 and the active device substrate 80 of FIG. 12 lies in that, the material of the first semiconductor channel layer SC 1 and the second semiconductor channel layer SC 2 of the active device substrate 90 includes metal oxide.

In the present embodiment, a heavily doping process and a lightly doping process are not performed on the semiconductor layer. Rather, a plasma treatment process is performed on the semiconductor layer to form a first semiconductor channel layer SC 1 and a second semiconductor channel layer SC 2 .

The first semiconductor channel layer SC 1 includes a channel region R 2 overlapped with the first gate G 1 , and a source region R 1 and a drain region R 3 respectively located at both sides of the channel region R 2 . The resistivity of the source region R 1 and the drain region R 3 is smaller than the resistivity of the channel region R 2 .

The second semiconductor channel layer SC 2 includes a channel region R 5 overlapped with the second gate G 2 , and a source region R 4 and a drain region R 6 respectively located at both sides of the channel region R 5 . The resistivity of the source region R 4 and the drain region R 6 is smaller than the resistivity of the channel region R 5 .

Based on the above, the first semiconductor channel layer SC 1 of the first active device T 1 is connected to the second semiconductor channel layer SC 2 of the second active device T 2 , so both the first active device T 1 and the second active device T 2 can be driven by the same data line DL. As compared with the conventional active device substrate in which each active device is connected to a data line, the active device substrate 90 of the embodiment can be provided with less data lines, so the design space of the first active device T 1 and the second active device T 2 can be improved, and the aperture ratio of the pixels and the design limit of the resolution can be enhanced.

In summary, the first active device and the second active device of the present invention can be driven by the same data line. As compared with the conventional active device substrate in which each active device is connected to a data line, the active device substrate of the invention can be provided with less data lines, so the design space of the first active device and the second active device can be improved, and the aperture ratio of the pixels and the design limit of the resolution can be enhanced.

It will be apparent to those skilled in the art that various modifications and variations may be made to the structure of the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims and their equivalents.