Semiconductor integrated circuit and adjustment method for semiconductor integrated circuit

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-040502, filed on Mar. 6, 2019; the entire contents of which are incorporated herein by reference.

The present embodiment generally relates to a semiconductor integrated circuit and an adjustment method for a semiconductor integrated circuit.

A semiconductor device which includes a normally-on type switching element and a normally-off type switching element that are cascode-connected to each other is disclosed conventionally. For example, a normally-on type switching element is composed of a transistor with a material that is gallium nitride (GaN) or silicon carbide (SiC). A normally-on type switching element that is composed of GaN or SiC is used to provide a semiconductor device with a high voltage resistance and a low loss. In a semiconductor device with such a configuration, a normally-off type switching element is turned on/off to turn on/off a normally-on type switching element.

Due to a characteristic of a normally-on type switching element that is in an on-state even in a state where a gate-source voltage is 0V, the normally-on type switching element is instantaneously turned on at a time when a normally-off type switching element is turned on, and a drain voltage thereof is shifted steeply. A steep shift of a drain voltage of a normally-on type switching element generates unnecessary radiation. Hence, a variety of attempts are executed to suppress a steep variation of a drain voltage of a normally-on type switching element at a time when a normally-off type switching element is turned on. A semiconductor integrated circuit and an adjustment method for a semiconductor integrated circuit are desired that utilize a characteristic of a semiconductor device that includes a normally-on type switching element and are capable of readily suppressing a steep shift of a drain voltage of the normally-on type switching element at a time when a normally-off type switching element is turned on/off.

FIG. 1 is a diagram illustrating a semiconductor integrated circuit according to a first embodiment.

FIG. 2 is a diagram illustrating a characteristic of a normally-on type switching element.

FIG. 3 is a diagram illustrating a result of simulation.

FIG. 4 is a diagram illustrating a semiconductor integrated circuit according to a second embodiment.

FIG. 5 is a diagram illustrating a semiconductor integrated circuit according to a third embodiment.

FIG. 6 is a diagram for explaining a control method for a semiconductor integrated circuit.

FIG. 7 is a flowchart illustrating a control method for a semiconductor integrated circuit.

According to one embodiment, a semiconductor integrated circuit includes a normally-on type first switching element that has a source, a drain, and a gate, a normally-off type second switching element that has a drain that is connected to the source of the first switching element, a gate that is supplied with a driving signal, and a source, a resistor that is connected between the gate of the first switching element and the source of the second switching element, a first capacitor that is connected in parallel to the resistor, and a second capacitor between the gate and the source of the first switching element.

Hereinafter, a semiconductor integrated circuit and an adjustment method for a semiconductor integrated circuit according to embodiments will be explained in detail with reference to the accompanying drawings. Additionally, the present invention is not limited by such embodiments.

First Embodiment

FIG. 1 is a diagram illustrating a semiconductor integrated circuit according to a first embodiment. A semiconductor integrated circuit according to the present embodiment has a normally-on type switching element Q 1 . The switching element Q 1 is composed of, for example, an N-channel type MOS transistor with a material that is GaN. For example, a main current path between a drain and a source of a MOS transistor with a material that is GaN is composed of GaN. Hereinafter, it may be referred to as a GaN transistor.

A normally-off type switching element Q 2 is composed of, for example, an N-channel type MOS transistor with a material that is Si. For example, a main current path between a drain and a source of the MOS transistor with a material that is Si is composed of Si. Hereinafter, it may be referred to as a Si transistor. A drain of the switching element Q 1 is connected to a terminal 11 . The terminal 11 is connected to, for example, a (non-illustrated) power source line where a voltage of 600V is applied thereto via (non-illustrated) another switching element. A source of the switching element Q 1 is connected to a drain of the switching element Q 2 .

A source of the switching element Q 2 is connected to a terminal 12 . The terminal 12 is supplied with, for example, ground potential. A gate of the switching element Q 2 is connected to a terminal 10 . A driving signal V D is applied to the terminal 10 .

A resistor R 1 is connected between a gate of the switching element Q 1 and the source of the switching element Q 2 . A capacitor C 1 is connected in parallel to the resistor R 1 . A capacitor C 2 is connected between the gate and the source of the switching element Q 1 . A common connection terminal for the capacitor C 1 and the capacitor C 2 is connected to the gate of the switching element Q 1 .

An operation in the present embodiment is as follows. As a driving signal V D that is applied to the gate of the switching element Q 2 is High, the switching element Q 2 is turned on. As the switching element Q 2 is turned on, a drain voltage V X of the switching element Q 2 is a voltage of the terminal 12 , for example, ground potential.

A series circuit of the capacitor C 1 and the capacitor C 2 is charged with a voltage between the terminal 12 and the drain of the switching element Q 2 when the switching element Q 2 is in an off-state, that is, a drain voltage V X . A sum of a voltage between both terminals of the capacitor C 1 and a voltage between both terminals of the capacitor C 2 is equal to a differential voltage between the terminal 12 and a drain voltage V. Additionally, when sufficient time has passed since the switching element Q 2 is in an off-state, voltages at both terminals of the capacitor C 1 are equal. Furthermore, a voltage between both terminals of C 2 is equal to a differential voltage between the terminal 12 and a drain voltage V X , so that an electric charge is stored depending on such a differential voltage.

As the switching element Q 2 is turned on, a drain voltage V X of the switching element Q 2 falls to a potential of the terminal 12 , that is, ground potential. As a drain voltage V X of the switching element Q 2 falls to ground potential, a gate voltage V G of the switching element Q 1 drops. Thereby, a gate voltage V G of the switching element Q 1 falls to a negative potential that is lower than ground potential.

When the switching element Q 2 is turned on, a gate-source of the switching element Q 1 is biased by a voltage between both terminals of the capacitor C 2 . As a drain voltage V X falls to ground potential, an electric charge that is stored in the capacitor C 2 is redistributed between the capacitor C 1 and the capacitor C 2 , so that a gate voltage V G of the switching element Q 1 is changed by a capacitance ratio between the capacitor C 1 and the capacitor C 2 . In other words, as capacitance values of the capacitor C 1 and the capacitor C 2 are selected, it is possible to adjust a gate voltage V G of the switching element Q 1 at a time when the switching element Q 2 is turned on or a gate-source voltage V GS of the switching element Q 1 .

An on-state of the normally-on type switching element Q 1 is determined by a gate-source voltage V GS . Therefore, it is possible to adjust an on-state of the normally-on type switching element Q 1 by setting of capacitance values of the capacitor C 1 and the capacitor C 2 .

For example, adjustment is executed in such a manner that a gate-source voltage V GS of the switching element Q 1 at a time when the switching element Q 2 is turned on is a value close to a threshold value of the switching element Q 1 , so that control is executed in such a manner that the switching element Q 1 is in a weak on-state. Furthermore, when the switching element Q 2 is turned on, the switching element Q 1 is not in an off-state but is in a strong on-state, so that it is possible to decrease a delay of a response of the switching element Q 1 . A more detailed method of adjustment will be described later.

As the switching element Q 2 is turned on, a state is provided where the drain and the source of the switching element Q 2 are connected substantially, so that a CR circuit that is provided by a parallel connection of the capacitor C 1 and the capacitor C 2 and the resistor R 1 is provided between the drain and the source of the switching element Q 2 . Hence, a gate voltage V G of the switching element Q 1 is changed depending on a time constant (τ=C×R) of a CR circuit that is composed of a parallel connection of the capacitor C 1 and the capacitor C 2 and the resistor R 1 . More specifically, a gate voltage V G of the switching element Q 1 provides a transition from a voltage that has dropped by a voltage that is shared by the capacitor C 2 at a time when the switching element Q 2 is turned on to a potential of the terminal 12 , for example, ground potential, depending on a time constant of a CR circuit that is provided by a parallel connection of the capacitor C 1 and the capacitor C 2 and the resistor R 1 .

Thereby, it is possible to adjust a value of a gate voltage V G of the switching element Q 1 at a time when the switching element Q 2 is turned on and a shift thereof, by capacitance values of the capacitors C 1 and C 2 and a resistance value of the resistor R 1 .

When a gate-source voltage V GS of the switching element Q 1 is close to 0V, the switching element Q 1 is in a complete on-state and an on-resistance thereof is small. Therefore, as a gate-source voltage V GS is instantaneously changed from an off-state where a gate-source voltage V GS of the switching element Q 1 is lower than a threshold value to 0V, a change of the drain voltage V X of the switching element Q 2 is instantaneously reflected in a drain voltage V γ of the switching element Q 1 . That is, a drain voltage V γ of the switching element Q 1 is changed steeply.

On the other hand, when a gate-source voltage V GS of the switching element Q 1 is a voltage close to a threshold value, the switching element Q 1 is in a weak on-state and an on-resistance thereof is large. Adjustment is executed in such a manner that when the switching element Q 2 is turned on, a gate-source voltage V GS of the switching element Q 1 is a voltage close to a threshold value to provide a weak on-state, and a gate voltage V G of the switching element Q 1 is gently changed by a time constant of a CR circuit that is composed of a parallel connection of the capacitor C 1 and the capacitor C 2 and the resistor R 1 to change a gate-source voltage V GS of the switching element Q 1 gently and provides a gentle transition of the switching element Q 1 to a strong on-state, so that it is possible to mitigate a steep variation of a drain voltage V γ of the switching element Q 1 .

According to the present embodiment, a series circuit of the capacitor C 1 and the capacitor C 2 is provided between the source of the switching element Q 1 and the source of the switching element Q 2 and a common connection terminal thereof is connected to the gate of the switching element Q 1 , so that it is possible to adjust a gate-source voltage V GS of the switching element Q 1 at a time when the switching element Q 2 is turned on. That is, it is possible to readily adjust an on-state of the switching element Q 1 by adjustment of a gate-source voltage V GS of the switching element Q 1 .

Furthermore, a transition of a gate-source voltage V GS of the switching element Q 1 is provided according to a time constant of a CR circuit that is composed of the resistor R 1 that is connected to the gate of the switching element Q 1 , the capacitor C 1 , and the capacitor C 2 , so that it is possible to change the switching element Q 1 from a weak on-state to a strong on-state gently. Thereby, it is possible to suppress a steep variation of a drain voltage V Y of the switching element Q 1 , so that it is possible to suppress generation of unnecessary radiation that is caused at a time when the switching element Q 2 is in an on-state in response to a driving signal V D .

FIG. 2 is a diagram illustrating a characteristic of a normally-on type switching element. A characteristic of the switching element Q 1 in the first embodiment as already described is illustrated. A horizontal axis represents a gate-source voltage V GS and a vertical axis represents a drain current I D . A characteristic curve 100 is illustrated in such a manner that a drain current I D flows even when a gate-source voltage V GS is zero (0) V and a drain current I D is approximately zero (0) A at a time when a gate-source voltage V GS is a threshold value V TH that is minus.

In the first embodiment as already described, a gate-source voltage V GS of the switching element Q 1 at a time when the switching element Q 2 is turned on is adjusted by adjustment of capacitance values of the capacitor C 1 and the capacitor C 2 , so that it is possible to adjust an on-state of the switching element Q 1 . For example, adjustment is executed in such a manner that a gate-source voltage V GS of the switching element Q 1 at a time when the switching element Q 2 is turned on is a value close to a threshold value V TH , so that it is possible to transfer the switching element Q 1 to a weak on-state.

FIG. 3 is a diagram illustrating a result of simulation. A driving signal V D that is applied to the gate of the switching element Q 2 , a drain voltage V X of the switching element Q 2 , a gate voltage V G of the switching element Q 1 , and a drain voltage V Y of the switching element Q 1 are illustrated from an upper side.

As a driving signal V D is High at timing t 0 , the switching element Q 2 is turned on and a drain voltage V X falls steeply. A gate voltage V G also falls. Therefore, in a case where, for example, ground potential is applied to the terminal 12 that is connected to the source of the switching element Q 2 , a gate voltage V G is a negative voltage.

In a configuration to divide a drain voltage V X of the switching element Q 2 by a series connection of the capacitor C 1 and the capacitor C 2 , a capacitance ratio between the capacitor C 1 and the capacitor C 2 is adjusted appropriately, so that it is possible to readily execute adjustment to raise a gate voltage V G of the switching element Q 1 at a time when the switching element Q 2 is turned on from a voltage V G1 to a voltage V G2 , as indicated by a broken ellipse 101 .

A value of a voltage V G2 is set at, for example, a voltage close to a threshold value V TH of the switching element Q 1 , so that it is possible to provide a weak on-state of the switching element Q 1 immediately after the switching element Q 2 is turned on. A gate voltage V G of the switching element Q 1 provides a transition to a potential of the terminal 12 , that is, ground potential according to a time constant of a CR circuit that is connected to the gate of the switching element Q 1 and composed of the resistor R 1 , the capacitor C 1 , and the capacitor C 2 .

The switching element Q 1 is gently transferred from a weak on-state to a strong on-state according to a CR time constant, so that a steep change of a drain voltage V Y of the switching element Q 1 at a time when the switching element Q 2 is turned on is suppressed. That is, it is possible to mitigate a change (dV Y /dt) of a drain voltage V Y of the switching element Q 1 , as indicated by a dashed ellipse 102 , relative to a change of a drain voltage V X of the switching element Q 2 that responds to a driving signal V D that is applied to the gate of the switching element Q 2 . Thereby, a steep voltage variation of a wiring that is connected to the drain of the switching element Q 1 is suppressed, so that generation of unnecessary radiation is suppressed.

As a driving signal V D is Low at timing t 1 , the switching element Q 2 is turned off, so that a drain voltage V X of the switching element Q 2 and a drain voltage V Y of the switching element Q 1 rise.

Second Embodiment

FIG. 4 is a diagram illustrating a semiconductor integrated circuit according to a second embodiment. A component that corresponds to that of the embodiment as already described is provided with an identical sign and a redundant description is provided only in case of need. Hereinafter, the same applies.

In the present embodiment, a parasitic capacitor Cp of the switching element Q 1 is used as a capacitor that is connected to the capacitor C 1 in series.

In the present embodiment, a gate voltage V G of the switching element Q 1 at a time when the switching element Q 2 is turned on is adjusted by a capacitance ratio between the capacitor C 1 that is connected to the resistor R 1 in parallel and the parasitic capacitor Cp.

A gate voltage V G of the switching element Q 1 at a time when the switching element Q 2 is turned on is adjusted by setting of a capacitance ratio between the capacitor C 1 and the parasitic capacitor Cp to adjust a gate-source voltage V GS of the switching element Q 1 , so that it is possible to adjust an on-state of the switching element Q 1 . For example, adjustment is executed in such a manner that a gate-source voltage V GS of the switching element Q 1 at a time when the switching element Q 2 is turned on is a value close to a threshold value V TH , so that it is possible to execute adjustment to provide a weak on-state of the switching element Q 1 .

Furthermore, a gentle transition of a gate voltage V G of the switching element Q 1 is provided according to a time constant of an CR circuit that is composed of the resistor R 1 , the capacitor C 1 , and the parasitic capacitor Cp, so that it is possible to transfer the switching element Q 1 from a weak on-state to a strong on-state gently. Thereby, a steep change of a drain voltage V Y of the switching element Q 1 a time when the switching element Q 2 is turned on is suppressed, so that a steep voltage variation of a wiring that is connected to the drain of the switching element Q 1 is suppressed and generation of unnecessary radiation is suppressed.

Third Embodiment

FIG. 5 is a diagram illustrating a semiconductor integrated circuit according to a third embodiment. In the present embodiment, a variable resistor R 11 is connected between the gate of the switching element Q 1 and the source of the switching element Q 2 and a variable capacitor C 11 is connected to the variable resistor R 11 in parallel.

Values of a resistance of the variable resistor R 11 and a capacitance of the variable capacitor C 11 are controlled by a control signal from a control circuit 1 . It is possible to provide the variable resistor R 11 with, for example, a configuration to connect parallel connections of a (non-illustrated) resistor and a (non-illustrated) switch at multistage and in series, control on/off of such a switch by a control signal from the control circuit 1 , and change the number of resistors that are connected in series. That is, a resistance value of the variable resistor R 11 is associated with the number of switches that are turned on/off according to a control signal from the control circuit 1 , so that it is possible to adjust a resistance value of the variable resistor R 11 to a desired value.

It is possible to provide the variable capacitor C 11 with, for example, a configuration to connect serial connections of a (non-illustrated) capacitor and a (non-illustrated) switch at multistage and in parallel, control on/off of such a switch by a control signal from the control circuit 1 , and change the number of capacitors that are connected in parallel. That is, a capacitance value of the variable capacitor C 11 is associated with the number of switches that are turned on/off according to a control signal from the control circuit 1 , so that it is possible to adjust a capacitance value of the variable capacitor C 11 to a desired value.

Predetermined voltages are applied to the terminal 11 and the terminal 12 . For example, 600V is applied to the terminal 11 , and for example, ground potential is applied to the terminal 12 . A driving signal V D from the control circuit 1 is supplied to the terminal 10 .

A drain voltage V X of the switching element Q 2 and a gate voltage V G of the switching element Q 1 are supplied to an operation processing circuit 2 . The operation processing circuit 2 calculates a gate-source voltage V GS of the switching element Q 1 based on values of a drain voltage V X of the switching element Q 2 and a gate voltage V G of the switching element Q 1 at a time when a driving signal V D is High. For example, a calculated gate-source voltage V GS is compared with a value that is preliminarily stored in the operation processing circuit 2 as a desired gate-source voltage V GS and an instruction value to change a resistance value of the variable capacitor C 11 in such a manner that a gate-source voltage V GS of the switching element Q 1 at a time when a driving signal V D is High is a desired gate-source voltage V GS is supplied to the control circuit 1 . For a gate-source voltage V GS of the switching element Q 1 at a time when a driving signal V D that is supplied to the gate of the switching element Q 2 is High, that is, a time when the switching element Q 2 is turned on, it is possible to provide any value between a voltage value provided by inverting a sign of a maximum value of a preliminarily stored drain voltage V X and 0V. For example, it is possible to adjust a gate-source voltage V GS of the switching element Q 1 at a time when the switching element Q 2 is turned on to any value between a value near a threshold value that is slightly less than the threshold value and 0V. It is possible to provide the operation processing circuit 2 with a configuration to install a program that is based on a variety of control algorithms that define timing of application of a driving signal V D to the switching element Q 2 , timing of changing of a resistance value of the variable resistor R 11 or a capacitance value of the variable capacitor C 11 , and the like.

The control circuit 1 changes a capacitance value of the variable capacitor C 11 by a control signal CT 2 to control a capacitance value of the variable capacitor C 11 in response to an instruction value from the operation processing circuit 2 . In such a configuration, it is possible to adjust a gate-source voltage V GS of the switching element Q 1 at a time when the switching element Q 2 is turned on to a desired value by capacitance values of the variable capacitor C 11 and the capacitor C 2 .

Furthermore, the operation processing circuit 2 supplies an instruction value to change a resistance value of the variable resistor R 11 to the control circuit 1 . A resistance value of the variable resistor R 11 is adjusted by the control circuit 1 , so that it is possible to adjust a time constant of a CR circuit that is composed of a parallel circuit of the variable resistor R 11 , the variable capacitor C 11 , and the capacitor C 2 . A time constant is adjusted, so that it is possible to adjust a transition of a gate-source voltage V GS of the switching element Q 1 , that is, a period of time when a transition of a gate voltage V G immediately after the switching element Q 2 is turned on to a voltage of the terminal 12 is provided.

For example, as a time constant is increased, a period of time when a gate voltage V G reaches a voltage of the terminal 12 is increased, so that a period of time until the switching element Q 1 turns into an on-state completely is increased. That is, it is possible to mitigate a change of a drain voltage V Y of the switching element Q 1 .

The operation processing circuit 2 supplies, for example, an instruction value to change a resistance value of the variable resistor R 11 depending on a change of a capacitance value of the variable capacitor C 11 , to the control circuit 1 . For example, an instruction value to change a resistance value of the variable resistor R 11 in such a manner that time constants of a CR circuit that is composed of the variable resistor R 11 , the variable capacitor C 11 , and the capacitor C 2 before and after a capacitance value of the variable capacitor C 11 is changed are identical is supplied to the control circuit 1 . Alternatively, a time constant that is provided by the variable resistor R 11 , the variable capacitor C 11 , and the capacitor C 2 after a capacitance value of the variable capacitor C 11 is changed may be compared with a setting value that is stored in the operation processing circuit 2 as a preliminarily desired value of a time constant and an instruction value to change a resistance value of the variable resistor R 11 in such a manner that the time constant that is provided by the variable resistor R 11 , the variable capacitor C 11 , and the capacitor C 2 is such a desired value of a time constant may be supplied to the control circuit 1 . The control circuit 1 changes a resistance value of the variable resistor R 11 by a control signal CT 1 to change a resistance value of the variable resistor R 11 in response to an instruction value from the operation processing circuit 2 .

Additionally, the capacitor C 2 may be composed of a variable capacitor. As the capacitor C 2 is a variable capacitor, a degree of freedom of setting of a capacitance ratio between the capacitor C 2 and the variable capacitor C 11 is increased, so that it is possible to improve a degree of freedom at a time when a gate voltage V G of the switching element Q 1 is adjusted.

FIG. 6 is a diagram for explaining an adjustment method for a semiconductor integrated circuit where a gate voltage V G of the switching element Q 1 is illustrated schematically. An adjustment method in FIG. 6 is used for, for example, adjustment of a gate-source voltage V GS of the switching element Q 1 in the embodiment as illustrated in FIG. 5 .

It is possible to adjust a value of a gate voltage V G at a time when a driving signal V D is High by setting of a capacitance ratio between the variable capacitor C 11 and the capacitor C 2 . That is, it is possible to adjust a gate voltage V G from a transition according to a dashed-dotted line 103 to a transition as indicated by a solid line 104 . Specifically, a capacitance value of the variable capacitor C 11 relative to that of the capacitor C 2 is increased. A voltage that is shared by the capacitor C 2 at a time when the switching element Q 2 is turned on is decreased, so that it is possible to execute adjustment to raise a value of a gate voltage V G of the switching element Q 1 from the voltage V G1 to the voltage V G2 .

A gate voltage V G of the switching element Q 1 at a time when the switching element Q 2 is turned on is adjusted by a ratio between capacitance values of the variable capacitor C 11 and the capacitor C 2 to adjust a gate-source voltage V GS of the switching element Q 1 , so that it is possible to adjust an on-state of the switching element Q 1 at the time when the switching element Q 2 is turned on.

Specifically, as a gate-source voltage V GS of the switching element Q 1 is higher than a threshold value V TH and is a value close to the threshold value V TH , so that it is possible to provide a weak on-state of the switching element Q 1 at a time when the switching element Q 2 is turned on. Additionally, “higher than a threshold value V TH ” as mentioned herein means that the switching element Q 1 is a normally-on type and such a threshold value V TH is a negative voltage, so that a value of a voltage on a plus side of a threshold value V TH is provided.

Fourth Embodiment

FIG. 7 is a diagram illustrating a flowchart of an adjustment method for a semiconductor integrated circuit. For example, it is used in the embodiment as illustrated in FIG. 5 . The variable resistor R 11 and the variable capacitor C 11 are set at initial values (step S 101 ). The capacitor C 2 has a fixed capacitance.

Whether or not a gate-source voltage V GS of the switching element Q 1 at a time of driving of the switching element Q 1 , that is, a time when a driving signal V D that is applied to the gate of the switching element Q 2 is High is within a desired value range is determined (step S 102 ). For example, it is possible to detect a gate-source voltage V GS of the switching element Q 1 from values of a drain voltage V X of the switching element Q 2 and a gate voltage V G of the switching element Q 1 at a time when a driving signal V D that is applied to the gate of the switching element Q 2 is High.

For example, whether or not a gate-source voltage V GS of the switching element Q 1 is within a desired range between a threshold value V TH and 0V is determined. In a case where a gate-source voltage V GS of the switching element Q 1 is not a value between a threshold value V TH and 0V and is not within a desired value range (step S 102 : No), a capacitance value of the variable capacitor C 11 is changed (step S 103 ). Application of a driving signal V D , detection of a gate-source voltage V GS of the switching element Q 1 , and a change of a capacitance value of the variable capacitor C 11 based on a result of such detection are executed so that a capacitance value of the variable capacitor C 11 is changed until the gate-source voltage V GS of the switching element Q 1 at a time when the driving signal V D is High falls within a desired range. Additionally, a case where a gate-source voltage V GS is not within a desired range is, for example, a case where a gate voltage V G of the switching element Q 1 at a time when the switching element Q 2 is turned on falls and a gate-source voltage V GS is lower than a value of a threshold value V TH . Additionally, “lower than a threshold value V TH ” as mentioned herein means that the switching element Q 1 is a normally-on type and such a threshold value V TH is a negative voltage, so that a value of a voltage on a minus side of the threshold value V TH is provided.

In a case where a gate-source voltage V GS of the switching element Q 1 at a time when a driving signal V D is High is within a desired range (step S 102 : Yes), whether or not a time constant that is provided by the variable resistor R 11 , the variable capacitor C 11 , and the capacitor C 2 is within a desired range is determined (step S 104 ). As a time constant is increased, a change of a gate-source voltage V GS is gentle, so that it is possible to turn on the switching element Q 1 gently in a case where a driving signal V D is changed from Low to High and it is possible to suppress generation of unnecessary radiation that is caused by a steep change of a drain voltage V Y of the switching element Q 1 .

On the other hand, as a time constant is increased, an operation speed of a semiconductor integrated circuit falls. Therefore, it is possible to suppress generation of unnecessary radiation that is involved with a steep change of a drain voltage V Y of the switching element Q 1 and set a desired time constant by taking an operation speed of a semiconductor integrated circuit into consideration. A resistance value of the variable resistor R 11 may be changed so as to provide an initially set time constant depending on a change of a capacitance value of the variable capacitor C 11 .

Additionally, in a case where a driving signal V D that is applied to the gate of the switching element Q 2 is switched from High to Low, that is, a case where the switching element Q 2 is switched from on to off, adjustment to decrease a resistance value of the variable resistor R 11 so as to decrease a time constant may be executed. As a time constant is decreased, it is possible to decrease a delay of a change of a drain voltage V Y of the switching element Q 1 , that is, a delay of an operation of the switching element Q 1 .

That is, when the switching element Q 2 is turned on, a resistance value of the variable resistor R 11 is increased to increase a time constant, and when the switching element Q 2 is turned off, a resistance value of the variable resistor R 11 is decreased to decrease a time constant, so that it is possible to provide a configuration to suppress a steep variation of a drain voltage V Y of the switching element Q 1 at a time when the switching element Q 2 is turned on so as to suppress generation of unnecessary radiation and to decrease a delay of an operation of the switching element Q 1 at a time when the switching element Q 2 is turned off.

Additionally, it is possible to execute control to increase a resistance value of the variable resistor R 11 , for example, at any timing immediately after a gate-source voltage V GS of the switching element Q 1 is greater than a threshold value V TH to provide an off-state of the switching element Q 1 and immediately before the switching element Q 1 is in an on-state.

Furthermore, it is possible to execute control to decrease a resistance value of the variable resistor R 11 , for example, at any timing immediately after a gate-source voltage V GS of the switching element Q 1 is 0V to provide a complete on-state of the switching element Q 1 and immediately before the switching element Q 1 is in an off-state.

In a case where a time constant that is provided by the variable resistor R 11 , the variable capacitor C 11 , and the capacitor C 2 is within a desired range (step S 104 : Yes), ending is executed. In a case where it is not within a desired range (step S 104 : No), an operation to change a resistance value of the variable resistor R 11 is continued (step S 105 ).

Due to an adjustment method according to the present embodiment, a gate voltage V G of the switching element Q 1 at a time when the switching element Q 2 is turned on is adjusted by adjustment of capacitance values of the variable capacitor C 11 and the capacitor C 2 , therefore, a gate-source voltage V GS is adjusted, and a resistance value of the variable resistor R 11 is further adjusted, so that it is possible to adjust a time constant of a CR circuit that is composed of the variable resistor R 11 , the variable capacitor C 11 , and the capacitor C 2 to a desired value. Thereby, it is possible to readily execute adjustment to gently change the switching element Q 1 at a time when the switching element Q 2 is turned on from a weak on-state to a strong on-state. Thereby, a steep change of a drain voltage V Y of the switching element Q 1 is suppressed, so that it is possible to readily execute adjustment to suppress generation of unnecessary radiation. Furthermore, it is also possible to readily execute adjustment of a delay of an operation of the switching element Q 1 at a time when the switching element Q 2 is switched from an on-state to an off-state by adjustment of a time constant of a CR circuit that is composed of the variable resistor R 11 , the variable capacitor C 11 , and the capacitor C 2 .

Additionally, the normally-on type switching element Q 1 according to the embodiment as already described may be composed of a Junction Field Effect Transistor (JFET).

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.