Comparator circuit

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-011215, filed on Jan. 25, 2019; the entire contents of which are incorporated herein by reference.

The present embodiment generally relates to a comparator circuit.

A variety of techniques that deal with characteristic degradation that is caused by Negative Bias Temperature Instability (NBTI) in a comparator circuit that uses PMOS transistors as a differential pair are disclosed conventionally. In a PMOS transistor, NBTI causes characteristic degradation that causes a threshold value to vary in a state where a drain voltage is higher than a gate voltage. Hence, a comparator circuit is desired that is capable of suppressing a rise in a drain voltage of a PMOS transistor and readily avoiding transferring to NBTI.

FIG. 1 is a diagram illustrating a comparator circuit according to a first embodiment.

FIG. 2 is a diagram illustrating a comparator circuit according to a second embodiment.

FIG. 3 is a diagram illustrating a comparator circuit according to a third embodiment.

According to one embodiment, a comparator circuit includes first and second PMOS transistors that compose a differential pair, a first switching transistor with a main current path that is connected between an input terminal and a gate of the first PMOS transistor, a voltage source that applies a reference voltage to a gate of the second PMOS transistor, and a first bias circuit that applies a first bias voltage to a control electrode of the first switching transistor.

Hereinafter, a comparator circuit according to embodiments will be explained in detail with reference to the accompanying drawings. Additionally, the present invention is not limited by such embodiments.

First Embodiment

FIG. 1 is a diagram illustrating a comparator circuit according to a first embodiment. In the first embodiment, for example, a case where an input voltage Vin is lower than a reference voltage Vref is detected as abnormality. A comparator circuit 1 has PMOS transistors M 1 and M 2 that compose a differential pair. Sources of the PMOS transistors M 1 and M 2 are commonly connected to one terminal of a current source 12 . The other terminal of the current source 12 is connected to a power source line 11 . A gate of the PMOS transistor M 1 is connected to an input terminal 100 where an input voltage Vin is applied thereto via an NMOS transistor M 5 . A gate of the PMOS transistor M 2 is connected to a reference voltage source 3 that supplies a reference voltage Vref thereto.

A source-drain path of the NMOS transistor M 5 that is a main current path is connected between the input terminal 100 and the gate of the PMOS transistor M 1 . A drain of the NMOS transistor M 5 is connected to the input terminal 100 and a source thereof is connected to the gate of the PMOS transistor M 1 . A bias voltage V 1 is applied to a gate of the NMOS transistor M 5 by a bias circuit 20 .

The bias circuit 20 has a diode-connected NMOS transistor M 6 . A drain and a gate of the NMOS transistor M 6 are connected to one terminal of a constant current source 21 and a source thereof is connected to a reference voltage source 3 . The other terminal of the constant current source 21 is connected to the power source line 11 . A gate voltage of the NMOS transistor M 6 is a voltage that is higher than a reference voltage Vref by a gate-source voltage Vgs of the NMOS transistor M 6 . Therefore, a bias voltage V 1 is Vref+Vgs.

It has an NMOS transistor M 3 with a source-drain path that is a main current path that is connected between a drain of the PMOS transistor M 1 and ground. The NMOS transistor M 3 composes diode connection where a drain and a gate thereof are commonly connected.

It has an NMOS transistor M 4 with a source-drain path that is a main current path that is connected between a drain of the PMOS transistor M 2 and ground. A gate of the NMOS transistor M 4 is connected to a gate of the NMOS transistor M 3 . The NMOS transistors M 3 and M 4 compose a current mirror circuit.

A connection point between the PMOS transistor M 2 and the NMOS transistor M 4 is connected to an output terminal 200 . The output terminal 200 outputs an output voltage Vout 1 .

An operation is as follows. An input voltage Vin is applied to a gate of the PMOS transistor M 1 via the source-drain path of the NMOS transistor M 5 . In a steady state, that is, a state where an input voltage Vin is higher than a reference voltage Vref, the PMOS transistor M 2 is in an on-state and an output voltage Vout 1 is High.

As an input voltage Vin rises to be higher than Vref+Vgs−Vth(M 5 ), the NMOS transistor M 5 is in an off-state. Herein, Vth(M 5 ) represents a threshold value of the NMOS transistor M 5 .

As the NMOS transistor M 5 is turned off, an input voltage Vin is not applied to the gate of the PMOS transistor M 1 . That is, it is possible to restrict an upper limit value of a voltage that is applied to the gate of the PMOS transistor M 1 , by a value of a bias voltage V 1 . In other words, the NMOS transistor M 5 functions as a switch that restricts a voltage that is applied to the gate of the PMOS transistor M 1 , depending on a value of a bias voltage V 1 . It is possible to restrict a voltage difference between the gates of the PMOS transistors M 1 and M 2 and thereby execute control in such a manner that the PMOS transistor M 2 is not completely in an on-state.

The PMOS transistor M 2 avoids a state where it is completely turned on, so that a rise in a drain voltage is suppressed. Thereby, it is possible for the PMOS transistor M 2 to avoid a drain voltage that is higher than a gate voltage, so that it is possible to avoid transferring to an NBTI state.

As an input voltage Vin falls to be lower than Vref+Vgs−Vth(M 5 ), the NMOS transistor M 5 is in an on-state. As the NMOS transistor M 5 is turned on, an input voltage Vin is applied to the gate of the PMOS transistor M 1 .

The PMOS transistor M 1 is turned on as a gate voltage thereof is lower than a reference voltage Vref. Thereby, gate voltages of the NMOS transistors M 3 and M 4 rise to cause turning on thereof. As the NMOS transistor M 4 is turned on, an output voltage Vout is Low. That is, an output voltage Vout that is Low is detected, so that it is possible to detect an abnormal state where an input voltage Vin is lower than a reference voltage Vref.

A drain voltage of the PMOS transistor M 1 at a time of turning on is a gate-source voltage of the diode-connected NMOS transistor M 3 . Thereby, when the PMOS transistor M 1 is turned on, a state where a drain voltage is higher than a gate voltage is avoided, so that it is possible to avoid transferring to an NBTI state.

It is possible to appropriately set a bias voltage V 1 at a value in such a manner that the PMOS transistor M 2 is not in a complete on-state. A highest voltage that is applied to the gate of the PMOS transistor M 1 is restricted to be a voltage that is lower than a bias voltage V 1 by a threshold value Vth(M 5 ) of the NMOS transistor M 5 . That is, it is restricted by Vref+Vgs−Vth(M 5 ).

For example, as a voltage that corresponds to Vgs in a bias voltage V 1 is raised, an upper limit value of a voltage that is applied to the gate of the PMOS transistor M 1 is raised. An on-state of the PMOS transistor M 2 is controlled by a difference between a reference voltage Vref and a voltage that is applied to the gate of the PMOS transistor M 1 . Therefore, it is possible to provide a configuration to adjust a bias voltage V 1 appropriately in such a manner that the PMOS transistor M 2 is not tuned on completely. It is possible to readily adjust Vgs in a bias voltage V 1 by, for example, a dimension of the NMOS transistor M 6 or a current value of the constant current source 21 .

A bias voltage V 1 is set at, for example, a value in such a manner that the NMOS transistor M 5 is in an on-state even when an input voltage Vin is equal to a reference voltage Vref. Thereby, it is possible to compare a magnitude relationship between an input voltage Vin and a reference voltage Vref accurately. Specifically, a bias voltage V 1 is set so as to be greater than or equal to a voltage provided by adding a threshold value Vth(M 5 ) of the NMOS transistor M 5 to a reference voltage Vref.

According to the first embodiment, it includes the NMOS transistor M 5 that functions as a switch that restricts an upper limit value of a voltage that is applied to the gate of the PMOS transistor M 1 , by a bias voltage V 1 that is set by the bias circuit 20 . Thereby, a rise in a drain voltage of the PMOS transistor M 2 is suppressed, so that it is possible to readily avoid transferring to an NBTI state in a steady state where an input voltage Vin is higher than a reference voltage Vref. Furthermore, in a case where an input voltage Vin is lower than a reference voltage Vref and the PMOS transistor M 1 is in an on-state, a rise in a drain voltage of the PMOS transistor M 1 is suppressed, so that it is possible to avoid being in an NBTI state.

That is, in an active state where an operation of comparison between an input voltage Vin and a reference voltage Vref is executed, it is possible to readily avoid being in an NBTI state for any of the PMOS transistors M 1 and M 2 that are in on-states and it is possible to provide the comparator circuit 1 with high reliability.

An output voltage Vout 1 indicates High that corresponds to a drain voltage of the PMOS transistor M 2 at a time of an on-state or Low that corresponds to a voltage that is substantially equal to a ground potential at a time when the NMOS transistor M 4 is in an on-state. Hence, a dynamic range of an output voltage Vout 1 is wide.

Second Embodiment

FIG. 2 is a diagram illustrating a comparator circuit according to a second embodiment. A component that corresponds to that of the embodiment as already described will be provided with an identical sign and a redundant description will be provided only in case of need. Hereinafter, the same applies. In the second embodiment, a state where an input voltage Vin is higher than a reference voltage Vref is detected as a state where abnormality is caused.

A comparator circuit 2 has PMOS transistors M 11 and M 12 that compose a differential pair. Sources of the PMOS transistors M 11 and M 12 are commonly connected to one terminal of a current source 14 . The other terminal of the current source 14 is connected to a power source line 11 . A gate of the PMOS transistor M 11 is connected to an input terminal 100 where an input voltage Vin is applied thereto via a PMOS transistor M 7 . A gate of the PMOS transistor M 12 is connected to a reference voltage source 13 that supplies a reference voltage Vref thereto.

A source-drain path of the PMOS transistor M 7 that is a main current path is connected between the input terminal 100 and the gate of the PMOS transistor M 11 . A drain of the PMOS transistor M 7 is connected to the input terminal 100 and a source thereof is connected to the gate of the PMOS transistor M 11 . A bias voltage V 2 is applied to a gate of the PMOS transistor M 7 by a bias circuit 30 .

The bias circuit 30 has a diode-connected PMOS transistor M 8 . A drain and a gate of the PMOS transistor M 8 are connected to one terminal of a constant current source 31 and a source thereof is connected to a reference voltage source 13 . The other terminal of the constant current source 31 is grounded. A gate voltage of the PMOS transistor M 8 is a voltage that is lower than a reference voltage Vref by a gate-source voltage Vgs of the PMOS transistor M 8 . Therefore, a bias voltage V 2 is Vref−Vgs.

It has an NMOS transistor M 13 with a source-drain path that is a main current path that is connected between a drain of the PMOS transistor M 11 and ground.

It has an NMOS transistor M 14 with a source-drain path that is a main current path that is connected between a drain of the PMOS transistor M 12 and ground. The NMOS transistor M 14 composes diode connection where a drain and a gate thereof are commonly connected. A gate of the NMOS transistor M 14 is connected to a gate of the NMOS transistor M 13 . The NMOS transistors M 13 and M 14 compose a current mirror circuit.

A connection point between the PMOS transistor M 11 and the NMOS transistor M 13 is connected to an output terminal 201 . The output terminal 201 outputs an output voltage Vout 2 .

As a gate-source voltage of the PMOS transistor M 8 is Vgs and a reference voltage Vref is supplied by the reference voltage source 13 , a bias voltage V 2 that is supplied to the gate of the PMOS transistor M 7 is represented by Vref−Vgs.

An operation is as follows. In a steady state, a state where an input voltage Vin is lower than a reference voltage Vref is provided. In such a state, the PMOS transistor M 11 is in an on-state and an output voltage Vout 2 indicates High.

As an input voltage Vin falls and a voltage difference between a bias voltage V 2 (=Vref−Vgs) that is applied to the gate of the PMOS transistor M 7 and a source voltage of the PMOS transistor M 7 is less than a threshold value Vth(M 7 ) of the PMOS transistor M 7 , the PMOS transistor M 7 is turned off. As the PMOS transistor M 7 is turned off, an input voltage Vin is not applied to the gate of the PMOS transistor M 11 . That is, it is possible to restrict a lower limit of a voltage that is applied to the gate of the PMOS transistor M 11 , by a bias voltage V 2 .

In other words, the PMOS transistor M 7 functions as a switch that restricts a voltage that is applied to the gate of the PMOS transistor M 11 , depending on a value of a bias voltage V 2 . It is possible to restrict a voltage difference between gates of the PMOS transistors M 11 and M 12 and thereby execute control in such a manner that the PMOS transistor M 11 is not completely in an on-state.

The PMOS transistor M 11 avoids a state where it is completely turned on, so that a rise in a drain voltage is suppressed. Thereby, it is possible for the PMOS transistor M 11 to avoid a drain voltage that is higher than a gate voltage, so that it is possible to avoid transferring to an NBTI state.

As an input voltage Vin rises and a gate voltage of the PMOS transistor M 11 is higher than a reference voltage Vref, the PMOS transistor M 12 is turned on. As the PMOS transistor M 12 is turned on, a gate voltage of the NMOS transistor M 14 rises and the NMOS transistors M 13 and M 14 are turned on. Thereby, an output voltage Vout 2 is Low. As an output voltage Vout 2 is Low, it is possible to detect an abnormal state where an input voltage Vin is higher than a reference voltage Vref.

A drain voltage of the PMOS transistor M 12 at a time of turning on is a gate-source voltage of the diode-connected NMOS transistor M 14 . Thereby, when the PMOS transistor M 12 is turned on, a state where a drain voltage is higher than a gate voltage is avoided, so that it is possible to avoid transferring to an NBTI state.

It is possible to appropriately set a bias voltage V 2 at a value in such a manner that the PMOS transistor M 11 is not in a complete on-state. A lowest voltage that is applied to the gate of the PMOS transistor M 11 is restricted to be a voltage that is higher than a bias voltage V 2 by a threshold value Vth(M 7 ) of the PMOS transistor M 7 . That is, it is restricted by Vref−Vgs+Vth(M 7 ).

For example, as a voltage that corresponds to Vgs in a bias voltage V 2 is raised, a lower limit value of a voltage that is applied to the gate of the PMOS transistor M 11 is lowered. An on-state of the PMOS transistor M 11 is controlled by a difference between a reference voltage Vref and a voltage that is applied to the gate of the PMOS transistor M 11 . Therefore, it is possible to provide a configuration to adjust a bias voltage V 2 appropriately in such a manner that the PMOS transistor M 11 is not tuned on completely. It is possible to readily adjust Vgs in a bias voltage V 2 by, for example, a dimension of the PMOS transistor M 8 or a current value of the constant current source 31 .

A bias voltage V 2 is set at, for example, a value in such a manner that the PMOS transistor M 7 is in an on-state even when an input voltage Vin is equal to a reference voltage Vref. Thereby, it is possible to compare a magnitude relationship between an input voltage Vin and a reference voltage Vref accurately. Specifically, a bias voltage V 2 is set so as to be less than or equal to a voltage provided by subtracting a threshold value Vth(M 7 ) of the PMOS transistor M 7 from a reference voltage Vref.

According to the second embodiment, it includes the PMOS transistor M 7 that functions as a switch that restricts a lower limit value of a voltage that is applied to the gate of the PMOS transistor M 11 , by a bias voltage V 2 that is set by the bias circuit 30 . Thereby, a rise in a drain voltage of the PMOS transistor M 11 is suppressed, so that it is possible to readily avoid transferring to an NBTI state in a steady state where an input voltage Vin is lower than a reference voltage Vref.

Furthermore, in a case where an input voltage Vin is higher than a reference voltage Vref and the PMOS transistor M 12 is in an on-state, a rise in a drain voltage of the PMOS transistor M 12 is suppressed, so that it is possible to avoid being in an NBTI state.

That is, in an active state where an operation of comparison between an input voltage Vin and a reference voltage Vref is executed, it is possible to avoid being in an NBTI state for any of the PMOS transistors M 11 and M 12 that are in on-states and it is possible to provide the comparator circuit 2 with high reliability.

An output voltage Vout 2 indicates High that corresponds to a drain voltage of the PMOS transistor M 11 at a time of an on-state or Low that corresponds to a voltage that is substantially equal to a ground potential at a time when the NMOS transistor M 13 is in an on-state. Hence, a dynamic range of an output voltage Vout 2 is wide.

Third Embodiment

FIG. 3 is a diagram illustrating a comparator circuit according to a third embodiment. The present embodiment includes the comparator circuit 1 according to the first embodiment and the comparator circuit 2 according to the second embodiment as already described. Configurations and operations of the respective comparator circuits 1 and 2 are as already described.

An output voltage Vout 1 of the comparator circuit 1 is Low in a state where a voltage that is applied to the gate of the PMOS transistor M 1 is lower than a reference voltage Vref. Specifically, as an input voltage Vin is lower than a voltage provided by subtracting a threshold value Vth(M 5 ) of the NMOS transistor M 5 from a bias voltage V 1 , an output voltage Vout 1 is Low.

On the other hand, an output voltage Vout 2 of the comparator circuit 2 is Low in a state where an input voltage Vin is higher than a reference voltage Vref. Specifically, as an input voltage Vin is higher than a voltage provided by adding a threshold value Vth(M 7 ) of the PMOS transistor M 7 to a bias voltage V 2 , an output voltage Vout 2 is Low.

Therefore, as bias voltages V 1 and V 2 are adjusted appropriately, it is possible to set a state where both output voltages Vout 1 and Vout 2 indicate Low in a range of ±ΔV centered at a reference voltage Vref. Thereby, it is possible to provide a configuration of a window comparator circuit to detect that an input voltage Vin is within a predetermined range with respect to a reference voltage Vref. Additionally, +ΔV represents a difference between Vgs and a threshold value Vth(M 5 ) of the NMOS transistor M 5 in the bias circuit 20 and −ΔV corresponds to a difference between Vgs and a threshold value Vth(M 7 ) of the PMOS transistor M 7 in the bias circuit 30 .

According to the third embodiment, when both output voltages Vout 1 and Vout 2 are Low, that is, both output voltages Vout 1 and Vout 2 are High, a window comparator circuit is configured to detect that an input voltage Vin is within a predetermined range centered at a reference voltage Vref.

It is possible for the respective comparator circuits 1 and 2 to readily avoid transferring to NBTI states at a time when the PMOS transistors M 1 and M 2 and M 11 and M 12 in the respective differential pairs are in on-sates in an active state where an operation of comparison between an input voltage Vin and a reference voltage Vref is executed, by adjustment of bias voltages V 1 and V 2 . Hence, it is possible to prevent characteristic degradation that is involved with a variation of a threshold value, so that it is possible to provide a window comparator circuit with high reliability.

Additionally, a range of an input voltage Vin may appropriately be set by appropriately adjusting reference voltages Vref of the comparator circuit 1 and the comparator circuit 2 to be different voltage values.

Furthermore, output voltages Vout 1 and Vout 2 may be supplied to an AND circuit (non-illustrated) and an input voltage Vin that is within a predetermined range at a time when an output signal of such an AND circuit is Low may be detected.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.