Charge-based charge pump with wide output voltage range

The present disclosure relates to a charge pump, and more particularly to a charge-based charge pump (CBCP), with wide output voltage range (from −0.84·VDD to 1.82·VDD), for wide tuning range frequency synthesizer applications. It can be utilized for multiple applications requiring negative or higher-than-supply positive bias potential.

Conventionally, the charge pump used within a frequency synthesizer (PLL), includes a pair of current mirror device, which is in response to a trigger input by the incoming up or down pulse signal, source or sink a fixed magnitude of current into the loop filter. This charge pump is widely employed in all analog PLL implementations due to its linear characteristics and low noise performance. However, the performance of this charge pump is affected by a wide range of inherent nonlinearities, such as up-down current mismatch, charge injection, clock feedthrough, and require intricate layout to suppress the random mismatches between the large current mirror devices. In addition, the useable linear output voltage range is a subset of the total available range from ground (0V) to the supply potential (VDD) and is typically less than 70% of the VDD. Moreover, the cascoding implemented within the constant current branches further restricts the output voltage range and the minimum supply voltage that can be utilized.

Further to this, in a PLL environment, the current (or charge) mismatch arising from the charge pump (hereinafter referred to as “CP”) directly translates into a reference spur at the PLL output spectrum. Therefore, the conventional current mirror CP commonly employs a high-gain auxiliary feedback loop to obtain precise matching of the UP-DN current magnitude. An example of such implementation is shown in FIG. 1 (Prior Art-1). As seen from FIG. 1 , this implementation requires a rail-to-rail input/output range amplifier and comprises of replica bias paths that remain turned on, even when CP is in idle state (no UP or DN pulse input provided to the CP). Therefore, the state-of-the-art current-mirror CP implementation results in significantly increased complexity, power and area utilization.

In order to effectively suppress CP nonlinearities, a charge-based charge pump is proposed in Schober et al. [U.S. Pat. No. 8,525,564B2]. As indicated in FIG. 2 (Prior Art-2), the charge from pump capacitor, nominally charged to VDD, is shared to the load capacitor, following the trigger input by the incoming UP/DN pulse inputs. This capacitive charge re-distribution scheme results in improved matching performance and lower power consumption. However, due to the involved capacitive charge-sharing the useable linear range is even lower than the former case.

In this patent a novel charge-based charge pump architecture is proposed. The proposed CP retains all the merits of earlier charge-based charge pump, while extending the output voltage range from −0.84·VDD to 1.82·VDD. The approximated linear output voltage range also extends from ˜−0.7·VDD to ˜1.4·VDD. Such wide output voltage range can be utilized for wide tuning-range voltage-controlled oscillator (VCO)/PLL implementations. In addition, the steady-state ripple magnitude is less than 0.03% of its saturated output at −0.84·VDD/1.82·VDD, and the CP response is free from any memory effect. Thus, the proposed design can be employed for multiple applications, such as RF-Antenna switches, that can exploit the negative or higher-than-supply positive potential output from the CP.

It is an object of the present disclosure to provide a charge-based charge pump with wide output voltage range. The given charge-based charge pump powered by a standard supply potential (VDD), provides an output voltage range from −0.84·VDD to 1.82·VDD, thus extending its operation well beyond the headroom defined by input supply rails. Meanwhile, the approximated linear output voltage range extends from ˜−0.7·VDD to 1.4·VDD, thus achieving a total useable output voltage range of ˜2.1·VDD for PLL and other similar applications that operate within the linear region of the CP transfer characteristic. In addition, the charge pump transfer characteristic of the charge-based charge pump is free from any memory effect. This implies that the time lapsed to reach from one potential to another is independent of the prior state of charge pump.

In accordance with an aspect of the present disclosure, there is provided a charge-based charge pump with wide output voltage range. The charge-based charge pump includes an input supply node, a ground node at 0V, an output node, a pump capacitor, a first NMOS, a positive hold subcircuit, a first dynamic body-bias generator, a positive charge transfer subcircuit, a first static body-bias generator, a first PMOS, a negative hold subcircuit, a second dynamic body-bias generator, a negative charge transfer subcircuit, a second static body-bias generator and a digital logic circuit. The input supply node is configured for receiving an input supply voltage at a supply potential. The output node is configured for outputting an output voltage. The pump capacitor includes a top plate and a bottom plate. The first NMOS is electrically connected between the ground node and the top plate. The positive hold subcircuit is electrically connected between the input supply node and the top plate. The first dynamic body-bias generator is electrically connected with the positive hold subcircuit. The positive charge transfer subcircuit is electrically connected between the top plate and the output node. The first static body-bias generator is electrically connected with the positive charge transfer subcircuit and the top plate. The first PMOS is electrically connected between the input supply node and the bottom plate. The negative hold subcircuit is electrically connected between the ground node and the bottom plate. The second dynamic body-bias generator is electrically connected with the negative hold subcircuit. The negative charge transfer subcircuit is electrically connected between the bottom plate and the output node. The second static body-bias generator is electrically connected with the negative charge transfer subcircuit and the bottom plate. The digital logic circuit is configured to receive an up pulse signal and a down pulse signal and output a plurality of switching signals for controlling the first NMOS, the positive hold subcircuit, the first dynamic body-bias generator, the positive charge transfer subcircuit, the first static body-bias generator, the first PMOS, the negative hold subcircuit, the second dynamic body-bias generator, the negative charge transfer subcircuit and the second static body-bias generator electrically connected therewith, so as to allow the charge-based charge pump to achieve the output voltage ranging from −0.84·VDD to 1.82·VDD. When the charge-based charge pump is operating in the default state, the top plate is electrically connected to the input supply node and is isolated from the output node, and the bottom plate is electrically connected to the ground node and is isolated from the output node. When the charge-based charge pump is triggered by the up pulse signal, the top plate is isolated from the input supply node and is electrically connected to the output node, and the bottom plate is electrically connected to the input supply node and is isolated from the ground node and the output node. When the charge-based charge pump is triggered by the down pulse signal, the top plate is electrically connected to the ground node and is isolated from the input supply node and the output node, and the bottom plate is isolated from the ground node and is electrically connected to the output node.

FIG. 1 is a schematic circuit diagram illustrating a modified conventional current mirror charge pump;

FIG. 2 is a schematic circuit diagram illustrating a conventional charge-based charge pump;

FIG. 3A and FIG. 3B are schematic diagrams illustrating a charge-based charge pump according to an embodiment of the present disclosure;

FIG. 4 is a schematic oscillogram illustrating a typical output waveform of a three-state phase-frequency detector;

FIG. 5 is a schematic logic diagram of the digital logic circuit of FIG. 3B ;

FIG. 6 schematically shows the up pulse signal, the down pulse signal and the active signals of FIG. 5 in three states of the charge-based charge pump;

FIG. 7 is a schematic diagram illustrating the switched buffer of FIG. 5

FIG. 8 is a schematic oscillogram of the signals of FIG. 7 ;

FIG. 9 and FIG. 10 schematically show the up pulse signal, the down pulse signal and the corresponding active signal and switching signals when the charge-based charge pump is triggered by the up pulse signal or the down pulse signal;

FIG. 11 is a schematic circuit diagram showing the detailed components of the charge-based charge pump of the present disclosure;

FIG. 12 is a schematic diagram illustrating a typical three-state phase frequency detector and the charge-based charge pump of the present disclosure;

FIG. 13A and FIG. 13B schematically show the oscillogram of a reference input, a divider input, the up pulse signal and the down pulse signal of FIG. 12 ;

FIG. 14A is a schematic oscillogram illustrating the output voltage in response to the up pulse signal depicted in FIG. 13A and the voltage ripple of the steady output voltage;

FIG. 14B is a schematic oscillogram illustrating the output voltage in response to the down pulse signal depicted in FIG. 13B and the voltage ripple of the steady output voltage;

FIG. 15 is a schematic oscillogram combining the oscillogram of FIG. 14A and FIG. 14B ;

FIG. 16A and FIG. 16B are schematic oscillograms showing the test waveforms with a series of alternating up pulse signal and down pulse signal; and

FIG. 17A and FIG. 17B are schematic oscillograms illustrating the output voltage in response to the test waveform depicted in FIG. 16A and FIG. 16B respectively.

The present disclosure will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this disclosure are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.

FIG. 3A and FIG. 3B are schematic diagrams illustrating a charge-based charge pump according to an embodiment of the present disclosure. As shown in FIG. 3A and FIG. 3B , the charge-based charge pump includes an input supply node, a ground node (GND) at 0V, an output node 110 , a pump capacitor 101 , a first NMOS (N-type Metal-Oxide-Semiconductor) N 1 , a first PMOS (P-type Metal-Oxide-Semiconductor) P 1 , a positive hold subcircuit 102 , a negative hold subcircuit 103 , a first dynamic body-bias generator 104 , a second dynamic body-bias generator 105 , a positive charge transfer subcircuit 106 , a negative charge transfer subcircuit 107 , a first static body-bias generator 108 , a second static body-bias generator 109 and a digital logic circuit 111 . The input supply node is configured for receiving an input supply voltage at a supply potential (VDD). The output node 110 is configured for outputting an output voltage Vout, and the output node 110 is for example but not limited to connect with an output load capacitor C LOAD . The pump capacitor 101 includes a top plate 101 a and a bottom plate 101 b . The first NMOS N 1 is electrically connected between the ground node and the top plate 101 a . The positive hold subcircuit 102 is electrically connected between the input supply node and the top plate 101 a . The first dynamic body-bias generator 104 is electrically connected with the positive hold subcircuit 102 . The positive charge transfer subcircuit 106 is electrically connected between the top plate 101 a and the output node 110 . The first static body-bias generator 108 is electrically connected with the positive charge transfer subcircuit 106 and the top plate 101 a . The first PMOS P 1 is electrically connected between the input supply node and the bottom plate 101 b . The negative hold subcircuit 103 is electrically connected between the ground node and the bottom plate 101 b . The second dynamic body-bias generator 105 is electrically connected with the negative hold subcircuit 103 . The negative charge transfer subcircuit 107 is electrically connected between the bottom plate 101 b and the output node 110 . The second static body-bias generator 109 is electrically connected with the negative charge transfer subcircuit 107 and the bottom plate 101 b . The digital logic circuit 111 is electrically connected with the first NMOS N 1 , the positive hold subcircuit 102 , the first dynamic body-bias generator 104 , the positive charge transfer subcircuit 106 , the first static body-bias generator 108 , the first PMOS P 1 , the negative hold subcircuit 103 , the second dynamic body-bias generator 105 , the negative charge transfer subcircuit 107 and the second static body-bias generator 109 . The digital logic circuit 111 receives an input pulse UP and a down pulse signal DN and outputs a plurality of switching signals for controlling the generators and subcircuits electrically connected therewith. The plurality of switching signals are utilized to turn on or off the switches within the charge-based charge pump in a specific order, so that the positive or negative potential is generated on the plates of the pump capacitor 101 and is finally transferred to the output node 110 via the positive charge transfer subcircuit 106 or the negative charge transfer subcircuit 107 .

The first dynamic body-bias generator 104 dynamically generates a boosted positive potential for the PMOS devices within the positive hold subcircuit 102 . The second dynamic body-bias generator 105 dynamically generates an inverted negative potential for the NMOS devices within the negative hold subcircuit 103 . The first static body-bias generator 108 constantly provides the most positive potential for the PMOS devices within the positive charge transfer subcircuit 106 . The second static body-bias generator 109 constantly provides the most negative potential for the NMOS devices within the negative charge transfer subcircuit 107 .

The proposed charge-based charge pump (CBCP) operates in the following three modes: (1) the charge-based charge pump in default state in which no up pulse signal UP or down pulse signal DN is provided to the charge pump and the output voltage Vout remains constant; (2) the charge-based charge pump triggered by an up pulse signal UP, which results in the output voltage Vout being raised till saturating at 1.82·VDD potential; and (3) the charge-based charge pump triggered by an DN pulse signal, which results in lowering of the output voltage Vout till saturating at −0.84·VDD potential. The detailed operations of the charge-based charge pump are explained as follows.

In the default state, the positive hold subcircuit 102 connects the top plate 101 a to the input supply node, and the negative hold subcircuit 103 connects the bottom plate 101 b to the ground node. Accordingly, the pump capacitor 101 is charged to the supply potential VDD with its top plate 101 a maintained at VDD and bottom plate 101 b maintained at 0V. In addition, the top plate 101 a and the bottom plate 101 b are isolated from the output node by the positive charge transfer subcircuit 106 and the negative charge transfer subcircuit 107 respectively.

When the charge-based charge pump is triggered by the up pulse signal UP, the top plate 101 a is isolated from the input supply node by the positive hold subcircuit 102 . The bottom plate 101 b is electrically connected to the input supply node via the first PMOS P 1 . Therefore, the potential of the top plate 101 a is boosted to ˜2·VDD. This is followed by enabling the positive charge transfer subcircuit 106 , which connects the top plate 101 a to the output node 110 . As a consequence of charge transfer between the pump capacitor 101 and the load capacitor C LOAD , the output voltage Vout is raised till it saturates at a boosted potential of 1.82·VDD.

When the charge-based charge pump is triggered by the down pulse signal DN, the bottom plate 101 b is isolated from the ground node by the negative hold subcircuit 103 . The top plate 101 a is electrically connected to the ground node via the first NMOS N 1 . Therefore, the potential of the bottom plate 101 b is lowered to ˜−VDD. This is followed by configuring the negative charge transfer subcircuit 107 to connect the bottom plate 101 b to the output node 110 . The resulting charge transfer between the pump capacitor 101 and the load capacitor C LOAD , causes the output voltage Vout to be lowered till it saturates at an inverted bottom plate potential of −0.84·VDD.

The circuit level implementation of the proposed CBCP must address several design challenges associated with its operation. Firstly, in the default state, the output voltage node must remain electrically isolated from the top and bottom plate of the pump capacitor 101 and this isolation must remain effective for the complete output voltage Vout range from −0.84·VDD to 1.82·VDD. Secondly, for the up pulse signal UP, the boosted top plate potential at ˜2·VDD must remain isolated from the input supply node at VDD potential. Similarly, for the down pulse signal DN, the inverted bottom plate potential at ˜−VDD must be shielded from the gnd terminal. Thirdly, it must be ensured that all the parasitic p-n junction diodes, formed within NMOS and PMOS devices in a CMOS process, must remain reverse biased (turned off) for the complete charge pump operating range. Finally, the shoot-through current should be minimized by ensuring that all the switching events are non-overlapping and the charge redistribution is executed in a predetermined sequence.

Specific circuit design techniques, as described later, are utilized to keep all the possible p-n junctions turned off for the complete range of the operation of the charge-based charge pump. The digital logic circuit 111 generates the plurality of switching signals in the required sequence and maintains a finite time difference between any two switching events, thereby preventing any loss of charge and ensuring that the charge-based charge pump continues to operate with high charge-transfer efficiency.

FIG. 4 is a schematic oscillogram illustrating a typical output waveform of a three-state phase-frequency detector. FIG. 5 is a schematic logic diagram of the digital logic circuit of FIG. 3B . FIG. 6 schematically shows the up pulse signal, the down pulse signal and the active signals of FIG. 5 in three states of the charge-based charge pump. Preferably, but not exclusively, the digital logic circuit 111 of the charge-based charge pump receives the up pulse signal UP and the down pulse signal DN from a three-state phase-frequency detector. As shown in FIG. 4 and highlighted FIG. 6 , there exists a finite duration when both the up pulse signal UP and the down pulse signal DN are active. Therefore, the up pulse signal UP and the down pulse signal DN cannot be directly buffered to generate the required switching signals. As shown FIG. 5 , the digital logic circuit 111 includes three differential buffers ( 21 , 22 , 26 ), three AND gates ( 23 , 24 , 25 ) and two switched buffers ( 27 , 28 ). The differential buffer ( 21 , 22 , 26 ) produces two out-of-phase differential signals incurring the same total delay with respect to their respective input signal. In order to remove the overlap between the up pulse signal UP and the down pulse signal DN, the up pulse signal UP and the down pulse signal DN are firstly split into four differential signals UPO_H, UPO_L, DNO_H and DNO_L by two differential buffers 21 and 22 . Then, three AND gates 23 , 24 and 25 are employed to extract three active signals RESET_ACTIVE, UP_ACTIVE and DN_ACTIVE according to the four differential signals UPO_H, UPO_L, DNO_H and DNO_L. The differential buffer 26 is electrically connected with the AND gate 23 for receiving the active signal RESET_ACTIVE, and the differential buffer 26 outputs two switching signals RST_H and RST_L. The switched buffer 27 is electrically connected with the AND gate 24 for receiving the active signal UP_ACTIVE, and the switched buffer 27 outputs four pairs of differential signals: UP 1 _H/UP 1 _L, UP 2 _H/UP 2 _L, UP 3 _H/UP 3 _L and UP 4 _H/UP 4 _L. The switched buffer 28 is electrically connected with the AND gate 25 for receiving the active signal DN_ACTIVE, and the switched buffer 28 outputs four pairs of differential signals: DN 1 _H/DN 1 _L, DN 2 _H/DN 2 _L, DN 3 _H/DN 3 _L and DN 4 _H/DN 4 _L.

The active signal RESET_ACTIVE is high when both the up pulse signal UP and the down pulse signal DN are low, which represents that the charge-based charge pump is in the default state. The active signal UP_ACTIVE is high when the up pulse signal UP is high and the down pulse signal DN is low. Similarly, the active signal DN_ACTIVE is high when the up pulse signal UP is low and the down pulse signal DN is high. As an example, the waveform of the three active signals RESET_ACTIVE, UP_ACTIVE and DN_ACTIVE corresponding to the three states of the charge-based charge pump are shown in FIG. 6 .

FIG. 7 is a schematic diagram illustrating the switched buffer of FIG. 5 . FIG. 8 is a schematic oscillogram of the signals of FIG. 7 . Taking the switched buffer 27 as an example, as shown in FIG. 7 , the switched buffer 27 includes a primary clock splitter 271 , a first secondary clock splitter 272 and a second secondary clock splitter 273 . The primary clock splitter 271 is electrically connected with the AND gate 24 for receiving the active signal UP_ACTIVE, as shown in FIG. 5 . The primary clock splitter 271 outputs a first internal signal UP_IN 1 and a second internal signal UP_IN 2 according to the active signal UP_ACTIVE. The first secondary clock splitter 272 is electrically connected with the primary clock splitter 271 for receiving the first internal signal UP_IN 1 . The first secondary clock splitter 272 outputs four switching signals UP 3 _H, UP 3 _L, UP 4 _H and UP 4 _L according to the first internal signal UP_IN 1 . The second secondary clock splitter 273 is electrically connected with the primary clock splitter 271 for receiving the second internal signal UP_IN 2 . The second secondary clock splitter 273 outputs four switching UP 2 _L, UP 2 _H, UP 1 _H and UP 1 _L according to the second internal signal UP_IN 2 .

As it is well known to those skilled in the art, the clock splitter structure generates varying path-delay for the in-phase and out-of-phase output in the transmission of logic 0 and logic 1. Thus, the clock splitter ( 271 , 272 , 273 ) produces two out-of-phase outputs with non-overlapping edges, where the relative phase difference between the edges determined by the relative delay incurred by the input signal to reach each of its two outputs. The primary clock splitter 271 doubles the number of delay cells in the two secondary clock splitters 272 and 273 . As shown in FIG. 8 , the delay time Tdly 1 is approximately twice that of the delay time Tdly 2 . This ensures that the phase difference between the switching signal UP 2 _H/UP 2 _L and the switching signal UP 3 _H/UP 3 _L is the same as that between the switching signal UP 1 _H/UP 1 _L and the switching signal UP 2 _H/UP 2 _L or between the switching signal UP 3 _L/UP 3 _H and the switching signal UP 4 _H/UP 4 _L. Consequently, the switched buffer 27 generates the required sequence of the four pairs of switching signals with non-overlapping edges. The components of the switched buffer 28 are similar to that of the switched buffer 27 , and thus the detailed description thereof is omitted.

When the charge-based charge pump is triggered by the up pulse signal UP, the oscillogram of the up pulse signal UP, the active signal UP_ACTIVE and the corresponding switching signals is shown in FIG. 9 . Alternatively, when the charge-based charge pump is triggered by the down pulse signal DN, the oscillogram of the down pulse signal DN, the active signal DN_ACTIVE and the corresponding switching signals is shown in FIG. 10 .

FIG. 11 is a schematic circuit diagram showing the detailed components of the charge-based charge pump of the present disclosure. The positive hold subcircuit 102 includes a second PMOS P 2 , a third PMOS P 3 , a fourth NMOS N 4 and a fifth NMOS N 5 . The negative hold subcircuit 103 includes a second NMOS N 2 , a third NMOS N 3 , a fourth PMOS P 4 and a fifth PMOS P 5 . The first dynamic body-bias generator 104 includes a sixth NMOS N 6 and a first node MPP 1 . The second dynamic body-bias generator 105 includes a sixth PMOS P 6 and a second node MNP 1 . The positive charge transfer subcircuit 106 includes a seventh PMOS P 7 , a eighth PMOS P 8 , a ninth PMOS P 9 and a thirteenth NMOS N 13 . The negative charge transfer subcircuit 107 includes a seventh NMOS N 7 , a eighth NMOS N 8 , a ninth NMOS N 9 and a thirteenth PMOS P 13 . The first static body-bias generator 108 includes a tenth PMOS P 10 , a eleventh PMOS P 11 , a twelfth PMOS P 12 , a fourteenth NMOS N 14 , a fifteenth NMOS N 15 and a third node MPP 2 . The second static body-bias generator 109 includes a tenth NMOS N 10 , a eleventh NMOS N 11 , a twelfth NMOS N 12 , a fourteenth PMOS P 14 , a fifteenth PMOS P 15 and a fourth node MNP 2 .

The entire operations of the charge-based charge pump can be classified by three operating states, namely the charge-based charge pump in the default state, the charge-based charge pump triggered by the up pulse signal UP and the charge-based charge pump triggered by the down pulse signal DN.

In the default state, the fourth NMOS N 4 and the fourth PMOS P 4 are turned on by the switching signals RST_H and RST_L respectively. Therefore, the gate of the second PMOS P 2 and the gate of the second NMOS N 2 are maintained at ground (0V) and VDD respectively. As a result, the second PMOS P 2 and the second NMOS N 2 are turned on, and the pump capacitor 101 is charged to the supply potential VDD with its top plate 101 a at VDD and its bottom plate 101 b at ground (0V).

With regard to the positive charge transfer subcircuit 106 , in the default state, the switching signals UP 3 _L and UP 4 _L are at logic high, and the switching signal UP 3 _H is at logic low. Since the thirteenth NMOS N 13 is always on with its gate and source connected to VDD, gate of the ninth PMOS P 9 is maintained at high potential. The positive charge transfer subcircuit 106 is configured to isolate the output node 110 from the top plate 101 a of the pump capacitor 101 . The operation of the positive charge transfer subcircuit 106 can be analyzed by splitting the completed output voltage range into three regions defined as follows.

(1) Vout<VDD−|V TP_P8 |, where V TP_P8 is the threshold voltage of the eighth PMOS P 8 .

(2) VDD−|V TP_P8 |<Vout<VDD+|V TP_P9 |, where V TP_P9 is the threshold voltage of the ninth PMOS P 9 .

(3) Vout>VDD+|V TP_P9 |.

For region (1), the eighth PMOS P 8 is turned on, thereby connecting the gate of the seventh PMOS P 7 to VDD and turning the seventh PMOS P 7 off. For region (2), both the eighth PMOS P 8 and the ninth PMOS P 9 are turned off, and the gate of the seventh PMOS P 7 is maintained at VDD, as there in no leakage of charge. For region (3), the ninth PMOS P 9 is turned on, and the gate of the seventh PMOS P 7 is connected to the output node 110 . Consequently, in the default state, it can be safely concluded that the seventh PMOS P 7 remains off for the entire range of the output voltage Vout from −0.84·VDD to 1.82·VDD.

With regard to the negative charge transfer subcircuit 107 , in the default state, the switching signal DN 3 _L is at logic high, and the switching signals DN 3 _H and DN 4 _H is at logic low. Since the thirteenth PMOS P 13 is always on, a gate of the ninth NMOS N 9 is maintained at low potential. The negative charge transfer subcircuit 107 is configured to isolate the output node 110 from the bottom plate 101 b of the pump capacitor 101 . The operation of the negative charge transfer subcircuit 107 can be analyzed by splitting the output voltage Vout into three regions defined as follows.

(4) Vout>V TN_N8 , where V TN_N8 is the threshold voltage of the eighth NMOS N 8 .

(5) −|V TN_N9 |<Vout<V TN_N8 , where V TN_N9 is the threshold voltage of the ninth NMOS N 9 .

(6) Vout<−|V TN_N9 |.

For region (4), the eighth NMOS N 8 is turned on, thereby causing the gate of the seventh NMOS N 7 to be at ground and turning the seventh NMOS N 7 off. For region (5), both the eighth NMOS N 8 and the ninth NMOS N 9 are turned off, and the gate of the seventh NMOS N 7 is maintained at ground, as there in no leakage of charge. For region (6), the ninth NMOS N 9 is turned on, and the gate of the seventh NMOS N 7 is connected to the output node 110 . Consequently, in the default state, it is safely concluded that the seventh NMOS N 7 remains off for the entire range of the output voltage Vout from −0.84·VDD to 1.82·VDD.

Therefore, in the default state, both the seventh PMOS P 7 and the seventh NMOS N 7 are remained off for the entire range of the output voltage Vout from −0.84·VDD to 1.82·VDD. The output node is thus electrically isolated from the top plate 101 a and the bottom plate 101 b of the pump capacitor 101 .

When the charge-based charge pump is triggered by the up pulse signal UP, firstly the switching signal RST_H goes low and the switching signal RST_L goes high for turning off the fourth PMOS P 4 and the fourth NMOS N 4 respectively. Following this, the switching signal UP 1 _L goes low, which turns on the third PMOS P 3 in the positive hold subcircuit 102 , and the fifth PMOS P 5 in the negative hold subcircuit 103 . As a result, the gate and drain of the second PMOS P 2 are connected and low potential is forced at the gate of the second NMOS N 2 . Consequently, both the second PMOS P 2 and the second NMOS N 2 are turned off, thereby isolating the top plate 101 a and bottom plate 101 b from the input supply rails VDD and ground respectively. During the same switching transition, the default high potential set by the always on sixth NMOS N 6 at the first node MPP 1 , is boosted by VDD magnitude as the switching signal UP 1 _H goes high. Then, the first PMOS P 1 is turned on by the switching signal UP 2 _L, thereby connecting the bottom plate 101 b to the input supply node and boosting the top plate 101 a to ˜2·VDD. Since the third PMOS P 3 is already turned on, the gate of the second PMOS P 2 acquires the boosted potential of the top plate 101 a at ˜2·VDD. As a result, the second PMOS P 2 remains turned off, and the top plate 101 a is kept isolated from the input supply node at VDD. Meanwhile, the boosted potential at the first node MPP 1 , connected to the body terminals of the second PMOS P 2 and the third PMOS P 3 , prevents the drain-body p-n junction diode of these two PMOS devices from being forward biased while the top plate 101 a potential is boosted, for the duration of up pulse input UP signal.

In the charge transfer process, the switching signal UP 3 _L goes low, thereby turning off the eighth PMOS P 8 . The switching signal UP 3 _H goes high, thereby boosting the default high potential at the gate of the ninth PMOS P 9 by VDD magnitude and thus turns off the ninth PMOS P 9 . After a finite time lapse, the switching signal UP 4 _L goes low, causing the potential at the gate of the seventh PMOS P 7 to be reduced by VDD. As a result, the seventh PMOS P 7 turns on, and the positive charge is transferred across the drain of the seventh PMOS P 7 . While the charge-based charge pump returns to the default state, firstly, the switching signal UP 4 _L goes high, thereby turning off the seventh PMOS P 7 . Then, the switching signals UP 3 _H and UP 3 _L go low and high respectively. The required switching order, generated by the clock splitter employed in the digital logic circuit 111 , as shown in FIG. 9 , ensures that the seventh PMOS P 7 turns on only for the period while both the eighth PMOS P 8 and the ninth PMOS P 9 are turned off.

The first static body-bias generator 108 , is a replica of the positive charge transfer subcircuit 106 , with its output terminal at the third node MPP 2 , connected to the body terminals of PMOSs P 7 , P 8 and P 9 in the positive charge transfer subcircuit 106 . In the default state, the third node MPP 2 is forced to high voltage by the fifteenth NMOS N 15 with its gate and source connected to VDD. While the charged-based charge pump is triggered by the up pulse signal UP, the first static body-bias generator 108 is enabled alongside the positive charge transfer subcircuit 106 , and therefore its output at the third node MPP 2 is connected to the top plate 101 a by turning on the PMOS P 10 through the switching signal UP 4 _L. Consequently, the potential at the third node MPP 2 is the same as that of the output voltage Vout, once the output voltage Vout crosses the default high potential set at the third node MPP 2 by the always-on fifteenth NMOS N 15 . In this way, the potential at the third node MPP 2 tracks and holds the steady-state most-positive potential of the charge-based charge pump and provides it as body biasing potential for the PMOSs P 7 , P 8 and P 9 . Since there is almost no leakage from the body of the PMOSs, the positive potential built on the third node MPP 2 is stored on the capacitor C 12 , irrespective of the output voltage Vout. Thus, it is ensured that the p-n junction diodes of the PMOSs P 7 , P 8 and P 9 remain turned off for the entire charge-pump operating range.

When the charge-based charge pump is triggered by the up pulse signal UP, the negative charge transfer subcircuit 107 remains in a state similar to the default state, and the seventh NMOS N 7 is kept off to isolate the bottom plate 101 b from the output node 110 .

In an analogous operation executed for DN pulse input, when the charge-based charge pump is triggered by the down pulse signal DN, firstly the fourth NMOS N 4 and the fourth PMOS P 4 are turned off through the switching signal RST_H going low and the switching signal RST_L going high. This is followed by a rising edge of the switching signal DN 1 _H, which turns on the third NMOS N 3 thereby connecting the gate and drain of the second NMOS N 2 , and concurrently turns on the fifth NMOS N 5 , resulting in high potential being forced at the gate of the second PMOS P 2 . Consequently, both the second NMOS N 2 and the second PMOS P 2 are turned off, and thus the top plate 101 a and the bottom plate 101 b of the pump capacitor 101 are isolated from the input supply rails VDD and ground respectively. At the same time, the switching signal DN 1 _L goes low, which pulls down the default low potential set by the always on the sixth PMOS P 6 at the second node MNP 1 by VDD magnitude. Then, the first NMOS N 1 is turned on by the switching signal DN 2 _H, thereby connecting the top plate 101 a to ground and pulling down the potential of the bottom plate 101 b to ˜−VDD. Since the third NMOS N 3 is turned on, the gate of the second NMOS N 2 acquires the inverted potential of the bottom plate 101 b at ˜−VDD. As a result, the second NMOS N 2 remains turned off, and the bottom plate 101 b is shielded from the ground node. Meanwhile, the lowered potential at the second node MNP 1 , connected to the body terminals of the second NMOS N 2 and the third NMOS N 3 , prevents the drain-body p-n junction diodes of these NMOS devices from being forward biased, for the duration on the down pulse signal DN while the potential of the bottom plate 101 b is being pulled down.

In the charge transfer process, the switching signal DN 3 _H goes high, thereby turning off the eighth NMOS N 8 . The switching signal DN 3 _L goes LOW, thereby pulling down the default low potential set at the gate of the ninth NMOS N 9 by VDD magnitude, thus turning off the ninth NMOS N 9 . After a finite time lapse, the switching signal DN 4 _H goes high, thereby increasing the potential at the gate of the seventh NMOS N 7 by VDD. As a result, the seventh NMOS N 7 turns on, and the negative charge is transferred from the bottom plate 101 b to the output node 110 . While the charge-based charge pump returning to the default state, firstly, the switching signal DN 4 _H goes high, thereby turning off the seventh NMOS N 7 . Then, the switching signals DN 3 _H and DN 3 _L go low and high respectively. The required switching order, generated by the clock splitter employed in the digital logic circuit 111 , as shown in FIG. 10 , ensures that the seventh NMOS N 7 turns on only for the period while both the eighth NMOS P 8 and the ninth NMOS N 9 are turned off.

The body bias potential for the NMOSs N 7 , N 8 and N 9 is provided by the second static body-bias generator 109 , which is a replica of the negative charge transfer subcircuit 107 , with its output terminal connected to the fourth node MNP 2 . In the default state, the fourth node MNP 2 is forced to low voltage by the fifteenth PMOS P 15 with its gate and source tied at ground. While the charged-based charge pump is triggered by the down pulse signal DN, the voltage at the fourth node MNP 2 acquires the settled output voltage Vout once the output voltage Vout falls below the initial low voltage set at the fourth node MNP 2 . Therefore, the fourth node MNP 2 tracks and holds the steady-state most negative potential of the circuit and protects any p-n junction diodes for the NMOSs N 7 , N 8 and N 9 from being turned on for the entire charge-pump operating range.

When the charge-based charge pump is triggered by the down pulse signal DN, the positive charge transfer subcircuit 106 remains in a state similar to the default state, and the seventh PMOS P 7 is kept off to isolate the top plate 101 a from the output node 110 .

The charge-based charge pump employs a number of circuit design techniques, which enables the charge-based charge pump to achieve the extended output voltage Vout ranging from −0.84·VDD to 1.82·VDD.

Firstly, the NMOSs, including N 6 , N 13 , N 14 and N 15 , are set of always-on low-threshold voltage (low V TH ) NMOS devices with their gate and source terminals tied at VDD, thus force a default high potential at their respective drain terminal. In addition, when the fifth NMOS N 5 , with its source terminal at VDD, is turned on through the switching signal DN 1 _H, it forces high potential at the gate of the second PMOS P 2 . As a complimentary implementation, the PMOSs, including P 6 , P 13 , P 14 and P 15 , are set of always-on low-threshold voltage (low V TH ) PMOS devices with their gate and source terminals tied at GND, and thus force a default low potential at their respective drain terminals. In addition, when the fifth PMOS P 5 , with its source terminal at GND, is turned on through the switching signal UP 1 _L, it forces low potential at the gate of the second NMOS N 2 . The NMOSs remain safely off when the potential of the node connected therewith is higher than the supply positive potential, and the PMOSs remain safely off when their respective drain thereof acquires negative voltage.

Secondly, the body bias potential for the PMOSs in the positive hold subcircuit 102 is provided by the first dynamic body-bias generator 104 , and the body bias potential for the NMOSs in the negative hold subcircuit 103 is provided by the second dynamic body-bias generator 105 . When the charge-based charge pump is triggered by the up pulse signal UP, the default high potential set at the first node MPP 1 of the first dynamic body-bias generator 104 is pulled up by VDD magnitude. The first node MPP 1 , connected at the body terminals of PMOSs P 2 and P 3 , thus provides dynamically boosted body-biasing for these pmos devices, for the duration of up pulse input. Conversely, when the charge-based charge pump is triggered by the down pulse signal DN, the default low potential set at the second node MNP 1 of the second dynamic body-bias generator 105 is pulled down by VDD magnitude. The second node MNP 1 , connected at the body terminals of NMOSs N 2 and N 3 , thus provides dynamically lowered body-biasing for these nmos devices, for the duration of the down pulse signal.

Thirdly, the body bias potential for the PMOSs in the positive charge transfer subcircuit 106 is provided by the first static body-bias generator 108 , and the body bias potential for the NMOSs in the negative charge transfer subcircuit 107 is provided by the second static body-bias generator 109 . When the charge-based charge pump is triggered by the up pulse signal UP, the first static body-bias generator 108 follows the output voltage Vout once the output voltage Vout exceeds the initial high potential at the third node MPP 2 . Thus, the third node MPP 2 provide the stead-state most positive potential for the PMOSs P 7 , P 8 and P 9 , irrespective of the instantaneous output voltage Vout. When the charge-based charge pump is triggered by the down pulse signal DN, the second static body-bias generator 109 tracks and holds the output voltage Vout once the output voltage Vout falls below the initial low potential set at the fourth node MNP 2 . Thus, the fourth node MNP 2 provide the steady-state most negative potential for the NMOSs N 7 , N 8 and N 9 , irrespective of the instantaneous output voltage Vout.

Lastly, the digital logic circuit 111 prevents any possible loss of charge by implementing a specific switching sequence and avoiding overlapping among various switching events involved in the charge-transfer process. For instance, the seventh PMOS P 7 and the seventh NMOS N 7 are only turned on for an intermediate duration when the NMOS or PMOS devices connected to the gates thereof are turned off. Consequently, the output voltage Vout is kept isolated from the top plate 101 a and the bottom plate 101 b of the pump capacitor 101 .

FIG. 12 is a schematic diagram illustrating a typical three-state phase frequency detector and the charge-based charge pump of the present disclosure. FIG. 13A and FIG. 13B schematically show the oscillogram of a reference input, a divider input, the up pulse signal and the down pulse signal of FIG. 12 . As shown in FIG. 12 , the charge-based charge pump operation is verified with a typical three-state phase frequency detector 2 (hereinafter referred to as PFD 2 ). The PFD 2 receives a reference input REF_IN and a divider input DIV_IN and outputs the up pulse signal UP and the down pulse signal DN. The charge-based charge pump is electrically connected with the PFD 2 for receiving the up pulse signal UP and the down pulse signal DN. As shown in FIG. 13A , the up pulse signal UP is high when the phase of the reference input REF_IN leads the phase of the divider input DIV_IN by ΔΦ seconds. The PFD 2 returns to default state when the down pulse signal DN momentarily goes high with a reset time T RST , whereby the reset time T RST is determined by the delay incurred by an internally generated reset pulse of the PFD 2 . Conversely, as shown in FIG. 13B , the down pulse signal DN is high when the phase of the reference input REF_IN lags behind the phase of the divider input DIV_IN by ΔΦ seconds. The PFD 2 returns to default state when the up pulse signal UP momentarily goes high. FIG. 14A and FIG. 14B is a schematic oscillogram illustrating the charge-pump transient behavior and the steady-state output voltage ripple, in response to the up and down pulse signals depicted in FIG. 13A and FIG. 13B respectively, with a time period T PRD of two inputs REF_IN and DIV_IN set at 4 ns, their relative phase difference ΔΦ set at 2 ns and the width of the reset pulse T RST assumed to be 0.1 ns. The indicative charge-pump transfer characteristic depicted in FIG. 14A and FIG. 14B are obtained for an input supply VDD at 1.2V, 500 fF pump capacitor 101 (C PUMP ) and 53 pF load capacitor C LOAD . It is to be noted that the value for all the aforementioned design and operating parameters is for the purposes of illustration and are in no way exclusive to the operation of the proposed charge-based charge pump. As shown in FIG. 14A , when the charge-based charge pump is triggered by the up pulse signal UP, the steady output voltage Vout reaches within 10% of 2·VDD. As shown in FIG. 14B , when the charge-based charge pump is triggered by the down pulse signal DN, the steady output voltage Vout is within 16% of −VDD. In addition, FIG. 14A and FIG. 14B also show the peak-to-peak voltage ripple at the output node when the output voltage Vout is saturated for either the up pulse signal or the down pulse signal. In either case, the steady-state ripple magnitude is under 0.5 mV and is below 0.03% of its corresponding steady-state value.

FIG. 15 is a schematic oscillogram combining the oscillogram of FIG. 14A and FIG. 14B . As shown in FIG. 15 , the proposed charge-based charge pump achieves a total output voltage range greater than 2.6 times the input supply potential VDD. The approximated linear range of the output voltage Vout, normalized to the supply potential VDD, can be considered to extend from ˜−0.7·VDD to ˜1.4·VDD. Thus, the approximated linear output range for the CP is more than 2 times the input supply potential VDD.

In order to be useable for any practical application, the charge-based charge pump has to maintain a transfer characteristic that is inherently free from any memory effect. This implies that for a given set of operating parameters, the time lapsed to reach from one potential to another, should remain independent of the prior state of the charge pump. This is ensured by testing the charge-based charge pump with a series of alternating up pulse signal UP and down pulse signal DN shown in FIG. 16A and FIG. 16B . FIG. 16A and FIG. 16B are schematic oscillograms showing the test waveforms with a series of alternating up pulse signal and down pulse signal. Each trigger input by the up pulse signal or the down pulse signal is continued for a duration, which is long enough as required to saturate the charge-based charge pump output, before the next set of trigger input is applied. FIG. 17A and FIG. 17B are schematic oscillograms illustrating the output voltage in response to the test waveforms depicted in FIG. 16A and FIG. 16B respectively. As an example of the illustration, which can be observed from FIG. 17A and FIG. 17B , the time taken to reach from 0V to 1.6V remains same whether the charge-based charge pump is powered up at t=0 or if it was previously saturated at −0.84·VDD. Similarly, the time lapsed for the output voltage Vout varying from 0V to −0.8V remains same whether the charge-based charge pump is powered up at t=0 or if it was previously saturated at 1.82·VDD. Thus, it is verified that no memory effect is manifested in the output response of the charge-based charge pump.

From the above descriptions, the present disclosure provides a charge-based charge pump with wide output voltage range. When the charge-based charge pump is powered by a standard supply potential (VDD), the charge-based charge pump allows the output voltage thereof to range from −0.84·VDD to 1.82·VDD. Meanwhile, the approximated linear output voltage range is also extended, and the useable linear output voltage range is wider. In addition, the digital logic circuit generates the plurality of switching signals in a required sequence and avoids overlapping among various switching events involved in the charge-transfer process, thereby preventing any loss of charge and ensuring that the charge-based charge pump continues to operate with high transfer efficiency. Moreover, the transfer characteristic of the charge-based charge pump is free from the memory effect. Further, when the output voltage is saturated at −0.84·VDD/1.82·VDD, the steady-state output voltage has a minimal ripple magnitude of under 0.03% of the corresponding steady-state output potential.

While the disclosure has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the disclosure needs not be limited to the disclosed embodiment.