Single-line serial data transmission circuit and single-line serial data transmission method

The present invention relates to a single-line serial data transmission circuit which transmits serial data across a single transmission line, and also relates to a single-line serial data transmission method using such a single-line serial data transmission circuit.

In recent years, there has been increasing demand for smaller, more versatile, and higher-performance semiconductor integrated circuit device. For example, in interface circuits for controlling digital signals that are implemented in power supply ICs etc., a switch from a parallel interface circuit to a serial interface circuit has been achieving reduction in the number of pins.

For example, serial data transmission is used to switch output voltages in a power supply circuit.

However, conventional serial interface circuits are at present mostly of a three-line or two-line type, and those of a single-line type are still not very common.

Well-known common single-line asynchronous serial interfaces perform transmission and reception across a single line. Despite requiring only one signal line, they conveniently permit a plurality of slave devices to be connected over a bus. They can also feed power via a single bus.

Patent Document 1 discloses a single-line serial data transmission method and a transmission interface circuit. In this transmission method, the transmitting side mixes data and a clock signal and transmits them together. The receiving side extracts clock timing and reconstructs the transmission-side data bit string. In transmission, the transmitting side alternately transmits a H-level chip selection signal with a long duration, followed by one clock signal of a zero-return type, followed by bit-by-bit data comprising the first to the last bit of transmission data in this order. When the receiving side receives the chip selection signal, the clock timing is extracted from the following data, and then, with write timing which is a predetermined time delayed from the clock timing, transmission data is written bit by bit to a buffer memory.

Patent Document 2 discloses a single-line serial data transmission method. In a communication system in which data generated in a slave part asynchronously from the operation of a master part is serially transmitted to the master part, a data transmission request from the slave part is asynchronously transmitted to the master part. The master part then transmits to the slave part a clock signal for synchronized communication based on the transmission request, and the slave part transmits to the master part the above-mentioned data in synchronism with the clock signal.

Patent Document 3 discloses a single-line serial data transmission method. In a serial communication method in which the transmitting and receiving sides are connected together across a single line and data is transmitted sequentially bit by bit, a synchronizing trigger for synchronizing the transmitting and receiving sides is transmitted. Between this synchronizing trigger and the subsequent synchronizing trigger, data of a predetermined number n (>1) of bits is transmitted. This makes it possible to achieve a serial communication method which, while preventing loss of synchronism by inserting synchronizing triggers, can prevent a drop in the transfer rate.

Patent Literature

Patent Document 1: JP-A-2002-335234

Patent Document 2: JP-A-2003-163653

Patent Document 3: JP-A-2003-273942

Non-Patent Literature

Problem to be Solved by the Invention

However, since the common single-line serial interfaces described above allow connection of a plurality of devices, they require complicated control methods. In addition, incorporation of a large capacitor is required to support a power supply circuit, and this may increase the size of the circuit area.

The single-line serial data transmission method and the transmission circuit according to Patent Document 1 allow transmission of a clock and data from the slave side, and this may increase the size of the circuit area.

The single-line serial data transmission method according to Patent Document 2 allows connection of a plurality of slaves, and this increases the size of the circuit area. Furthermore, a start bit and a stop bit are used only for identifying plurality of slaves and at the start of communication from the slave to the master, and thus the purpose of the use of the start bit and the stop bit is different from that in the present invention.

In the single-line serial data transmission method according to Patent Document 3, a clock is required in both the master and the slave, and this may increase the size of the circuit area. Furthermore, when there is a large error between the respective clock frequencies, high-speed data transmission may not be possible.

The present invention is made with consideration given to the above problems, and is aimed at providing a single-line serial data transmission circuit with a simpler circuit design and a simpler transmission method than in conventional single-line serial data transmission circuits.

According to one aspect of the present invention, a single-line serial transmission circuit has a master circuit and a slave circuit. The master circuit includes a data clock adder used in writing transmission data from the master circuit to the slave circuit and a data receiver used in writing reception data from the slave circuit to the master circuit. The slave circuit includes a data clock separator used in writing the transmission data from the master circuit to the slave circuit, a data transmitter used in writing the reception data from the slave circuit to the master circuit, and an active generator. The master circuit and the slave circuit are connected together via a single signal line.

According to another aspect of the present invention, in the single-line serial transmission circuit, during a write of the transmission data from the master circuit to the slave circuit, in the master circuit, a synthetic signal synthesized from a clock signal and a data signal by the data clock adder is transmitted to the slave circuit via the signal line. In the slave circuit, the synthetic signal transmitted via the signal line is passed through the data clock separator, and is then passed through a delay circuit to extract the clock signal and through the data clock separator to extract the data signal.

According to another aspect of the present invention, in the single-line serial transmission circuit, during a write of the reception data from the slave circuit to the master circuit, a logic out signal from a logic in the slave circuit is passed through a delay circuit and the data transmitter and is transmitted via the signal line to the master circuit. In the master circuit, transmission data transmitted from the signal line is passed through the data receiver to extract a read data signal.

According to another aspect of the present invention, in the single-line serial transmission circuit, the slave circuit includes a signal terminal via which a synthetic signal synthesized from a clock signal and a data signal by the data clock adder is received, a control terminal via which the slave circuit is brought into a data accepting state, a slave clock terminal, and a slave data terminal. An input to the signal terminal is fed as the data signal to the slave data terminal. The clock signal generated from the input to the signal terminal is fed to the slave clock terminal. A control signal generated from the input to the signal terminal is fed to the control terminal.

According to another aspect of the present invention, in the single-line serial transmission circuit, in the slave circuit, the input to the signal terminal is fed as the data signal to the slave data terminal. The clock signal generated from the input to the signal terminal via a D flip-flop is fed to the slave clock terminal. The control signal generated from the input to the signal terminal via a delay circuit and the D flip-flop is fed to the control terminal.

According to another aspect of the present invention, in the slave circuit, the input to the signal terminal is fed as the data signal to the slave data terminal. The clock signal generated from the input to the signal terminal via the D flip-flop is fed to the slave clock terminal. The control signal generated from the input to the signal terminal via the delay circuit is fed to the control terminal.

According to another aspect of the present invention, in the single-line serial transmission circuit, to delay the input to the signal terminal, the delay circuit charges a capacitor with a current source and discharges a capacitor with a MOS transistor.

According to another aspect of the present invention, in the single-line serial transmission circuit, the delay circuit is composed of a charging/discharging circuit including a resistor and a capacitor, and a delay time is determined by a resistance value of the resistor and a capacitance value of the capacitor.

According to another aspect of the present invention, in the single-line serial transmission circuit, generation of the clock signal becomes possible when the control signal turns to high level, and the control signal stabilizes the control signal itself on having turned to high level or low level.

According to another aspect of the present invention, in the single-line serial transmission circuit, the slave circuit responds to the signal line upon receiving a request of a read (reading) from the master circuit to the slave circuit.

According to another aspect of the present invention, in the single-line serial transmission circuit, the slave circuit includes a switching power supply circuit.

According to another aspect of the present invention, in the single-line serial transmission circuit, the switching power supply circuit has at least one of an overcurrent protection function, an overvoltage protection function, an output ground short protection function, and a temperature protection.

According to another aspect of the present invention, in a single-line serial transmission method, communication starts at a fall of a synthetic signal synthesized from a clock signal and a data signal by the data clock adder, and when the synthetic signal stays at low level for a predetermined time, a control signal generated from the synthetic signal turns to high level to bring the slave circuit into an accepting state. A slave clock is extracted a predetermined time after the fall of the synthetic signal, and data is read at a rise of the slave clock. When the synthetic signal stays at high level for a predetermined time, the control signal turns to low level to bring the slave circuit into a non-accepting state, thereby ending communication.

According to another aspect of the present invention, in the single-line serial transmission method, the synthetic signal includes a start bit at the head, followed by a read (reading) and a write (writing), an address, data, and a stop bit at the tail.

According to another aspect of the present invention, in the single-line serial transmission method, at a start of communication, an AND of the clock signal and the data signal is transmitted as the synthetic signal from the master circuit, and when the synthetic signal stays at low level for a cycle T of the clock signal or longer, the control signal of the slave circuit turns to high level, thereby bringing the slave circuit into an accepting state.

According to another aspect of the present invention, in the single-line serial transmission method, a pulse width y 2 of the clock signal is set such that y 2 =T/m (the cycle T divided by m; 2≤m≤50), and other events are processed during part of a time of one cycle excluding the pulse width.

According to another aspect of the present invention, in the single-line serial transmission method, during a write (writing), an AND of the clock signal and the data signal is transmitted as the synthetic signal from the master circuit. The slave circuit drops a slave clock at a fall of the synthetic signal and then generates a signal which rises T/m (the cycle T of the clock signal divided by m) thereafter, and at a rise of the slave clock, slave data is determined.

According to another aspect of the present invention, in the single-line serial transmission method, during a read (reading), the clock signal alone is transmitted as the synthetic signal from the master circuit. The slave circuit drops a slave clock at a fall of the clock signal and then generates a signal which rises T/m (the cycle T of the clock signal divided by m) thereafter. At a rise of the slave clock, a logic out is determined. At a rise of the slave clock, a data out is determined. At a rise of a read clock in the master circuit, a signal is read.

According to another aspect of the present invention, in the single-line serial transmission method, at an end of communication, an AND of the clock signal and the data signal is transmitted as the synthetic signal from the master circuit, and when the synthetic signal stays at high level for a cycle T of the clock signal or longer, the control signal of the slave circuit turns to low level, thereby bringing the slave circuit into a non-accepting state.

According to another aspect of the present invention, a master circuit includes a data clock adder used in writing transmission data to a slave circuit and a data receiver used in writing reception data from the slave circuit. The master circuit forms a single-line serial transmission circuit by being connected with the slave circuit via a single signal line.

Advantageous Effects of the Invention

According to the invention disclosed herein, in a single-line serial transmission circuit of what is called a one-to-one configuration which is configured such that one slave circuit is provided for one master circuit, it is possible to achieve a smaller circuit scale than before.

FIG. 1 A block diagram showing an outline of a single-line serial data transmission circuit of the present invention.

FIG. 2 A block diagram showing a configuration of part of a slave circuit 4 .

FIG. 3 A diagram showing a timing chart associated with FIG. 2 .

FIG. 4 A circuit diagram showing one specific example of the part of the configuration shown in FIG. 2 .

FIG. 5 A circuit diagram showing another specific example of the part of the configuration shown in FIG. 2 .

FIG. 6 A diagram showing an example of data configuration adopted in a single-line serial data transmission method of the present invention.

FIG. 7 A diagram showing a start bit signal used in the single-line serial data transmission method of the present invention.

FIG. 8 A diagram showing a stop bit signal used in the single-line serial data transmission method of the present invention.

FIG. 9 A diagram showing a write signal (write) used in the single-line serial data transmission method of the present invention.

FIG. 10 A diagram showing a read signal (read) used in the single-line serial data transmission method of the present invention.

Now, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an outline of a single-line serial data transmission circuit of the present invention. A master circuit 1 has a data clock adder 2 , which adds together a clock CLK and data DATA, and a data receiver 3 . A slave circuit 4 has an active generator 5 , which generates a control signal ACT; a data clock separator 6 , which separates a slave clock SCLK from slave data SDATA; and a data transmitter 7 . The master circuit 1 and the slave circuit 4 are connected together via a signal line 8 .

One example of the slave circuit 4 is a power supply circuit. An incorporated logic 9, by receiving the control signal ACT, the slave clock SCLK, and the slave data SDATA, controls at least one of the protection functions of a comparatively large number of circuits provided as protection circuits for, for example, a switching regulator 14 , such as an overcurrent protection function (OCP) 10 , an overvoltage protection function (OVP) 11 , an output ground short protection function (SCP) 12 , and a temperature protection function (TSD) 13 . The overcurrent protection function 10 etc. control a driver logic 15 of the switching regulator 14 under a condition set by the logic 9.

The switching regulator 14 is provided with, in addition to the overcurrent protection function 10 etc., a driver logic 15 , an error amplifier 16 , a PWM comparator 17 , an oscillator 18 , a reference voltage source 19 , a PMOS transistor P 1 , and an NMOS transistor N 1 , and has these integrated in it. In addition, the switching regulator 14 is provided with external terminals VIN, SW, PGND, FB, and COMP for establishing electrical connection with the outside. Furthermore, as external components, there are provided a power source Vin, a coil L 1 , a capacitor C 1 , a capacitor C 2 , a resistor R 1 , a resister R 2 , and a resister R 3 . Since the topology of the switching regulator 14 is a common one, it will not be discussed herein.

In a power supply circuit that employs the single-line serial transmission circuit and its transmission method shown in FIG. 1 , the clock CLK and the data DATA are transmitted from the master circuit 1 to the slave circuit 4 , and are received as the slave clock SCLK by the slave circuit 4 and the slave data SDATA. In the slave circuit 4 , the settings of various protection functions are changed based on the received slave data SDATA.

This makes it possible, for example, to change specifications such that, for one user, the sensing threshold value of the overvoltage protection function 11 is set at 25 V and the sensing threshold value of the overcurrent protection function 10 is set at 1.5 A, and, for another user, the sensing threshold value of the overvoltage protection function 11 is set at 20 V and the sensing threshold value of the overcurrent protection function 10 is set at 1.0 A.

When communication between the master circuit 1 and the slave circuit 4 is started, an activating signal at, for example, low level L is transmitted from the master circuit 1 to the slave circuit 4 via the signal line 8 . In the slave circuit 4 , the activating signal is passed through the active generator 5 , and thereby the control signal ACT is activated; this brings the logic 9 into a data accepting state.

In this description, a write (writing) means writing of control data from the master circuit 1 to the slave circuit 4 , and a read (reading) means reading of status data from the slave circuit 4 to the master circuit 1 .

During a write (writing), the clock CLK and the data DATA are, as a synthetic signal SIG synthesized by the data clock adder 2 , output from the master signal terminal Tms of the master circuit 1 to the signal line 8 . In the slave circuit 4 , the synthetic signal SIG passes via the signal terminal Tsig through the data clock separator 6 to be separated into the slave data SDATA and the slave clock SCLK.

During a read (reading), the clock CLK alone is, as the synthetic signal SIG, transmitted from the master circuit 1 to the signal line 8 . In the slave circuit 4 , the clock CLK fed in via the data clock separator 6 is used as the slave clock SCLK. An output logic out LO from the logic 9 is turned into a data out DO via a delay circuit LC 14 , and the data out DO is output to the signal line 8 via the data transmitter 7 . The master circuit 1 reads, with the data receiver 3 , the data out DO from the slave circuit 4 using a read clock RCLK and uses the data out DO as read data RDATA.

When communication is finished, a deactivating signal at high level H is transmitted from the master circuit 1 to the slave circuit 4 via the signal line 8 . In the slave circuit 4 , the activating signal is passed through the active generator 5 , and thereby the control signal ACT is deactivated; this brings the logic 9 into a non-data accepting state.

FIG. 2 is a block diagram showing a specific configuration of a part (the active generator 5 , the data clock separator 6 , and the data transmitter 7 ) of the slave circuit 4 .

The slave circuit 4 has a signal terminal Tsig for receiving the synthetic signal SIG, a control terminal Tact for bringing the slave circuit 4 into a data accepting state or a non-data accepting state, a slave clock terminal Tsc, a slave data terminal Tsd, and a logic out terminal Tlo.

To the slave data terminal Tsd, the output of a buffer BUF 11 is connected. The input of the buffer BUF 11 is connected to the signal terminal Tsig. To the slave clock terminal Tsc, the output of a clock generation circuit CG 11 is connected. The input of the clock generation circuit CG 11 is connected to the output of the delay circuit LC 13 . The input of the delay circuit 13 is connected to the signal terminal Tsig.

To the signal terminal Tsig, the input of an inverter INV 11 and the first input of an AND circuit AND 11 are connected. The output of the inverter INV 11 is connected to the input of a delay circuit LC 11 . The output of the delay circuit LC 11 is connected to the set terminal Set of an RS flip-flop RSFF 11 .

The output terminal Q of the RS flip-flop RSFF 11 is connected to the control terminal Tact and to the second input of the AND circuit AND 11 . The output of the AND circuit AND 11 is connected to the input of a delay circuit LC 12 . The output of the delay circuit LC 12 is connected to the reset terminal Reset of the RS flip-flop RSFF 11 .

The logic out terminal Tlo is connected to the input of the delay circuit LC 14 . The output of the delay circuit LC 14 is connected to the input of an inverter INV 91 . The output of the inverter INV 91 is connected to the gate of a MOS transistor M 91 . The source of the MOS transistor M 91 is connected to a ground potential DGND. The drain of the MOS transistor M 91 is connected to the signal terminal Tsig.

In the illustrated single-line serial transmission circuit, the clock CLK and the data DATA are transmitted together via a single signal line. The synthetic signal SIG also serves as the control signal ACT. Thus, the inverter, the delay circuit, the RS flip-flop, etc. are used to separate those signals.

For example, the inverter INV 11 and the delay circuit LC 11 are provided to turn the control signal ACT to high level H a predetermined time after the synthetic signal SIG turns to low level L (that is, the logic level during the activated time). On the other hand, the AND circuit AND 11 and the delay circuit LC 12 are provided to turn the control signal ACT to low level L a predetermined time after the synthetic signal SIG turns to high level H (that is, the logic level during the deactivated period). The RS flip-flop RSFF 11 is used to hold the logic level of the control signal ACT.

The delay circuit LC 13 and the clock generation circuit CG 11 are used to extract the clock. A read (reading) is performed using the MOS transistor M 91 . The inverter circuit INV 91 is provided to drive the MOS transistor M 91 . If the polarity of the signal permits, the inverter INV 91 may be replaced with a buffer. The delay circuit LC 14 is used to adjust the output timing of a read (reading).

FIG. 3 is a timing chart of different signals that appear at relevant nodes during a write (writing) in the slave circuit 4 shown in FIG. 2 .

The synthetic signal SIG is fed from the master circuit 1 to the signal terminal Tsig of the slave circuit 4 via the signal line 8 . The level and the behavior of the synthetic signal SIG at different time points are as described below.

At time point t 0 , the synthetic signal SIG turns to low level L and communication starts between the master circuit 1 and the slave circuit 4 . At time point t 3 , the signal turns to high level H and preparation is done for generation of the slave clock SCLK. At time point t 4 , the signal turns to low level L and generation of the slave clock SCLK is started. At time point t 5 , the signal turns to high level H and preparation is done for reading of the slave data SDATA. At time point t 7 , the signal turns to low level L and generation of the slave clock SCLK is started. At time point t 8 , the signal is at low level L and preparation is done for reading of the slave data SDATA. At time point t 9 , the signal turns to high level H and preparation is done for ending of communication.

The control signal ACT is a signal fed (output) to the control terminal Tact and determines whether the slave circuit 4 is in a data accepting state or in a non-data accepting state. When the control signal ACT is at low level L, the slave circuit 4 does not accept the slave data SDATA.

The control signal ACT turns to high level H at time point t 2 and the slave circuit 4 goes into a data accepting state. Between time points t 0 and t 2 , a predetermined response start time Y is provided. This is to prevent a false value from being written to the slave circuit 4 due to noises or the like.

The slave clock SCLK is a signal extracted to the slave clock terminal Tsc. At time point t 1 , the slave clock SCLK responds, but at that time the control signal ACT is at low level and thus the slave circuit 4 does not operate as such. The response wait time X 1 before the slave clock SCLK responds will be described later.

The slave clock SCLK appears at time point t 6 , which is a response wait time X 2 later than the fall of the synthetic signal SIG. The setting of the response wait time X 2 is very important in reading the slave data SDATA. In a single-line serial data transmission method according to the present invention, the clock CLK and the data DATA are mixed and transmitted together as the synthetic signal SIG. Thus, how far behind the clock CLK to place the data DATA needs to be determined in advance so as to be able to determine at what timing to read the slave data SDATA.

The slave data SDATA is at high level H or at low level L with the same timing as the synthetic signal SIG, and is read when the slave clock SCLK rises. At time point t 1 , the slave clock SCLK responds, but at that time the control signal ACT is at low level and thus the slave circuit 4 does not operate as such.

The slave data SDATA is at high level H at time point t 6 , and thus, in this example, high level H is read as the slave data SDATA.

The slave data SDATA is at low level L a response wait time X 3 after time point t 7 , that is, at time point t 8 , and thus, in this example, low level L is read as the slave data SDATA. The response wait times X 1 , X 2 , and X 3 are set at the same value in the embodiment of the present invention.

At time point t 9 , the synthetic signal SIG turns to high level H. Then, when the period of a given response end time Z has passed, that is, at time point t 10 , the control signal ACT turns to low level L. The slave circuit 4 goes into a non-data accepting state and communication ends.

FIG. 4 is an example, as presented in a specific circuit diagram, of the active generator 5 and data clock separator 6 shown in the block diagram in FIG. 2 . The single-line serial transmission circuit having the active generator 5 and the data clock separator 6 shown in FIG. 4 includes a signal terminal Tsig for receiving the synthetic signal SIG, a control terminal Tact for bringing the slave circuit 4 into a data accepting state or a non-accepting state, a slave clock terminal Tsc, and a slave data terminal Tsd.

To the signal terminal Tsig, the input of an inverter INV 21 , the input of a buffer BUF 21 , and the input of a buffer BUF 23 are connected, and the output of the buffer BUF 23 is connected to the slave data terminal Tsd. The buffer BUF 23 is used to pass the synthetic signal SIG as the slave data SDATA to the succeeding stage.

The output of the inverter INV 21 is connected to the CP input of a D flip-flop DFF 22 . To the D input of the D flip-flop DF 22 , a supply power potential VREG 3 D is connected. The inverter INV 21 is used to drive the D flip-flop DFF 22 at the fall of the signal.

To the RN input of the D flip-flop DFF 22 , the output of an AND circuit AND 22 is connected. To the output of the D flip-flop DFF 22 , the input of an inverter INV 24 is connected. The D flip-flop DFF 22 is used to extract the slave clock SCLK. The output of the inverter INV 24 is connected to the slave clock terminal Tsc. The inverter INV 24 is used to adjust the polarities and the delay time of the slave clock SCLK and also as a buffer which connects the D flip-flop DFF 22 to the slave clock terminal Tsc.

The output of the buffer BUF 21 is connected to the second input of a NAND circuit NAND 21 and to the gate of a MOS transistor M 21 , and the source of the MOS transistor M 21 is connected to the ground potential DGND. The buffer BUF 21 is used to drive the MOS transistor M 21 .

The drain of the MOS transistor M 21 is connected to one end of a capacitor C 21 , to the input of a buffer BUF 22 , and to one end of a current source CC 21 , and the other end of the capacitor C 21 is connected to the ground potential DGND.

The other end of the current source CC 21 is connected to the supply power potential VREG 3 D. The output of the buffer BUF 22 is connected to the CP input of a D flip-flop DFF 21 . To the D input of the D flip-flop DFF 21 , the supply power potential VREG 3 D is connected. The buffer BUF 22 is used to shape the waveform of a triangular-wave signal generated by the current source CC 21 and the capacitor C 21 .

To the RN input of the D flip-flop DFF 21 , the output of an inverter INV 22 is connected, and the output of the D flip-flop DFF 21 is connected to the control terminal Tact. The D flip-flop DFF 21 is used to hold the control signal ACT.

The first input of the NAND circuit NAND 21 is connected to the control terminal Tact, and the output of the NAND circuit NAND 21 is connected to the gate of a MOS transistor M 22 . The source of the MOS transistor M 22 is connected to the ground potential DGND, and the drain of the MOS transistor M 22 is connected to one end of a capacitor C 22 , to the input of the inverter INV 22 , and to one end of a current source CC 22 . The NAND circuit NAND 21 is controlled by the control signal ACT and is used to drive the MOS transistor M 22 . The inverter INV 22 is used to shape the waveform of a triangular-wave signal generated by the current source CC 22 and the capacitor C 22 .

The other end of the capacitor C 22 is connected to the a ground potential DGND, and the other end of the current source CC 22 is connected to the supply power potential VREG 3 D.

The slave clock terminal Tsc is connected to the gate of a MOS transistor M 23 , and the source of the MOS transistor M 23 is connected to the ground potential DGND. The drain of the MOS transistor M 23 is connected to one end of a capacitor C 23 , to the input of an inverter INV 23 , and to one end of the current source CC 23 . The other end of the capacitor C 23 is connected to the ground potential DGND, and the other end of the current source CC 23 is connected to the supply power potential VREG 3 D.

The output of the inverter INV 23 is connected to the first input of the AND circuit AND 22 . The control terminal Tact is connected to the second input of the AND circuit AND 22 . The inverter INV 23 is used to shape the waveform of a triangular-wave signal generated by the current source CC 23 and the capacitor C 23 . The AND circuit AND 22 is controlled by the control signal ACT and is used to generate the slave clock SCLK.

The response start time Y shown in FIG. 3 is determined by the current value of the current source CC 21 and the capacitance value of the capacitor C 21 . The response end time Z in FIG. 3 is determined by the current value of the current source CC 22 and the capacitance value of the capacitor C 22 . The response wait time X shown in FIG. 3 is determined by the current value of the current source CC 23 and the capacitance value of the capacitor C 23 .

FIG. 5 is a circuit diagram showing another specific example of the part of the configuration shown in FIG. 2 . A major difference from FIG. 4 is that less capacitors are used as a result of a delay circuit used in the active generator 5 being shared. By the shared delay circuit, the response start times Y and Z in FIG. 3 are generated.

The active generator 5 and the data clock separator 6 shown in FIG. 5 include a signal terminal Tsig for receiving the synthetic signal SIG, a control terminal Tact for turning the slave circuit 4 data to a data accepting state, a slave clock terminal Tsc, and a slave data terminal Tsd.

To the signal terminal Tsig, the input of an inverter INV 31 and the input of a buffer BUF 31 are connected, and the output of the buffer BUF 31 is connected to the slave data terminal Tsd. The buffer BUF 31 is used to pass the synthetic signal SIG as slave data SDATA to the succeeding stage.

The output of the inverter INV 31 is connected to one end of a resistor R 31 , to the input of an inverter INV 33 , to the input of an inverter INV 36 , and to the CP input of the D flip-flop DFF 31 . To the D input of the D flip-flop DFF 31 , the supply power potential VREG 3 D is connected. The inverter INV 31 is used to drive the resistor R 31 .

To the RN input of the D flip-flop DFF 31 , the output of the AND circuit AND 33 is connected. To the output of the D flip-flop DFF 31 , the input of the inverter INV 39 is connected. The output of the inverter INV 39 is connected to the slave clock terminal Tsc. The inverter INV 39 is used to adjust the polarities and the delay time of the slave clock SCLK and also as a buffer which connects the D flip-flop DFF 31 to the slave clock terminal Tsc. The D flip-flop DFF 31 is used to extract the slave clock SCLK.

The output of the inverter INV 36 is connected to the second input of an AND circuit AND 31 . The input of an inverter INV 35 is connected to the control terminal Tact. The output of the inverter INV 35 is connected to the first input of the AND circuit AND 31 . The output of the AND circuit AND 31 is connected to the gate of a MOS transistor M 33 . The inverters INV 35 and INV 36 are used to adjust the polarities of the control signal ACT and the synthetic signal SIG, respectively, which are fed to the AND circuit AND 31 .

The AND circuit AND 31 is controlled by the control signal ACT and is used to drive the MOS transistor M 33 .

The output of the inverter INV 33 is connected to the second input of an OR circuit OR 31 . The input of an inverter INV 32 is connected to the control terminal Tact. The output of the inverter INV 32 is connected to the first input of the OR circuit OR 31 . The output of the OR circuit OR 31 is connected to the gate of a MOS transistor M 31 . The inverters INV 32 and INV 33 are used to adjust the polarities of the control signal ACT and the synthetic signal SIG, respectively, which are fed to the OR circuit OR 31 .

The OR circuit OR 31 is controlled by the control signal ACT and is used to drive the MOS transistor M 31 .

The source of the MOS transistor M 31 is connected to the supply power potential VREG 3 D. The drain of the MOS transistor M 31 is connected to the other end of a resistor R 31 , to one end of a capacitor C 31 , to the drain of a MOS transistor M 33 , and to the input of a Schmitt inverter SMT 31 . The output of the Schmitt inverter SMT 31 is connected to the input of an inverter INV 37 . The Schmitt inverter SMT 31 is used to shape the waveform of a triangular-wave signal generated by the resistor 31 and the capacitor C 31 .

The source of the MOS transistor M 33 is connected to the ground potential DGND. The other end of the capacitor C 31 is connected to the ground potential DGND. The source of a MOS transistor M 34 is connected to the ground potential DGND. One end of a capacitor C 32 is connected to the ground potential DGND.

The drain of the MOS transistor M 34 is connected to the other end of the capacitor C 32 , to the input of an inverter INV 38 , and to one end of a resistor R 32 . The slave clock terminal Tsc is connected to the gate of the MOS transistor M 34 . The other end of the resistor R 32 is connected to the drain of a MOS transistor M 32 . The source of the MOS transistor M 32 is connected to the supply power potential VREG 3 D.

The output of the inverter INV 38 is connected to the first input of the AND circuit AND 33 . The control terminal Tact is connected to the second input of the AND circuit AND 33 . The inverter INV 38 is used to shape the waveform of a triangular-wave signal generated by the resistor R 32 and the capacitor C 32 . The AND circuit AND 33 is controlled by the control signal ACT and is used to generate the slave clock SCLK.

The output of the inverter INV 37 is connected to the input of a buffer BUF 32 and to the input of an inverter INV 34 . The output of the inverter INV 34 is connected to the gate of the MOS transistor M 32 . The output of the buffer BUF 32 is connected to the control terminal Tact. The inverter INV 37 is used to adjust polarities. The inverter INV 34 is used to drive the MOS transistor M 32 . The buffer BUF 32 is used to drive the control signal ACT.

FIG. 6 shows an example of data configuration adopted in the serial data transmission method of the present invention. Data used in the present invention is composed of a start bit 61 at the head, the subsequent one bit for read/write judgement 62 , the subsequent seven bits for specifying an address 63 , the subsequent eight bits for transmitting or receiving data 64 , and a stop bit 65 at the tail. A possible usage is, for example, to specify the storage destination of the sensing threshold value of the overvoltage protection function 11 in the address 63 and to set the sensing threshold value in the data 64 .

For the slave circuit 4 to be able to receive a command, it needs to receive the start bit 61 from the master circuit 1 .

FIG. 7 shows different signals which appear at relevant nodes in the master circuit 1 and the slave circuit 4 shown in FIG. 1 . They will be described below with reference to FIGS. 1 to 6 .

In this example, the transmission frequency f 1 ranges, for example, approximately from 100 kHz to 2 MHz. The frequency can be changed through the adjustment of the resistor R 31 , the capacitor C 31 , the resistor R 32 , and the capacitor C 32 shown in FIG. 5 (in FIG. 4 , the constant current sources and the capacitors), through the adjustment of the delay time of the delay circuit LC 14 in FIG. 2 , and through the setting of the master circuit 1 (the changing of the settings for the read clock RCLK) according to different frequencies.

FIG. 7 shows a signal of the start bit 61 . In this example, the transmission frequency f 1 is, for example, 200 kHz; that is, the clock CLK is transmitted in such a way that it falls and holds low for 1 μs (the clock transmission time y 2 ) every 5 μs (one cycle time y 1 ).

The clock CLK transmits low level L for only one fifth (T/5) of a cycle (T).

The data DATA stays at low level L for a time equal to or longer than two cycles (2T). Here, the time is set to be equal to or longer than the cycle T for distinction from low level L in the data DATA during a write (writing), which will be described later. With manufacturing variations in ICs taken into consideration, however, it is preferable that the time be set to be two cycles or longer. Accordingly, in this example, the time is set to be two cycles or longer.

The synthetic signal SIG has the waveform of the AND of the clock CLK and the data DATA.

The control signal ACT turns to high level H when the synthetic signal SIG stays at low level L for a time equal to or longer than two cycles (2T), and this brings the slave circuit 4 into a data DATA accepting state. A response start transmission time y 3 needs to be longer than a response start time y 4 .

In this example, two cycles (2T) equal 10 μs (the response start time y 4 ). The subsequent one bit permits a read/write 62 judgement. It is assumed that a high level H indicates a read (reading) and that low level L indicates a write (writing). The subsequent seven bits indicate the address 63 , and the subsequent eight bits indicate the data 64 . The stop bit 65 at the tail marks the end of communication.

FIG. 8 shows a signal of the stop bit 65 .

The clock CLK transmits low level L for only one fifth (T/5) of a cycle (T).

The data DATA stays at high level H for a time equal to or longer than two cycles (2T). Here, the time is set to be longer than the cycle T for distinction from high level H in the data DATA during a write (writing), which will be described later. With manufacturing variations in ICs taken into consideration, however, it is preferable that the time be set to be two cycles or longer. Accordingly, in this example, the time is set to be two cycles or longer.

The synthetic signal SIG has the waveform of the AND of the clock CLK and data DATA.

The control signal ACT turns to low level L when the synthetic signal SIG stays at high level H for a time equal to or longer than two cycles (2T), and this brings the slave circuit 4 into a non-data DATA accepting state. A response end transmission time y 5 needs to be longer than a response end time y 6 . In this example, two cycles (2T) equal 10 μs (the response end time y 6 ).

FIG. 9 shows the signals (clock CLK and data DATA) in the master circuit 1 , the synthetic signal SIG, and the signals (slave clock SCLK and slave data SDATA) in the slave circuit 4 , all as observed during a write (writing).

The clock CLK transmits low level L for only one fifth (T/5) of a cycle (T).

The data DATA, while at low level L, outputs low level L for about four fifths (4T/5) of a cycle (a data low time y 7 ), and, while at high level H, outputs high level H for one cycle (T) (a data high time y 8 ).

The synthetic signal SIG has the waveform of the AND of the clock CLK and data DATA.

The slave clock SCLK exhibits a waveform Tr 1 which falls at the same time as the fall Tf 1 of the synthetic signal SIG and rises about two fifths (2T/5) of a cycle thereafter (after a clock reception time y 9 has passed).

The slave data SDATA is exactly the same as the synthetic signal SIG.

The slave circuit 4 reads the slave data SDATA at the rise Tr 1 of the slave clock SCLK.

FIG. 10 shows the signals (clock CLK and read clock RCLK) in the master circuit 1 , the synthetic signal SIG, and the signals (slave clock SCLK, logic out LO, and data out DO) in the slave circuit 4 , all as observed during a read (reading).

The clock CLK transmits low level L for only one fifth (T/5) of a cycle (T).

The read clock RCLK falls at the same time as the fall of the clock CLK and reads the read data RDATA at the rise of the set terminal Set, that is, about three fifths (3T/5) of a cycle thereafter (after a read time y 10 has passed).

As the synthetic signal SIG, the AND signal of the clock CLK from the master circuit 1 and the data out DO from the slave circuit 4 is transmitted.

The slave clock SCLK exhibits a waveform Tr 2 which falls at the same time as the fall Tf 2 of the synthetic signal SIG and rises about two fifths (2T/5) of a cycle thereafter (after a clock reception time y 9 has passed).

The output of the logic out LO is determined at the rise of the slave clock SCLK.

The data out DO so operates that its logic level to be output is determined at the fall of the logic out LO and that it outputs that logic level for about two-fifths (2T/5) of a cycle (a data output time y 11 ).

The invention has been described by way of an example where a cycle is divided into five periods, but this is not meant to be any limitation.

In this example, what happens in one cycle is divided into the following four events:

They include transmission of the clock CLK from the master circuit 1 : generation of the slave clock SCLK in the slave circuit 4 ; generation of the read clock RCLK in the master circuit 1 ; and transmission of data DATA from the master circuit 1 (or transmission of data out DO from the slave circuit 4 ).

In addition to the above four events, returning to initial values constitutes another event, and so a total of five events is necessary in one cycle. This is the reason that the above description assumes division into five segments.

For example, if the read (reading) function is omitted, division into four segments is sufficient. Or, the number of division may be increased to, for example, six or seven.

Furthermore, while, in this invention, a cycle is divided into five equal periods for easy understanding, this is not meant to be any limitation in implementation. For example, the clock CLK pulse width y 2 is set such that y 2 =cycle T/m (2≤m≤50). That is, generation of the clock CLK may be processed in a shorter or longer time than in the example, and the rest of the time may be used for other events. That is, in the case of the events during a write (writing), the clock pulse width y 2 , the clock reception time y 9 , the data low time y 7 , and the data high time y 8 can maintain the relationship of y 2 <y 9 <y 7 (or y 8 ). Maintaining such a magnitude relationship permits the clock signal and the data signal to be processed properly.

While the present invention has been described on the assumption that all signals are high initially, needless to say, the same results can be achieved with all the signals reversed so that they are low initially.

As described above, it is possible to configure a high-speed single-line serial data transmission circuit with a very simple circuit configuration.

This invention is to provide a single-line serial transmission circuit, and a transmission method for use in it, that can greatly contribute to space saving, which is sought in recent years. Thus, the present invention finds extremely wide industrial application.

1 master circuit

2 data clock adder

3 data receiver

4 slave circuit

5 active generator

6 data clock separator

7 data transmitter

8 signal line

9 logic

10 overcurrent protection function

11 overvoltage protection function

12 output ground short protection function

13 temperature protection function

14 switching regulator

15 driver logic

16 error amplifier

17 PWM comparator

18 oscillator

19 reference voltage source

61 start bit

62 read/write

63 address

64 data

65 stop bit

ACT control signal

AND 11 , AND 21 , AND 22 , AND 31 to AND 33 AND circuit

BUF 11 , BUF 21 to BUF 23 , BUF 31 , BUF 32 buffer circuit

C 1 , C 2 , C 21 to C 23 , C 31 , C 32 capacitor

CC 21 to CC 23 current source

CLK clock

CG 11 clock generation circuit

COMP phase compensation terminal

DATA data

DGND ground potential

DFF 21 , DFF 22 , DFF 31 D flip-flop circuit

DO data out

f 1 transmission frequency

FB feedback terminal

H high level

INV 11 , INV 21 to INV 24 , INV 31 to INV 39 , INV 91 inverter circuit

L low level

L 1 coil

LC 11 to LC 14 delay circuit

LO logic out

M 21 to M 23 , M 31 to M 34 , M 91 MOS transistor

N 1 NMOS transistor

NAND 21 NAND circuit

OCP overcurrent protection function

OVP overvoltage protection function

OR 31 OR circuit

P 1 PMOS transistor

PGND ground terminal

Q output terminal

R 1 , R 2 , R 3 , R 31 , R 32 resistor

RCLK read clock

RDATA read data

Reset reset terminal

RSFF 11 RS flip-flop circuit

SCLK slave clock

SCP output ground short protection function

SDATA slave data

Set set terminal

SIG synthetic signal

SMT 31 Schmitt inverter circuit

SW switching terminal

T cycle

Tact control terminal

Tlo logic out terminal

Tms master signal terminal

Tsc slave clock terminal

Tsd slave data terminal

TSD temperature protection function

Tsig signal terminal

VIN power terminal

Vin power source

VREG 3 D supply power potential

X 1 , X 2 , X 3 response wait time

Y response start time

y 1 one cycle time

y 2 clock transmission time (clock pulse width)

y 3 response start transmission time

y 4 response start time

y 5 response end transmission time

y 6 response end time

y 7 data low time

y 8 data high time

y 9 clock reception time

y 10 data output time

y 11 read time

Z response end time