Charge pump circuit and phase-locked loop

This application is a Section 371 of International Application No. PCT/CN2018/075271, filed Feb. 5, 2018, which was published in the Chinese language on Aug. 16, 2018 under International Publication No. WO 2018/145612 A1, which claims priority under 35 U.S.C. § 119 to Chinese Patent Application No. 201710067159.9, filed on Feb. 7, 2017, the disclosures of which are incorporated herein by reference.

1. Technical Field

The invention relates to the technical field of integrated circuits, in particular to a low-voltage and wide-output range charge pump circuit and a phase-locked loop.

2. Description of Related Art

As one of the most popular frequency synthesizer structures in modern wireless communication system applications, a phase locked loop (PLL) can realize signal modulation and demodulation, as well as clock recovery, and generate local oscillator signals for carrier recovery of a mixer and a wireless receiver. A charge pump phase-locked loop (CP-PLL) has become the most common phase-locked loop circuit due to the characteristics of high speed and low noise. A charge pump (CP) circuit plays a very important role in a charge pump phase-locked loop. The main function of the charge pump circuit is to convert UP and DN pulse digital signals from a phase frequency detector (PFD) into analog voltage signals through a low-pass filter (LPF), and the analog voltage signals control the oscillation frequency of a voltage control oscillator (VCO). Therefore, the charge pump circuit has a very important influence on the characteristics of the whole phase-locked loop.

In a traditional circuit structure realizing the match of the charging current and the discharging current of a charge pump circuit, an operational amplifier circuit is used to hold the voltage between different nodes, which not only increases the complexity of the circuit, but also brings certain hidden dangers to the overall stability of the circuit. Meanwhile, in order to realize a large output voltage swing, the structure of an operational amplifier needs to realize rail-to-rail input and output characteristics, which further increases the design difficulty of the operational amplifier. Moreover, an operational amplifier working at low voltages often has low operating frequencies and cannot be applied to high-frequency fields.

In view of this, it is necessary to provide a charge pump circuit and a phase-locked loop which can realize the match of the charging current and the discharging current of a charge pump within a wide output voltage range without providing an additional operational amplifier and have simple circuit structure.

A charge pump circuit comprises a start module, a bias module, a current mirror module, a charging and discharging feedback control module and a charging and discharging matching module which are electrically connected in sequence; wherein

the start module is used for starting the bias module;

the bias module is used for generating constant bias current and outputting same to the current mirror module;

the current mirror module is used for receiving the bias current, and amplifying the bias current and outputting the amplified bias current in two paths;

the charging and discharging feedback control module is used for detecting the output voltage of a charge pump and controlling, according to the feedback of the output voltage, the charging current or the discharging current in the charging and discharging matching module, so as to suppress the mismatch between the charging current and the discharging current; and

the charging and discharging matching module is used for receiving an external charging control signal or an external discharging control signal, so as to charge or discharge the output load of the charge pump.

In one embodiment, the start module comprises transistors M 1 , M 2 , and M 3 , wherein the transistor M 1 and the transistor M 3 form a phase inverter, a source of the transistor M 1 and a source of the transistor M 2 are connected to a power end, and a drain of the transistor M 1 is connected to a gate of the transistor M 2 and then to a drain of the transistor M 3 ; a gate of the transistor M 1 is connected to a gate of the transistor M 3 , and a source of the transistor M 3 is grounded; and the gate of the transistor M 1 and a drain of the transistor M 2 are connected to the bias module.

In one embodiment, the bias module comprises transistors M 4 , M 5 , M 6 , M 7 , M 8 , M 9 , and M 10 , wherein a source of the transistor M 4 , a source of the transistor M 5 , and a source of the transistor M 10 are all connected to the power end; a gate of the transistor M 4 is connected to a gate of the transistor M 5 ; a drain of the transistor M 4 is connected to a gate of the transistor M 4 , the start module, a drain of the transistor M 6 , and a gate of the transistor M 10 ; a drain of the transistor M 5 is connected to a drain of the transistor M 7 and a gate of the transistor M 7 ; a gate of the transistor M 6 is connected to the gate of the transistor M 7 ; a source of the transistor M 6 is connected to a drain of the transistor M 8 ; a source of the transistor M 7 is connected to a drain of the transistor M 9 , a gate of the transistor M 9 , and the start module; a source of the transistor M 8 and a source of the transistor M 9 are both grounded; and a drain of the transistor M 10 is connected to a current mirror circuit.

In one embodiment, the bias module further comprises resistors R 1 , R 2 , and R 3 , wherein the source of the transistor M 8 is grounded via the resistor R 1 , and the resistors R 2 and R 3 are grounded in parallel and are pseudo resistors of the resistor R 1 .

In one embodiment, the current mirror module comprises transistors M 11 , M 12 , M 13 , M 14 , M 15 , M 16 , M 17 , M 18 , and M 19 , wherein a source of the transistor M 11 , a source of the transistor M 12 , a source of the transistor M 15 , a source of the transistor M 16 , and a source of the transistor M 17 are all grounded; a source of the transistor M 13 , a source of the transistor M 14 , a source of the transistor M 18 , and a source of the transistor M 19 are all connected to the power end; a drain of the transistor M 11 is connected to a gate of the transistor M 11 and the bias module; a gate of the transistor M 11 is connected to a gate of the transistor M 12 ; a drain of the transistor M 12 is connected to a drain of the transistor M 13 and a gate of the transistor M 13 ; the gate of the transistor M 13 is connected to a gate of the transistor M 14 ; a drain of the transistor M 14 is connected to a drain of the transistor M 15 , a gate of the transistor M 15 , and a gate of the M 17 ; the gate of the transistor M 15 is connected to a gate of the transistor M 16 ; a drain of the transistor M 16 is connected to a drain of the transistor M 18 and a gate of the transistor M 18 ; the gate of the transistor M 18 is connected to the gate of the transistor M 19 ; and a drain of the transistor M 17 and a drain of the transistor M 19 are connected to the charging and discharging matching module.

In one embodiment, the charging and discharging matching module comprises a charging unit and a discharging unit, wherein the charging unit receives the bias current in one of the paths output from the current mirror module, and outputs the charging current according to the charging control signal to charge an output load of the charge pump; and the discharging unit receives the bias current in another of the paths output from the current mirror module, and outputs the discharging current according to the discharging control signal to discharge the output load of the charge pump.

In one embodiment, the charging unit comprises transistors M 20 , M 21 , M 22 , M 23 , and M 24 , wherein a source of the transistor M 20 , a drain and a source of the transistor M 21 , and a source of the transistor M 22 are all connected to the power end; a gate of the transistor M 20 is grounded, and a drain of the transistor M 20 is connected to a source of the transistor M 23 and the charging and discharging feedback control module; a gate of the transistor M 21 is connected to a gate of the transistor M 23 and a gate of the transistor M 24 ; a gate of the transistor M 22 receives the charging control signal, and a drain of the transistor M 22 is connected to a source of the transistor M 24 ; a drain of the transistor M 23 is connected to a gate of the transistor M 23 and the current mirror module; and a drain of the transistor M 24 is connected to the output load of the charge pump.

The discharging unit comprises transistors M 25 , M 26 , M 27 , M 28 , and M 29 , wherein a drain of the transistor M 25 is connected to a gate of the transistor M 25 and the current mirror module; a gate of the transistor M 25 is connected to a drain of the transistor M 25 , a gate of the transistor M 26 , and a gate of the transistor M 28 ; a source of the transistor M 25 is connected to a drain of the transistor M 27 and the charging and discharging feedback control module; a drain of the transistor M 26 is connected to the output load of the charge pump, and a source of the transistor M 26 is connected to a drain of the transistor M 29 ; a gate of the transistor M 27 is connected to the power end, and a source of the transistor M 27 , a source and a drain of the transistor M 28 , and a source of the transistor M 29 are all grounded; and a gate of the transistor M 29 receives the discharging control signal.

In one embodiment, the charging and discharging feedback control module comprises a charging feedback unit and a discharging feedback unit; the charging feedback unit is connected to the charging unit and the output load of the charge pump; the charging feedback unit is used for detecting the output voltage of the charge pump and controlling, according to the feedback of the output voltage, the discharging current output by the discharging unit, so as to suppress the mismatch between the charging current and the discharging current; the discharging feedback unit is connected to the discharging unit and the output load of the charge pump; and the discharging feedback unit is used for detecting the output voltage of the charge pump and controlling, according to the feedback of the output voltage, the charging current output by the charging unit, so as to suppress the mismatch between the charging current and the discharging current.

In one embodiment, the charging feedback unit comprises a transistor M 30 , and the discharging feedback unit comprises a transistor M 31 , wherein a source of the transistor M 30 is connected to the power end, a drain of the transistor M 30 is connected to the charging unit, and a gate of the transistor M 30 is connected to the output load of the charge pump; and a source of the transistor M 31 is grounded, a drain of the transistor M 31 is connected to the discharging unit, and a gate of the transistor M 31 is connected to the output load of the charge pump.

The above charge pump circuit comprises the start module, the bias module, the current mirror module, the charging and discharging feedback control module and the charging and discharging matching module which are electrically connected in sequence, According to the detected output voltage of the charge pump, the charging current or the discharging current in the charging and discharging matching module can be controlled by a charging feedback circuit; so as to suppress the mismatch between the charging current and the discharging current, thus maintaining the match of the charging current and the discharging current of the charge pump within a wide output voltage range. Meanwhile, the charge pump circuit in the embodiment of the invention has a simple structure and is suitable for a low-voltage working environment.

In addition, the invention provides a phase-locked loop which comprises the charge pump circuit.

FIG. 1 is a structure block diagram of a charge pump circuit in one embodiment;

FIG. 2 is a schematic circuit diagram of a charge pump circuit in one embodiment;

FIG. 3 is a matching simulation diagram of the charging current and the discharging current of a charge pump in one embodiment;

FIG. 4 is a transient simulation diagram of a charge pump charging at 100 MHz in one embodiment; and

FIG. 5 is a transient simulation diagram of a charge pump discharging at 100 MHz in one embodiment.

In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the accompanying drawings. However, the present invention may be implemented in many different ways and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding to the disclosure of the present invention more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. As used herein, the term “and/or” includes any and all combinations of one or more related listed items.

FIG. 1 is a structure block diagram of a charge np circuit in one embodiment. A charge pump circuit comprises a start module 10 , a bias module 20 , a current mirror module 30 , a charging and discharging feedback control module 40 and a charging and discharging matching module 50 which are electrically connected in sequence.

The start module 10 is used for starting the bias module 20 ; the bias module 20 is used for generating constant bias current and outputting same to the current mirror module 30 ; the current mirror module 30 is used for receiving the bias current, and amplifying the bias current and outputting the amplified bias current in two paths; the charging and discharging feedback control module 40 is used for detecting the output voltage of a charge pump and controlling, according to the feedback of the output voltage, the charging current or the discharging current in the charging and discharging matching module 50 , so as to suppress the mismatch between the charging current and the discharging current; and the charging and discharging matching module 50 is used for receiving an external charging control signal or an external discharging control signal, so as to charge or discharge the output load of the charge pump.

The above charge pump circuit comprises the start module 10 , the bias module 20 , the current mirror module 30 , the charging and discharging feedback control module 40 and the charging and discharging matching module 50 which are electrically connected in sequence. According to the detected output voltage of the charge pump, the Charging current or the discharging current in the charging and discharging matching module 50 can be controlled by a charging feedback circuit, so as to suppress the mismatch between the charging current and the discharging current, thus maintaining the match of the charging current and the discharging current of the charge pump within a wide output voltage range. Meanwhile, the charge pump circuit it in the embodiment of the invention has a simple structure and is suitable for a low-voltage working environment.

In one embodiment, referring to FIG. 2 , the start module 10 comprises transistors M 1 , M 2 , and M 3 . The transistors are MOS transistors, the transistors M 1 and M 2 are P-channel MOS transistors (PMOS), and the transistor M 3 is an N-channel MOS transistor (NMOS). The transistor M 1 and the transistor M 3 form a phase inverter, a source of the transistor M 1 and a source of the transistor M 2 are connected to a power end, and a drain of the transistor M 1 is connected to a gate of the transistor M 2 and then to a drain of the transistor M 3 . A gate of the transistor M 1 is connected to a gate of the transistor M 3 , and a source of the transistor M 3 is grounded. The gate of the transistor M 1 and a drain of the transistor M 2 are respectively connected to the bias module 20 .

When a power supply is turned on, all the transistors are in the off state, a node A is at a high level and a node C is at a low level. After the start module 10 is added, the transistor M 1 and the transistor M 2 form a phase inverter, a node B is at a low level, the MOS transistor M 2 is turned on to charge the node C, so the level of the node C rises, and the bias module 20 starts to deviate from a zero point. When the bias module 20 reaches a stable state, the node A is at a low level, the node B is at a high level, the MOS transistor M 2 is turned off, and the start module 10 no longer affects the bias module 20 .

In one embodiment, the bias module 20 adopts a structure of a non-linear reference bias module 20 , and comprises transistors M 4 , M 5 , M 6 , M 7 , M 8 , M 9 and M 10 . The transistors are MOS transistors, the transistors M 4 , M 5 , and M 10 are P-channel MOS transistors (PHOS), and the transistors M 6 , M 7 , M 8 , and M 9 are N-channel MOS transistors (NMOS).

A source of the transistor M 4 , a source of the transistor M 5 , and a source of the transistor M 10 are all connected to the power end. A gate of the transistor M 4 is connected to a gate of the transistor M 5 . A drain of the transistor M 4 is connected to a gate of the transistor M 4 , the start module 10 , a drain of the transistor M 6 , and a gate of the transistor M 10 . A drain of the transistor M 5 is connected to a drain of the transistor M 7 and a gate of the transistor M 7 . A gate of the transistor M 6 is connected to the gate of the transistor M 7 , and a source of the transistor M 6 is connected to a drain of the transistor M 8 . A source of the transistor M 7 is connected to a drain of the transistor M 9 , a gate of the transistor M 9 , and the start module 10 . A source of the transistor M 8 and a source of the transistor M 9 are both grounded. A drain of the transistor M 10 is connected to a current mirror circuit. A stable bias voltage is generated by the bias module 20 , and then the MOS transistors in the bias module 20 are controlled to generate a constant bias current, wherein the constant bias current generated by the bias module 20 is about 10 uA.

In one embodiment, the bias module 20 further comprises resistors R 1 , R 2 , and R 3 , wherein the source of the transistor M 8 is grounded via the resistor R 1 , and the resistors R 2 and R 3 are connected in parallel and are pseudo resistors of the resistor R 1 . When the layout is realized, the resistors R 2 and R 3 are placed on both sides of the resistor R 1 , so that the physical environment around the resistor R 1 is uniform, and the influence of process fluctuation on the resistance value of the resistor R 1 is reduced.

In one embodiment, the current mirror module 30 comprises transistors M 11 , M 12 , M 13 , M 14 , M 15 , M 16 , M 17 , M 18 , and M 19 . The transistors are MOS transistors, the transistors M 13 , M 14 , M 18 , and M 19 are P-channel MOS transistors (PMOS), and the transistors M 11 , M 12 , M 15 , M 16 , and M 17 are N-channel MOS transistors (NMOS). The transistor M 11 and the transistor M 12 form a first current mirror pair, the transistor M 13 and the transistor M 14 form a second current mirror pair, the transistor M 15 , the transistor M 16 , and the transistor M 17 form a third current mirror pair, and the transistor M 18 and the transistor M 19 form a fourth current mirror pair.

A source of the transistor M 11 , a source of the transistor M 12 , a source of the transistor M 15 , a source of the transistor M 16 , and a source of the transistor M 17 are all grounded. A source of the transistor M 13 , a source of the transistor M 14 , a source of the transistor M 18 , and a source of the transistor M 19 are all connected to the power end. A drain of the transistor M 11 is connected to a gate of the transistor M 11 and the drain of the transistor M 10 , and a gate of the transistor M 11 is connected to a gate of the transistor M 12 . A drain of the transistor M 12 is connected to a drain of the transistor M 13 and a gate of the transistor M 13 . The gate of the transistor M 13 is connected to a gate of the transistor M 14 . A drain of the transistor M 14 is connected to a drain of the transistor M 15 , a gate of the transistor M 15 , and a gate of the M 17 . The gate of the transistor M 15 is connected to a gate of the transistor M 16 . A drain of the transistor M 16 is connected to a drain of the transistor M 18 and a gate of the transistor M 18 . The gate of the transistor M 18 is connected to the gate of the transistor M 19 . A drain of the transistor M 17 and a drain of the transistor M 19 are respectively connected to the charging and discharging matching module 50 .

In the third current mirror pair, the transistor M 16 is a mirror image of the transistor M 15 , and the transistor M 17 is another mirror image of the transistor M 15 . After the bias current output by the bias module 20 passes through the first current mirror pair and the second current mirror pair, the bias module 20 is divided into two paths by the third current mirror, one path is amplified into 1 MA constant current by the transistor M 16 and the fourth current mirror pair and then output to the charging and discharging matching module 50 , and the other path is amplified into 1 MA constant current by the transistor M 17 and then output to the charging and discharging matching module 50 . The constant current generated by the bias module 20 is about 10 uA. After passing through the four current mirror pairs: the transistors M 11 /M 12 , the transistors M 13 /M 14 , the transistors M 15 /M 16 /M 17 , and the transistors M 18 /M 19 , the 10 uA constant current can be amplified to about 500 uA, thus realizing current amplification.

In one embodiment, the charging and discharging matching module 50 comprises a charging unit 510 and a discharging unit 520 , wherein the charging unit receives the bias module 20 output by one path of the current mirror module 30 , and outputs the charging current according to the charging control signal to charge an output load of the charge pump; and the discharging unit receives the bias module 20 output by the other path of the current mirror module 30 , and outputs the discharging current according to the discharging control signal to discharge the output load of the charge pump.

In one embodiment, the charging unit 510 comprises transistors M 20 , M 21 , M 22 , M 23 , and M 24 . The discharging unit 520 comprises transistors M 25 , M 26 , M 27 , M 28 , and M 29 . The transistors are MOS transistors, the transistors M 20 , M 21 , M 22 , M 23 , and M 24 are P-channel MOS transistors (PMOS), and the transistors M 25 , M 26 , M 27 , M 28 , and M 29 are N-channel MOS transistors (NMOS).

A source of the transistor M 20 , a drain and a source of the transistor M 21 , and a source of the transistor M 22 are all connected to the power end; a gate of the transistor M 20 is grounded, and a drain of the transistor M 20 is connected to a source of the transistor M 23 and the charging and discharging feedback control module 40 .

A gate of the transistor M 21 is connected to a gate of the transistor M 23 and a gate of the transistor M 24 . A gate of the transistor M 22 receives the charging control signal (UP), and a drain of the transistor M 22 is connected to a source of the transistor M 24 . A drain of the transistor M 23 is connected to a gate of the transistor M 23 and a drain of the transistor M 17 . A drain of the transistor M 24 is connected to the output load of the charge pump. A drain of the transistor M 25 is connected to a gate of the transistor M 25 and a drain of the transistor M 19 ; a gate of the transistor M 25 is connected to a drain of the transistor M 25 , a gate of the transistor M 26 , and a gate of the transistor M 28 ; and a source of the transistor M 25 is connected to a drain of the transistor M 27 and the charging and discharging feedback control module 40 . A drain of the transistor M 26 is connected to the output load of the charge pump, and a source of the transistor M 26 is connected to a drain of the transistor M 29 . A gate of the transistor M 27 is connected to the power end, and a source of the transistor M 27 , a source and a drain of the transistor M 28 , and a source of the transistor M 29 are all grounded. A gate of the transistor M 29 receives the discharging control signal (DN).

In one embodiment, the charging and discharging feedback control module 40 comprises a charging feedback unit 410 and a discharging, feedback unit 420 . The charging feedback unit 410 is connected to the charging unit 510 and the output load of the charge pump; the charging feedback unit 410 is used for detecting the output voltage of the charge pump and controlling, according to the feedback of the output voltage, the discharging current output by the discharging unit 520 , so as to suppress the mismatch between the charging current and the discharging current. The discharging feedback unit 420 is connected to the discharging unit 520 and the output load of the charge pump; and the discharging feedback unit 420 is used for detecting the output voltage of the charge pump and controlling, according to the feedback of the output voltage, the charging current output by the charging unit 510 , so as to suppress the mismatch between the charging current and the discharging current.

In one embodiment, the charging feedback unit 410 comprises a transistor M 30 , the transistor M 30 is a P-channel MOS transistor (PMOS), the discharging feedback unit 420 comprises a transistor M 31 , and the transistor M 31 is an N-channel MOS transistor (NMOS). A source of the transistor M 30 is connected to the power end, a drain of the transistor M 30 is connected to a drain of the transistor M 20 and a source of the transistor M 23 , and a gate of the transistor M 30 is connected to the output load of the charge pump. A source of the transistor M 31 is grounded, a drain of the transistor M 31 is connected to a source of the transistor M 25 and a drain of the transistor M 27 , and a gate of the transistor M 31 is connected to the output load of the charge pump.

Specifically, the charging control signal UP controls the switching MOS transistor M 22 in the charging unit 510 , and the discharging control signal IA controls the switching MOS transistor M 26 in the discharging unit 520 . When the charging control signal UP and the discharging control signal IA are both at high levels, the charging unit 510 and the discharging unit 520 form a loop. The charging and discharging feedback control module 40 detects the output voltage OUT of the charge pump and feeds the detected output voltage back to the transistor M 30 of the charging feedback unit 410 or the transistor M 31 of the discharging feedback unit 420 , thereby controlling the charging and discharging matching module 50 to realize matching within a wide output range.

Further, when the output voltage OUT rises, the transistor M 30 of the charging feedback unit 410 enters a deep triode region, and the equivalent on-resistance decreases, reducing the current mirrored to an output branch (the transistor M 26 and the transistor M 29 ) in the discharging unit 520 , thus reducing the mismatch between the charging current and the discharging current. When the output voltage OUT decreases, the transistor M 31 of the discharging feedback unit 420 enters the deep triode region, and the equivalent on-resistance decreases, reducing the current mirrored to an output branch (the transistor M 22 and the transistor M 24 ) in the charging unit 510 , thus reducing the mismatch between the charging current and the discharging current. Through the above charge pump circuit, the match of the charging current and the discharging current of the charge pump within a wide output voltage range can be realized. Meanwhile, the charge pump circuit in the embodiment of the invention has a simple structure and is suitable for a low-voltage working environment.

FIG. 3 is a matching simulation diagram of the charging current and the discharging current of the charge pump, wherein the solid black line represents the relationship between the charging current and the output voltage, the dotted black line represents the relationship between the discharging current and the output voltage, and the solid gray line represents the difference between the charging current and the discharging current within the whole output swing range. As can be seen from FIG. 3 , when the supply voltage is 1 V, the output voltage swings from 113 mV to 870 mV, and the difference between the charging current and the discharging current is less than 4%. FIG. 4 is a transient simulation diagram of the charge pump charging at 100 MHz, and FIG. 5 is a transient simulation diagram of the charge pump discharging at 100 MHz. As can be seen from FIG. 4 and FIG. 5 , when the charging control signal or the discharging control signal is at 100 MHz, the transient simulation of charging and discharging of the charge pump has no burr phenomenon. A traditional circuit using an operational amplifier to expand the matching of the charging current and the discharging current of a charge pump has a complex structure, and the working frequency range thereof is affected by the bandwidth of the operational amplifier, so the circuit cannot work at high frequencies. In the embodiment of the invention, the charge pump circuit can work within a high frequency range. Even without an operational amplifier, the matching of the charging current and the discharging current of the charge pump can be maintained within a wide output voltage range.

In addition, a phase-locked loop (not shown in the figures) is also provided, and comprises the charge pump circuit in any of the above embodiments. Since the charge pump circuit in any of the above embodiments is arranged in the phase-locked loop, the matching of the charging current and the discharging current of the charge pump can be maintained within a wide output voltage range. In one embodiment, the charge pump circuit is suitable for a low-voltage and low-power phase-locked loop system for its simple structure.

The technical features of the above-described embodiments can be combined freely, and not all possible combinations of the technical features in the above-described embodiments are described for simplicity of description. However, as long as there is no contradiction between the combinations of these technical features, they should be considered within the scope of this specification.

The above-mentioned embodiments only describe several implementations of the present invention in a specific and detailed way, but it is not to be understood as limiting the scope of the invention. It should be noted that a person of ordinary skill in the art can make several modifications and improvements without departing from the spirit of the present invention, which all belong to the scope of this invention, Therefore, the scope of protection of the patent for the invention shall be subject to the appended claims.