High-speed low-power-consumption dynamic comparator

The present application is a 35 U.S.C. § 371 National Phase conversion of International (PCT) Patent Application No. PCT/CN2016/089044, filed on Jul. 7, 2016, which further claims benefit of Chinese Patent Application No. 201510618825.4, filed on Sep. 25, 2015, the disclosure of which is incorporated by reference herein. The PCT International Patent Application was filed and published in Chinese.

The present invention belongs to the technical field of analog or digital-analog hybrid integrated circuits, and particularly, to a high-speed low-power-consumption dynamic comparator.

In recent years, with the continuous development of the integrated circuit manufacturing technique, feature sizes of CMOS devices have been continuously decreased, and operating voltages of integrated circuits have been continuously reduced as well. Under a deep submicron process, an operating speed of analog-to-digital converters has been greatly improved. Meanwhile, the power consumption is further reduced. However, the performance of a comparator as a core component of the analog-to-digital converter becomes a bottleneck for high-speed low-power-consumption designs. It is difficult for traditional comparators to meet the requirements of speed, power consumption and low power supply voltage simultaneously.

In view of this, the present invention provides a high-speed low-power-consumption dynamic comparator that still maintains a very low static power consumption while implementing a high-speed operation. Meanwhile, as a power supply voltage decreases, the comparator provided by the present invention still maintains a relatively high comparison speed compared with the above-described conventional comparator.

In order to achieve the above object, the present invention provides the following technical solution: a high-speed low-power-consumption dynamic comparator includes a first NMOS transistor, a second NMOS transistor, a sixth NMOS transistor, a delay unit, a first inverter, a second inverter, an XNOR gate, an AND gate and a latch, wherein the latch includes a first control end, a second control end, a third control end, a first output end, a second output end and a power supply end; the gate of the first NMOS transistor is connected with a first input signal, the gate of the second NMOS transistor is connected with a second input signal, and the source of the first NMOS transistor and the source of the second NMOS transistor are respectively connected with the drain of the sixth NMOS transistor, and the source of the sixth NMOS transistor is grounded; the drain of the first NMOS transistor is respectively connected with the input end of the second inverter and the second output end of the latch; the drain of the second NMOS transistor is respectively connected with the input end of the first inverter and the first output end of the latch; the output end of the first inverter is connected with one of input ends of the XNOR gate, the output end of the second inverter is connected with the other one of the input ends of the XNOR gate, the output end of the XNOR gate is connected with one of input ends of the AND gate, the input end of the delay unit is connected with the other one of the input ends of the AND gate, and the output end of the AND gate is connected with the gate of the sixth NMOS transistor; and the output end of the delay unit is connected with the third control end, the input end of the delay unit is respectively connected with the first control end and the second control end, respectively, and the power supply end is connected with a Vdd.

Further, the latch includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, wherein the drain of the first NMOS transistor is respectively connected with the drain of the fourth NMOS transistor, the drain of the first PMOS transistor, the drain of the second PMOS transistor, the gate of the fifth NMOS transistor and the gate of the third PMOS transistor; the drain of the second NMOS transistor is connected with the drain of the fifth NMOS transistor, the drain of the third PMOS transistor, the drain of the fourth PMOS transistor, the gate of the fourth NMOS transistor and the gate of the second PMOS transistor, respectively; the source of the first PMOS transistor, the source of the second PMOS transistor, the source of the third PMOS transistor and the source of the fourth PMOS transistor are respectively connected with the Vdd; and the gate of the first PMOS transistor and the gate of the fourth PMOS transistor are respectively connected with the input end of the delay unit, the output end of the delay unit is connected with the gate of the third NMOS transistor, and the drain of the third NMOS transistor is respectively connected with the source of the fourth NMOS transistor and the source of the fifth NMOS transistor; and the source of the third NMOS transistor is grounded.

Due to the adoption of the above technical solution, the present invention has the following beneficial technical effects.

1. An output end Dip/Din of an input transistor is respectively connected to the drains of the NMOS transistors P 4 and P 5 , and connected to the drains of the PMOS transistors P 7 and P 8 , so that the advantage of high speed of this latch is fully exerted.

2. The output signal is generated through the XNOR gate from comparator output signals Dp and Dn, and from this output signal and the control signal clk 1 , the control signal of the NMOS transistor P 10 is generated through the AND gate, so that the problem of static power consumption in the conventional comparator is solved.

3. The present invention is simple in structure, has no obvious area increase compared with the conventional comparator, and achieves the purposes of high speed and low power consumption.

In order to make objects, technical solutions and advantages of the present invention more comprehensible, the present invention will be further described in detail below with reference to accompanying drawings in which:

FIG. 1 is a schematic view showing a structure of a high-speed low-offset dynamic comparator;

FIG. 2 is a schematic view showing a structure of a high-speed low-noise dynamic comparator;

FIG. 3 is a schematic view showing a structure of a low-power-consumption dynamic comparator;

FIG. 4 is a schematic view showing a structure of a high-speed low-power-consumption dynamic comparator;

FIG. 5 is a comparison view of comparison time of a comparator over an input signal;

FIG. 6 is a comparison view of power consumption of a comparator over a common mode voltage; and

FIG. 7 is a comparison view of comparison time of a comparator over a power supply voltage.

Preferred embodiments of the present invention will be described in detail below with reference to accompanying drawings. It should be understood that the preferred embodiments are only intended to illustrate the present invention, but not limit the scope of protection of the present invention.

In order to understand the technical solution of the present invention in more detail, operating principles and advantages and disadvantages of several conventional comparators will be firstly analyzed.

FIG. 1 shows a schematic view showing a structure (referred to as a structure [1]) of a high-speed low-offset dynamic comparator. When a control signal clk 1 is at a low level, a clk 2 as a delayed signal of the clk 1 is at a low level as well, NMOS transistors M 7 /M 8 /M 15 are in an off state, PMOS transistors M 11 /M 14 are in an on state, comparator output signals Dp and Dn are at a low level through inverters I 1 /I 2 , and the comparator is in a reset state; after the clk 1 /clk 2 becomes a high level, the NMOS transistors M 7 /M 8 /M 15 are in an on state, and a latch composed of NMOS transistors M 9 /M 10 and PMOS transistors M 12 /M 13 rapidly amplifies a voltage difference between Tip and Tin and enters a latched state. The structure [1] has the advantages of smaller offset and lower noise due to the adoption of an inverter input structure compared with a conventional NMOS input structure. However, the structure [1] has the disadvantages that the output ends Tip and Tin of the input stage inverter are connected to sources of M 9 /M 10 of the latch structure, so that only the M 9 and the M 10 operate while the M 12 and the M 13 do not operate at the beginning of establishing a positive feedback by the latch structure, this latching principle does not maximize the advantages of the latch structure, making the comparator slow. Meanwhile, since an input stage employs the inverter input structure, when the structure is in the latched state, the input stage still has a static current, so that there is static power consumption.

FIG. 2 shows a schematic view showing a structure (referred to as a structure [2]) of a high-speed low-noise dynamic comparator. When a control signal clk 1 is at a low level, a NMOS transistor M 3 is in an off state, a NMOS transistor M 10 is in an on state, PMOS transistors M 6 /M 9 is in an on state, comparator output signals Dp and Dn are at a low level through inverters I 1 /I 2 , and the comparator is in a reset state; after the clk 1 becomes a high level, the M 10 is in an off state, the M 3 is in an on state, and a latch composed of NMOS transistors M 4 /M 5 and PMOS transistors M 7 /M 8 rapidly amplifies a voltage difference between Bip and Bin and enters a latched state. It should be noted that the output ends Bip and Bin of the input stage in FIG. 2 are respectively connected with drains of the M 4 and a M 5 , so that the M 4 /M 5 and the M 7 /M 8 simultaneously operate at the beginning of establishing a positive feedback by a latch structure, this latching principle maximizes the advantages of the latch structure, enabling the comparator to be rapidly enter the latched state. However, the disadvantages of the comparator shown in FIG. 2 are also obvious, that is, since the M 10 , the M 6 and the M 9 simultaneously enter an on state from their reset state, such a structure has a great static power consumption.

FIG. 3 shows a schematic view showing a structure (referred to as a structure [3]) of a low-power-consumption dynamic comparator. When a control signal clk 1 is at a low level, a clk 2 as a delayed signal of the clk 1 is at a low level as well, NMOS transistors M 3 /M 4 /M 11 are in an off state, PMOS transistors M 7 /M 10 is in an on state, comparator output signals Dp and Dn are at a low level through inverters I 1 /I 2 , and the comparator is in a reset state. After the clk 1 becomes a high level, the clk 2 will maintain a low level for a period of time, at this time, the M 11 is in an on state, the M 3 /M 4 is kept to be in an off state, there is a voltage difference between Aip and Ain, and input transistors M 1 /M 2 are in a saturated state, which helps inhibition of noise; and subsequently, the clk 2 also becomes a high level, and a latch composed of NMOS transistors M 5 /M 6 and PMOS transistors M 8 /M 9 rapidly amplifies the voltage difference between the Aip and the Ain and enters a latched state. The structure shown in FIG. 3 has the advantages of smaller equivalent input noise and no static power consumption in both reset and latched states, but disadvantage thereof is similar to that of the structure shown in FIG. 1 , that is, the comparator is low in speed.

A schematic view showing a structure of a high-speed low-power-consumption dynamic comparator proposed by the present invention is shown in FIG. 4 .

A high-speed low-power-consumption dynamic comparator includes a first NMOS transistor P 1 , a second NMOS transistor P 2 , a sixth NMOS transistor P 10 , a delay unit B 1 , a first inverter I 1 , a second inverter I 2 , an XNOR gate, an AND gate and a latch, wherein the latch includes a first control end, a second control end, a third control end, a first output end (outputs a first output signal), a second output end (outputs a second output signal) and a power supply end; the gate of the first NMOS transistor P 1 is connected with a first input signal (Vinp), the gate of the second NMOS transistor P 2 is connected with a second input signal (Vinn), and the source of the first NMOS transistor P 1 and the source of the second NMOS transistor P 2 are respectively connected with the drain of the sixth NMOS transistor P 10 , and the source of the sixth NMOS transistor P 10 is grounded; the drain of the first NMOS transistor P 1 is respectively connected with the input end of the second inverter I 2 and the second output end of the latch; the drain of the second NMOS transistor P 2 is respectively connected with the input end of the first inverter I 1 and the first output end of the latch; the output end of the first inverter I 1 is connected with one of input ends of the XNOR gate, the output end of the second inverter I 2 is connected with the other one of the input ends of the XNOR gate, the output end of the XNOR gate is connected with one of input ends of the AND gate, the input end of the delay unit B 1 is connected with the other one of the input ends of the AND gate, and the output end of the AND gate is connected with the gate of the sixth NMOS transistor P 10 ; and the output end of the delay unit B 1 is connected with the third control end, the input end of the delay unit is respectively connected with the first control end and the second control end, respectively, and the power supply end is connected with a Vdd.

The latch includes a third NMOS transistor P 3 , a fourth NMOS transistor P 4 , a fifth NMOS transistor P 5 , a first PMOS transistor P 6 , a second PMOS transistor P 7 , a third PMOS transistor P 8 and a fourth PMOS transistor P 9 , wherein the drain of the first NMOS transistor P 1 is respectively connected with the drain of the fourth NMOS transistor P 4 , the drain of the first PMOS transistor P 6 , the drain of the second PMOS transistor P 7 , the gate of the fifth NMOS transistor P 5 and the gate of the third PMOS transistor P 8 ; the drain of the second NMOS transistor P 2 is connected with the drain of the fifth NMOS transistor P 5 , the drain of the third PMOS transistor P 8 , the drain of the fourth PMOS transistor P 9 , the gate of the fourth NMOS transistor P 4 and the gate of the second PMOS transistor P 7 , respectively; the source of the first PMOS transistor P 6 , the source of the second PMOS transistor P 7 , a source of the third PMOS transistor P 8 and a source of the fourth PMOS transistor P 9 are respectively connected with the Vdd; and the gate of the first PMOS transistor P 6 and the gate of the fourth PMOS transistor P 9 are respectively connected with the input end of the delay unit B 1 , the output end of the delay unit B 1 is connected with the gate of the third NMOS transistor P 3 , and the drain of the third NMOS transistor P 3 is respectively connected with the source of the fourth NMOS transistor P 4 and the source of the fifth NMOS transistor P 5 ; and the source of the third NMOS transistor P 3 is grounded.

In this embodiment, the first PMOS transistor and the fourth PMOS transistor are pull-up PMOS transistors, and the third NMOS transistor and the sixth NMOS transistor are pull-down NMOS transistors.

In this embodiment, an output signal Dp is generated from a first output signal of the latch through the first inverter I 1 , an output signal Dn is generated from a second output signal of the latch through the second inverter I 2 , an output signal is generated from Dp and Dn through the XNOR gate, this output signal and the control signal clk 1 are taken as input signals of the AND gate, the output signal of the AND gate controls the gate of the P 10 , and the delayed signal clk 2 of the clk 1 is generated from the clk 1 through the delay unit B 1 .

The comparator shown in FIG. 4 has two operating states, one is a reset state and the other is a latched state. When the comparator is in the reset state, the control signals clk 1 and clk 2 are at a low level, the NMOS transistors P 3 and P 10 are both in an off state, the PMOS transistors P 6 and P 9 are in an on state, and a signal Dip generated by the first NMOS transistor P 1 and a signal Din generated by the second NMOS transistor P 2 are pulled up to the power supply voltage Vdd, and the comparator output signals Dp and Dn are at a low level through the inverters I 1 and I 2 ; when the comparator enters the latched state, the control signal clk 1 becomes a high level, the clk 2 as the delayed signal of the clk 1 temporarily maintains a low level, at this time, the P 10 is in an on state, the P 3 is still in an off state, the Dip and the Din start to have a voltage difference therebetween, the P 1 and the P 2 are in a saturated state, which helps inhibition of the equivalent input noise of the comparator. After a certain delay, the control signal clk 2 also becomes a high level, and the voltage difference between the Dip and the Din causes the latch structure composed of the P 6 , the P 7 , the P 8 and the P 9 to quickly enter the latched state, and the comparison is completed, so that the purpose of high-speed operation is achieved. At this time, one of the comparator output signals Dp and Dn is at a high level and the other one is at a low level, they turn off the P 10 through the XNOR gate, so that the comparator has no static power consumption in the reset and latched states, so that the purpose of low power consumption is achieved. By way of the above analysis, this structure achieves purposes of both high speed and low power consumption.

On the other hand, as the power supply voltage decreases, the structure of the comparator proposed by the present invention has a higher speed than the above-described conventional structure. The reason is that the structure of the comparator of the present invention saves one source-drain voltage difference Vbs of the NMOS transistor in the latch structure with respect to the structures shown in FIG. 2 and FIG. 3 , so that the structure of the comparator proposed by the present invention has a speed advantage in the application of a low power supply voltage.

In order to further verify the above advantages of the present invention, the above various structures are carefully designed in a 65 nm CMOS process. The above four structures employ the same input/output transistor size, the latch structures also employ the same size, and load capacitances are 15 fF.

A clock frequency is 1.8 GHz, a power supply voltage is 1.2V, and a common mode voltage is 0.6V. When |Dp−Dn|=0.6V, it is considered that the comparator completes the comparison. Comparison curves of comparison time of comparators adopting the above four structures over an input differential signal ΔVin is shown in FIG. 5 .

A clock frequency is 1.8 GHz, and a power supply voltage is 1.2V. When |Dp−Dn|=0.6V, it is considered that the comparator completes the comparison. Comparison curves of power-consumption of comparators adopting the above four structures over a common mode voltage Vcm is shown in FIG. 6 .

A clock frequency is 0.4 GHz, and an input differential voltage ΔVin is 50 mV. When |Dp−Dn|=0.5 Vdd, it is considered that the comparator completes the comparison. Comparison curves of comparison time of comparators adopting the above four structures over a power supply voltage Vdd is shown in FIG. 7 .

The comparison of simulation results of several other indicators of the comparator is shown in the following table. As can be seen from the table, the present invention has several indicators in a medium range compared with the conventional several structures.

[1] [2] [3] in the table respectively represent FIG. 1 , FIG. 2 and FIG. 3 , and “proposed” represents the present invention.

It may be seen from the above simulation results that the structure of the high-speed low-power-consumption comparator proposed by the present invention has a speed increase of at least 30% and a power consumption reduction of at least 15% as compared with the conventional structure.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention. It is obvious that those skilled in the art may make various modifications and changes to the present invention without departing from the spirit and scope of the invention. In this way, it is intended that the present invention encompasses such modifications and variations if these modifications and variations of the present invention are intended to be included within the scope of the claims and equivalents thereof of the present invention.