Storage device and control method for controlling operations of the storage device

This application is a U.S. National Phase of International Patent Application No. PCT/JP2017/040401 filed on Nov. 9, 2017, which claims priority benefit of Japanese Patent Application No. JP 2016-251416 filed in the Japan Patent Office on Dec. 26, 2016. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety.

The present disclosure relates to a storage device that stores data and to a method of controlling such a storage device.

In recent years, for example, much focus has been placed on a nonvolatile memory device using a resistive random access memory that allows for performance of faster data access than a flash memory. For example, PTL1 discloses a storage device that writes the same data to a plurality of memory cells at the same time.

Patent Literature

PTL1: Japanese Unexamined Patent Application Publication No. 2006-323924.

Meanwhile, in the storage device, for example, high reliability is desired for a data write operation and a data read operation, and further improvement of reliability is expected.

It is desirable to provide a storage device and a control method that make it possible to increase reliability.

A storage device according to an embodiment of the present disclosure includes a first storage section, a first selection line driver, and a second selection line driver. The first storage section includes a plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines, a plurality of second wiring lines extending in a second direction that intersects with the first direction and including a plurality of third selection lines and a plurality of fourth selection lines, and a plurality of first memory cells each being inserted between a corresponding one of the plurality of first wiring lines and a corresponding one of the plurality of second wiring lines. The first selection line driver applies, to one or more selection lines of the plurality of first selection lines, a first voltage that is one of a first selection voltage and a second selection voltage, and applies, to one or more selection lines of the plurality of second selection lines, a second voltage that is one of the first selection voltage and the second selection voltage and is different from the first voltage. The second selection line driver applies, to one or more selection lines of the plurality of third selection lines, a third voltage that is one of the first selection voltage and the second selection voltage, and applies, to one or more selection lines of the plurality of fourth selection lines, a fourth voltage that is one of the first selection voltage and the second selection voltage and is different from the third voltage.

A control method according to an embodiment of the present disclosure includes: with respect to a first storage section that includes a plurality of first wiring lines, a plurality of second wiring lines, and a plurality of first memory cells, the plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines, the plurality of second wiring lines extending in a second direction that intersects with the first direction and including a plurality of third selection lines and a plurality of fourth selection lines, and the plurality of first memory cells each being inserted between a corresponding one of the plurality of first wiring lines and a corresponding one of the plurality of second wiring lines, applying a first voltage to one or more selection lines of the plurality of first selection lines while applying a second voltage to one or more selection lines of the plurality of second selection lines, the first voltage being one of a first selection voltage and a second selection voltage, and the second voltage being one of the first selection voltage and the selection voltage and being different from the first voltage; and applying a third voltage to one or more selection lines of the plurality of third selection lines while applying a fourth voltage to one or more selection lines of the plurality of fourth selection lines, the third voltage being one of the first selection voltage and the second selection voltage, and the fourth voltage being one of the first selection voltage and the second selection voltage and being different from the third voltage.

In the storage device and the control method according to the embodiments of the present disclosure, the first voltage is applied to the one or more selection lines of the plurality of first selection lines in the first storage section, and the second voltage is applied to the one or more selection lines of the plurality of second selection lines. In addition, the third voltage is applied to the one or more selection lines of the plurality of third selection lines, and the fourth voltage is applied to the one or more selection lines of the plurality of fourth selection lines. The first voltage is set to one voltage of the first selection voltage and the second selection voltage, and the second voltage is set to a voltage different from the first voltage of the first selection voltage and the second selection voltage. Likewise, the third voltage is set to one voltage of the first selection voltage and the second selection voltage, and the fourth voltage is set to a voltage different from the third voltage of the first selection voltage and the second selection voltage.

According to the storage device and the control method in the embodiments of the present disclosure, the first voltage is applied to the one or more selection lines of the plurality of first selection lines while the second voltage that is different from the first voltage is applied to the one or more selection lines of the plurality of second selection lines, and the third voltage is applied to the one or more selection lines of the plurality of third selection lines while the fourth voltage that is different from the third voltage is applied to the one or more selection lines of the plurality of fourth selection lines, thus making it possible to increase reliability. It is to be noted that the effects described here are not necessarily limitative, and may have any of the effects described in the present disclosure.

FIG. 1 is a block diagram that illustrates a configuration example of a storage device according to an embodiment of the present disclosure.

FIG. 2 is a configuration diagram that illustrates a configuration example of a memory array unit according to a first embodiment.

FIG. 3 is a perspective view that illustrates a configuration example of a memory array illustrated in FIG. 2 .

FIG. 4 is a circuit diagram that illustrates a configuration example of a memory cell illustrated in FIG. 2 .

FIG. 5 is a characteristic diagram that illustrates a characteristic example of a storage element illustrated in FIG. 4 .

FIG. 6 is a circuit diagram that illustrates a configuration example of a row selection line driver illustrated in FIG. 2 .

FIG. 7 is a circuit diagram that illustrates a configuration example of a column selection line driver illustrated in FIG. 2 .

FIG. 8 describes an example of a set operation in the memory array unit illustrated in FIG. 2 .

FIG. 9A describes an example of the set operation in the row selection line driver illustrated in FIG. 6 .

FIG. 9B describes an example of the set operation in the column selection line driver illustrated in FIG. 7 .

FIG. 10 describes an example of a reset operation in the memory array unit illustrated in FIG. 2 .

FIG. 11A describes an example of the reset operation in the row selection line driver illustrated in FIG. 6 .

FIG. 11B describes an example of the reset operation in the column selection line driver illustrated in FIG. 7 .

FIG. 12 describes an example of a sense operation in the memory array unit illustrated in FIG. 2 .

FIG. 13A describes an example of the sense operation in the row selection line driver illustrated in FIG. 6 .

FIG. 13B describes an example of the sense operation in the column selection line driver illustrated in FIG. 7 .

FIG. 14 is a circuit diagram that illustrates a configuration example of a row selection line driver according to a comparative example.

FIG. 15 is a circuit diagram that illustrates a configuration example of a column selection line driver according to the comparative example.

FIG. 16 describes an example of a set operation in a memory array unit according to the comparative example.

FIG. 17 describes another operation example of the set operation in the memory array unit illustrated in FIG. 2 .

FIG. 18A describes another operation example of the set operation in the row selection line driver illustrated in FIG. 6 .

FIG. 18B describes another operation example of the set operation in the column selection line driver illustrated in FIG. 7 .

FIG. 19 describes another operation example of the set operation in the memory array unit illustrated in FIG. 2 .

FIG. 20A describes another operation example of the set operation in the row selection line driver illustrated in FIG. 6 .

FIG. 20B describes another operation example of the set operation in the column selection line driver illustrated in FIG. 7 .

FIG. 21 describes another operation example of the set operation in the memory array unit according to the comparative example.

FIG. 22 is a circuit diagram that illustrates a configuration example of a row selection line driver according to a modification example.

FIG. 23 is a circuit diagram that illustrates a configuration example of a column selection line driver according to the modification example.

FIG. 24 is a circuit diagram that illustrates a configuration example of a row selection line driver according to another modification example.

FIG. 25 is a circuit diagram that illustrates a configuration example of a column selection line driver according to another modification example.

FIG. 26A describes an example of a set operation in the row selection line driver illustrated in FIG. 24 .

FIG. 26B describes an example of the set operation in the column selection line driver illustrated in FIG. 25 .

FIG. 27 is a circuit diagram that illustrates a configuration example of a row selection line driver according to another modification example.

FIG. 28 describes a region in which the driver illustrated in FIG. 27 is formed.

FIG. 29 is a configuration diagram that illustrates a configuration example of a storage device according to another modification example.

FIG. 30 is a configuration diagram that illustrates a configuration example of a memory array unit according to another modification example.

FIG. 31A is a circuit diagram that illustrates a configuration example of a decoder in a row selection line driver illustrated in FIG. 30 .

FIG. 31B is a circuit diagram that illustrates a configuration example of another decoder in the row selection line driver illustrated in FIG. 30 .

FIG. 32 describes an operation example of the decoder illustrated in FIG. 31A .

FIG. 33 is a circuit diagram that illustrates a configuration example of a decoder according to another comparative example.

FIG. 34 is a circuit diagram that illustrates a configuration example of a row selection line driver according to another modification example.

FIG. 35 describes an example of a set operation in a memory array unit according to another modification example.

FIG. 36 describes an example of the set operation in the row selection line driver illustrated in FIG. 34 .

FIG. 37 describes another operation example of the set operation in the memory array unit according to another modification example.

FIG. 38 describes an example of the set operation in the row selection line driver illustrated in FIG. 34 .

FIG. 39 is a circuit diagram that illustrates a configuration example of a column selection line driver according to another modification example.

FIG. 40 describes an example of the set operation in the memory array unit according to another modification example.

FIG. 41 describes an example of the set operation in the column selection line driver illustrated in FIG. 39 .

FIG. 42 describes another operation example of the set operation in the memory array unit according to another modification example.

FIG. 43 describes another operation example of the set operation in the column selection line driver illustrated in FIG. 39 .

FIG. 44 is a configuration diagram that illustrates a configuration example of a memory array unit according to a second embodiment.

FIG. 45 is a perspective view that illustrates a configuration example of a memory array illustrated in FIG. 44 .

FIG. 46 is a circuit diagram that illustrates a configuration example of a row selection line driver illustrated in FIG. 44 .

FIG. 47 is a circuit diagram that illustrates a configuration example of a column selection line driver illustrated in FIG. 44 .

FIG. 48 is a circuit diagram that illustrates a configuration example of a row selection line driver according to a modification example.

FIG. 49 is a circuit diagram that illustrates a configuration example of a column selection line driver according to a modification example.

In the following, some embodiments of the present disclosure are described in detail with reference to the drawings. It is to be noted that descriptions are given in the following order:

1. First Embodiment (Example of including two storage layers L 0 and L 1 )

2. Second Embodiment (Example of including four storage layers L 0 to L 3 )

1. First Embodiment

Configuration Example

FIG. 1 illustrates a configuration example of a storage device (a storage device 1 ) according to an embodiment. The storage device 1 is a nonvolatile storage device that stores data using a resistive random access storage element. It is to be noted that a method of controlling the storage device according to an embodiment of the present disclosure is embodied by the present embodiment, and thus is also described.

The storage device 1 selectively performs a data write operation or a data read operation on the basis of an instruction from a controller 99 . The controller 99 instructs the storage device 1 in response to a request from a host (not illustrated) to perform the data write operation or the data read operation. Specifically, in a case of instructing the storage device 1 to perform the data write operation, the controller 99 supplies a command signal CMD that instructs data writing, an address signal ADR, and a data signal DT. In this case, the storage device 1 writes data indicated by the data signal DT to an address indicated by the address signal ADR. In addition, in a case of instructing the storage device 1 to perform the data read operation, the controller 99 supplies a command signal CMD that instructs data reading, and the address signal ADR. In this case, the storage device 1 reads data from an address indicated by the address signal ADR and supplies the read data to the controller 99 as the data signal DT.

The storage device 1 includes an interface circuit IF and a plurality of banks BK (in this example, four banks BK 1 to BK 4 ). Each of the plurality of banks BK includes a plurality of memory array units MAU and a microcontroller MCON. In this example, the storage device 1 is a so-called semiconductor memory die that is formed on a semiconductor substrate.

The interface circuit IF performs communication with the controller 99 , and performs arbitration for the microcontroller MCON in each of the banks BK.

In each of the banks BK, as described later, each of the plurality of memory array units MAU includes a memory array MA that includes a plurality of memory cells MC. The plurality of memory array units MAU is arranged in a matrix in the semiconductor substrate. Each of the memory array units MAU is configured to allow for access in units of two bits. The microcontroller MCON controls an operation of the plurality of memory array units MAU on the basis of a control signal from the interface circuit IF. In access to each memory array unit MAU, the microcontroller MCON allow for access in units of two bits.

For example, in a case where each of the memory array units MAU has a storage capacity of 8M bits and each of the banks BK includes about 1000 (1k=32×32) memory array units MAU, each of the banks BK has a storage capacity of about 8 G bits. Thus, in this example, it is possible for the storage device 1 to have a storage capacity of 32 G bits. In this example, for example, it is possible for the controller 99 to access the storage device 1 in units of 2 k bits. The interface circuit IF selects one bank BK for one access on the basis of an instruction from the controller 99 . The microcontroller MCON in the selected bank BK accesses each of the 1 k memory array units MAU in units of two bits. Thus, it is possible for the controller 99 to write data to the storage device 1 in units of 2 k bits or read data from the storage device 1 in units of 2 k bits.

FIG. 2 illustrates a configuration example of the memory array unit MAU. The memory array unit MAU includes a memory array MA and an array driver AD. In this example, for convenience of description, the memory array unit MAU has a storage capacity of 32 bits.

The memory array MA includes a plurality of row selection lines RL (in this example, eight row selection lines RL 0 to RL 7 ), a plurality of column selection lines CL (in this example, four column selection lines CL 0 to CL 3 ), and a plurality of memory cells MC (in this example, 32 memory cells MC 0 to MC 31 ). One end of each of the row selection lines RL 0 to RL 7 and one end of each of the column selection lines CL 0 to CL 3 are coupled to the array driver AD. In FIG. 2 , the memory cells MC 0 to MC 31 are provided corresponding to 32 intersections between the row selection lines RL 0 to RL 7 and the column selection lines CL 0 to CL 3 .

It is to be noted that in this example, 32 (=8×4) memory cells MC are formed through providing the eight row selection lines RL 0 to RL 7 and the four column selection lines CL 0 to CL 3 . For example, as described above, in a case where the memory array unit MAU has a storage capacity of 8M bits, it is possible to form 8M (=2 k×4 k) memory cells MC, for example, through providing 4 k row selection lines RL and 2 k column selection lines CL.

FIG. 3 illustrates a configuration example of a memory array MA. The memory array MA is a so-called cross-point type memory array. The row selection lines RL 0 to RL 7 are formed to extend in an x-direction in an x-y plane parallel to a substrate surface S of a semiconductor. In addition, the column selection lines CL 0 to CL 3 are formed to extend in a y-direction in this x-y plane. The row selection lines RL 0 to RL 3 are formed in the same layer, and the column selection lines CL 0 to CL 3 are formed in a layer above the layer in which the row selection lines RL 0 to RL 3 are formed. Then, the row selection lines RL 4 to RL 7 are formed in a layer above the layer in which the column selection lines CL 0 to CL 3 are formed. Thus, in the memory array MA, the layer in which the row selection lines RL are formed and the layer in which the column selection lines CL are formed are alternately disposed.

In a storage layer L 0 interposed between the layer in which the four row selection lines RL 0 to RL 3 are formed and the layer in which the four column selection lines CL 0 to CL 3 are formed, 16 (=4×4) memory cells MC (MC 0 to MC 15 ) are formed. Likewise, in a storage layer L 1 interposed between the layer in which the four column selection lines CL 0 to CL 3 are formed and the layer in which the four row selection lines RL 4 to RL 7 are formed, 16 (=4×4) memory cells MC (MC 16 to MC 31 ) are formed.

FIG. 4 illustrates a configuration example of the memory cell MC. The memory cell MC includes a storage element VR, a selection element SE, and terminals TU and TL.

The storage element VR is a resistive random access storage element with a resistance state RS that changes reversibly in accordance with a polarity of a voltage difference between voltages applied to both ends. In other words, the resistance state RS of the storage element VR changes reversibly in accordance with a direction of a current flowing between both ends. For the storage element VR, for example, it is possible to use a stack of an ion source layer and a resistance change layer. The storage element VR has one end coupled to the terminal TU of the memory cell MC, and another end coupled to one end of the selection element SE.

FIG. 5 schematically illustrates a distribution of a resistance value of the storage element VR. The storage element VR possibly takes two identifiable resistance states RS (a high resistance state HRS and a low resistance state LRS). In this example, the high resistance state HRS corresponds to data “0”, and the low resistance state LRS corresponds to data “1”, for example. In other words, the storage element VR functions as a storage element that stores one-bit data. In the following, causing a change from the high resistance state HRS to the low resistance state LRS is referred to as “set”, and causing a change from the low resistance state LRS to the high resistance state HRS is referred to as “reset”.

The selection element SE ( FIG. 4 ) has bidirectional diode characteristics. Specifically, the selection element SE becomes conductive (on-state) in a case where an absolute value of the voltage difference between the voltages applied to both ends is larger than a predetermined voltage difference, and becomes nonconductive (off-state) in a case where the absolute value of the voltage difference is smaller than the predetermined voltage difference. The selection element SE has the one end coupled to the other end of the storage element VR, and another end coupled to the TL terminal of the memory cell MC.

The terminal TU is a terminal coupled to a selection line above a storage layer in which the memory cell MC is formed, and the terminal TL is a terminal coupled to a selection line below the storage layer in which the memory cell MC is formed. Specifically, as illustrated in FIG. 3 , in each of the memory cells MC (the memory cells MC 0 to MC 15 ) formed in the storage layer L 0 , the terminal TU is coupled to one of the column selection lines CL 0 to CL 3 , and the terminal TL is coupled to one of the row selection lines RL 0 to RL 3 . Likewise, in each of the memory cells MC (the memory cells MC 16 to MC 31 ) formed in the storage layer L 1 , the terminal TU is coupled to one of the row selection lines RL 4 to RL 7 , and the terminal TL is coupled to one of the column selection lines CL 0 to CL 3 . As described above, the terminal TU is coupled to the one end of the storage element VR, and the terminal TL is coupled to the other end of the selection element SE. In other words, in the memory cell MC, as illustrated in FIG. 3 , irrespective of which one of the storage layers L 0 and L 1 the memory cell MC is formed in, the storage element VR is formed above the selection element SE.

Thus, in the storage device 1 , respective storage layers have the same stacking order, thus allowing for cost reduction and quality improvement. In other words, for example, in a case of forming, in the storage layer L 0 , the storage element VR above the selection element SE and forming, in the storage layer L 1 , the selection element SE above the storage element VR, there is a possibility that a manufacturing process is complicated and a characteristic difference occurs between characteristics of the memory cell MC formed in the storage layer L 0 and characteristics of the memory cell MC formed in the storage layer L 1 . In contrast, in the storage device 1 , the respective storage layers have the same stacking order, which makes it possible to simplify the manufacturing process, thus allowing for cost reduction. In addition, it is possible to suppress the characteristic difference between the characteristics of the memory cell MC formed in the storage layer L 0 and the characteristics of the memory cell MC formed in the storage layer L 1 , thus allowing for quality improvement.

The array driver AD ( FIG. 2 ) writes data to the memory cell MC or reads data from the memory cell MC through selectively applying a voltage to the row selection lines RL 0 to RL 7 and the column selection lines CL 0 to CL 3 on the basis of an instruction from the microcontroller MCON.

The array driver AD writes data to the memory cell MC through performing a set operation OP 1 or a reset operation OP 2 . The array driver AD reads data stored in the memory cell MC through performing a sense operation OP 3 .

Specifically, in a case of performing the set operation OP 1 on a certain memory cell MC of the memory cells MC 0 to MC 15 formed in the storage layer L 0 , the array driver AD selects the certain memory cell MC through applying a selection voltage Vpset (for example, 6 V) to the column selection line CL related to the certain memory cell MC and applying a selection voltage Vnset (for example, 0 V) to the row selection line RL related to certain the memory cell MC. In addition, in a case of performing the set operation OP 1 on a certain memory cell MC of the memory cells MC 16 to MC 31 formed in the storage layer L 1 , the array driver AD selects the certain memory cell MC through applying the selection voltage Vpset (for example, 6 V) to the row selection line RL related to the certain memory cell MC and applying the selection voltage Vnset (for example, 0 V) to the column selection line CL related to the certain memory cell MC. In the selected memory cell MC, as illustrated in FIG. 4 , a voltage at the terminal TU becomes higher than a voltage at the terminal TL. This turns on the selection element SE to cause a set current Iset to flow from the terminal TU to the terminal TL, thus setting the storage element VR.

In addition, in a case of performing the reset operation OP 2 on a certain memory cell MC of the memory cells MC 0 to MC 15 formed in the storage layer L 0 , the array driver AD selects the certain memory cell MC through applying a selection voltage Vnrst (for example, 0 V) to the column selection line CL related to the certain memory cell MC and applying a selection voltage Vprst (for example, 6 V) to the row selection line RL related to the certain memory cell MC. In addition, in a case of performing the reset operation OP 2 on a certain memory cell MC of the memory cells MC 16 to MC 31 formed in the storage layer L 1 , the array driver AD selects the certain memory cell MC through applying the selection voltage Vnrst (for example, 0 V) to the row selection line RL related to the certain memory cell MC and applying the selection voltage Vprst (for example, 6 V) to the column selection line CL related to the certain memory cell MC. In the selected memory cell MC, as illustrated in FIG. 4 , the voltage at the terminal TL becomes higher than the voltage at the terminal TU. This turns on the selection element SE to cause a reset current Irst to flow from the terminal TL to the terminal TU, thus resetting the storage element VR.

In addition, in a case of performing the sense operation OP 3 on a certain memory cell MC of the memory cells MC 0 to MC 15 formed in the storage layer L 0 , the array driver AD selects the certain memory cell MC through applying a selection voltage Vpsns (for example, 5 V) to the column selection line CL related to the certain memory cell MC and applying a selection voltage Vnsns (for example, 1 V) to the row selection line RL related to the certain memory cell MC. In addition, in a case of performing the sense operation OP 3 on a certain memory cell MC of the memory cells MC 16 to MC 31 formed in the storage layer L 1 , the array driver AD selects the certain memory cell MC through applying the selection voltage Vpsns (for example, 5 V) to the row selection line RL related to the certain memory cell MC and applying the selection voltage Vnsns (for example, 1 V) to the column selection line CL related to the certain memory cell MC. In the selected memory cell MC, as illustrated in FIG. 4 , the voltage at the terminal TU becomes higher than the voltage at the terminal TL to cause a sense current Isns to flow from the terminal TU to the terminal TL. Then, sense amplifiers 24 A and 24 B (described later) detect a voltage generated in the memory cell MC, thereby determining the resistance state RS of the storage element VR. In the sense operation OP 3 , for example, as compared to the set operation OP 1 , the voltage difference between the voltage at the terminal TU and the voltage at the terminal TL is small. This does not sufficiently turn on the selection element SE, and therefore does not set the storage element VR. As a result, in the sense operation OP 3 , the resistance state RS of the storage element VR is maintained.

In addition, in a case of not performing any of the set operation OP 1 , the reset operation OP 2 , and the sense operation OP 3 on a certain memory cell MC of the memory cells MC 0 to MC 31 , the array driver AD applies a non-selection voltage Vinh (for example, 3 V) to the row selection line RL related to the certain memory cell MC, and applies the non-selection voltage Vinh (for example, 3 V) to the column selection line CL related to the certain memory cell MC. This causes the voltages at the terminals TU and TL to be equal to each other in the memory cell MC; the selection element SE is turned off; and a current hardly flows. As a result, in this memory cell MC, the resistance state RS of the storage element VR is maintained.

The array driver AD includes a row selection line driver 20 and a column selection line driver 30 . The row selection line driver 20 selectively applies a voltage to the row selection lines RL 0 to RL 7 on the basis of an instruction from the microcontroller MCON. The column selection line driver 30 selectively applies a voltage to the column selection lines CL 0 to CL 3 on the basis of an instruction from the microcontroller MCON. In the following, the row selection line driver 20 and the column selection line driver 30 are described in detail.

(Row Selection Line Driver 20 )

FIG. 6 illustrates a configuration example of the row selection line driver 20 . The row selection line driver 20 includes voltage selection circuits 21 A and 21 B, current limiting (compliance) circuits 22 A and 22 B, decoders 23 A and 23 B, and the sense amplifiers 24 A and 24 B. In addition, although not illustrated, the row selection line driver 20 also includes an inverting circuit that respectively generates, on the basis of logic signals Vgrset, Vgrrst, Vgrsns, and Vgr 0 to Vgr 7 supplied from the microcontroller MCON, logic signals Vgrsetb, Vgrrstb, Vgrsns, and Vgr 0 b to Vgr 7 b each of which is an inverted signal of a corresponding one of these logic signals. The voltage selection circuit 21 A, the current limiting circuit 22 A, the decoder 23 A, and the sense amplifier 24 A are included in a driver 20 A, and the voltage selection circuit 21 B, the current limiting circuit 22 B, the decoder 23 B, and the sense amplifier 24 B are included in a driver 20 B.

The voltage selection circuit 21 A outputs one of the selection voltages Vnset, Vprst, and Vnsns on the basis of the logic signals Vgrset, Vgrrst, and Vgrsns supplied from the microcontroller MCON. The voltage selection circuit 21 A includes transistors 201 to 203 . The transistors 201 and 203 are n-type MOS (Metal Oxide Semiconductor) transistors, and the transistor 202 is a p-type MOS transistor. The transistor 201 has a gate supplied with the logic signal Vgrset, a source supplied with the selection voltage Vnset (for example, 0 V), and a drain coupled to a node N 21 A. The transistor 202 has a gate supplied with the logic signal Vgrrstb that is the inverted signal of the logic signal Vgrrst, a source supplied with the selection voltage Vprst (for example, 6 V), and a drain coupled to a node N 21 . The transistor 203 has a gate supplied with the logic signal Vgrsns, a source supplied with the selection voltage Vnsns (for example, 1 V), and a drain coupled to the node N 21 .

In the set operation OP 1 , the voltage selection circuit 21 A outputs the selection voltage Vnset (for example, 0 V) on the basis of the high-level logic signal Vgrset supplied from the microcontroller MCON. In addition, in the reset operation OP 2 , the voltage selection circuit 21 A outputs the selection voltage Vprst (for example, 6 V) on the basis of the low-level logic signal Vgrrstb corresponding to the high-level logic signal Vgrrst supplied from the microcontroller MCON. In addition, in the sense operation OP 3 , the voltage selection circuit 21 A outputs the selection voltage Vnsns (for example, 1 V) on the basis of the high-level logic signal Vgrsns supplied from the microcontroller MCON.

The current limiting circuit 22 A limits a current value of a current flowing between the voltage selection circuit 21 A and the decoder 23 A, on the basis of signals Vpcmp and Vncmp supplied from the microcontroller MCON. The current limiting circuit 22 A includes transistors 204 and 205 . The transistor 204 is a p-type MOS transistor, and the transistor 205 is an n-type MOS transistor. The transistor 204 has a gate supplied with the signal Vpcmp, a source coupled to the node N 21 A, and a drain coupled to the node N 23 A. The transistor 205 has a gate supplied with the signal Vncmp, a source coupled to the node N 21 A, and a drain coupled to the node N 23 A.

In the set operation OP 1 , in a case where the voltage selection circuit 21 A outputs the selection voltage Vnset (for example, 0 V), the current limiting circuit 22 A limits, on the basis of the signal Vncmp that is an analog voltage supplied from the microcontroller MCON, the current value of a current flowing from the decoder 23 A to the voltage selection circuit 21 A to a predetermined current value (for example, 10 uA) or smaller. In addition, in the reset operation OP 2 , in a case where the voltage selection circuit 21 A outputs the selection voltage Vprst (for example, 6 V), the current limiting circuit 22 A operates not to limit the current, on the basis of the low-level signal Vpcmp supplied from the microcontroller MCON. In addition, in the sense operation OP 3 , in a case where the voltage selection circuit 21 A outputs the selection voltage Vnsns (for example, 1 V), the current limiting circuit 22 A limits, on the basis of the signal Vncmp that is an analog voltage supplied from the microcontroller MCON, the current value of a current flowing from the decoder 23 A to the voltage selection circuit 21 A to a predetermined current value (for example, 1 uA) or smaller.

The decoder 23 A selectively applies, to the row selection lines RL 0 to RL 3 , the selection voltage supplied from the voltage selection circuit 21 A via the current limiting circuit 22 A on the basis of logic signals Vgr 0 to Vgr 3 supplied from the microcontroller MCON. The decoder 23 A includes transistors 206 to 213 . The transistors 206 to 213 are n-type MOS transistors. The transistor 206 has a gate supplied with the logic signal Vgr 0 , a source coupled to the node N 23 A, and a drain coupled to a drain of the transistor 207 and the row selection line RL 0 . The transistor 207 has a gate supplied with the logic signal Vgr 0 b that is the inverted signal of the logic signal Vgr 0 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to the drain of the transistor 206 and the row selection line RL 0 . The transistor 208 has a gate supplied with a logic signal Vgr 1 b that is an inverted signal of the logic signal Vgr 1 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to a drain of the transistor 209 and the row selection line RL 1 . The transistor 209 has a gate supplied with the logic signal Vgr 1 , a source coupled to the node N 23 A, and a drain coupled to the drain of the transistor 208 and the row selection line RL 1 . The transistor 210 has a gate supplied with the logic signal Vgr 2 , a source coupled to the node N 23 A, and a drain coupled to a drain of the transistor 211 and the row selection line RL 2 . The transistor 211 has a gate supplied with a logic signal Vgr 2 b that is an inverted signal of the logic signal Vgr 2 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to the drain of the transistor 210 and the row selection line RL 2 . The transistor 212 has a gate supplied with a logic signal Vgr 3 b that is an inverted signal of the logic signal Vgr 3 , a source supplied with the non-selection voltage Vinh (for example, 3V), and a drain coupled to a drain of the transistor 213 and the row selection line RL 3 . The transistor 213 has a gate supplied with the logic signal Vgr 3 , a source coupled to the node N 23 A, and a drain coupled to the drain of the transistor 212 and the row selection line RL 3 .

The sense amplifier 24 A determines the resistance state RS of the memory cell MC on the basis of a signal Vsaen supplied from the microcontroller MCON. The sense amplifier 24 A is included in a differential amplifier. The sense amplifier 24 A includes transistors 214 to 218 . The transistors 214 to 216 are n-type MOS transistors, and the transistors 217 and 218 are p-type MOS transistors. The transistor 214 has a gate supplied with the signal Vsaen, a drain coupled to a source of each of the transistors 215 and 216 , and a source supplied with a voltage Vss. This transistor 214 functions as a current source for the differential amplifier. The transistor 215 has a gate supplied with a voltage Vref, a drain coupled to a drain of the transistor 217 , and a source coupled to a source of the transistor 216 and the drain of the transistor 214 . The transistor 216 has a gate coupled to the node N 23 A, a drain coupled to a drain of the transistor 218 and a gate of each of the transistors 217 and 218 , and the source coupled to the source of the transistor 215 and the drain of the transistor 214 . The transistors 215 and 216 function as differential pair transistors for the differential amplifier. The transistor 217 has a gate coupled to a gate of the transistor 218 , and the drain of the transistor 216 , and a drain of the transistor 218 , a source supplied with a voltage Vpp, and the drain coupled to the drain of the transistor 215 . The transistor 218 has the gate coupled to the gate of the transistor 217 and the drain of each of the transistors 216 and 218 , a source supplied with the voltage Vpp, and the drain coupled to the gate of each of the transistors 217 and 218 and the drain of the transistor 216 . The transistors 217 and 218 function as an active load for the differential amplifier.

In the sense operation OP 3 , the sense amplifier 24 A generates a signal SAout 0 through causing the transistor 214 to function as a current source on the basis of the signal Vsaen that is an analog voltage supplied from the microcontroller MCON, and comparing the voltage at the node N 23 A and the voltage Vref. Then, the sense amplifier 24 A supplies this signal SAout 0 to the microcontroller MCON. In addition, in a case of not performing the sense operation OP 3 , the sense amplifier 24 A is turned off the transistor 214 on the basis of the low-level signal Vsaen supplied from the microcontroller MCON. This makes it possible for the sense amplifier 24 A to reduce power consumption.

As with the voltage selection circuit 21 A, the voltage selection circuit 21 B outputs one of the selection voltages Vpset, Vnrst, and Vpsns on the basis of the logic signals Vgrset, Vgrrst, and Vgrsns supplied from the microcontroller MCON. The voltage selection circuit 21 B includes transistors 221 to 223 . The transistors 221 and 223 are p-type MOS transistors, and the transistor 222 is an n-type MOS transistor. The transistor 221 has a gate supplied with the logic signal Vgrsetb that is the inverted signal of the logic signal Vgrset, a source supplied with the selection voltage Vpset (for example, 6 V), and a drain coupled to the node N 21 B. The transistor 222 has a gate supplied with the logic signal Vgrrst, a source supplied with the selection voltage Vnrst (for example, 0 V), and a drain coupled to the node N 21 B. The transistor 223 has a gate supplied with a logic signal Vgrsnsb that is an inverted signal of the logic signal Vgrsns, a source supplied with the selection voltage Vpsns (for example, 5 V), and a drain coupled to the node N 21 B.

In the set operation OP 1 , the voltage selection circuit 21 B outputs the selection voltage Vpset (for example, 6 V) on the basis of the low-level logic signal Vgrsetb corresponding to the high-level logic signal Vgrset supplied from the microcontroller MCON. In addition, in the reset operation OP 2 , the voltage selection circuit 21 B outputs the selection voltage Vnrst (for example, 0 V) on the basis of the high-level logic signal Vgrrst supplied from the microcontroller MCON. In addition, in the sense operation OP 3 , the voltage selection circuit 21 B outputs the selection voltage Vpsns (for example, 5 V) on the basis of the low-level logic signal Vgrsnsb corresponding to the high-level logic signal Vgrsns supplied from the microcontroller MCON.

As with the current limiting circuit 22 A, the current limiting circuit 22 B limits, on the basis of the signals Vpcmp and Vncmp supplied from the microcontroller MCON, the current value of a current flowing between the voltage selection circuit 21 B and the decoder 23 B. The current limiting circuit 22 B has a configuration similar to that of the current limiting circuit 22 A. The current limiting circuit 22 B includes transistors 224 and 225 . The transistors 224 and 225 respectively correspond to the transistors 204 and 205 in the current limiting circuit 22 A.

In the set operation OP 1 , in a case where the voltage selection circuit 21 B outputs the selection voltage Vpset (for example, 6 V), the current limiting circuit 22 B limits, on the basis of the signal Vpcmp that is an analog voltage supplied from the microcontroller MCON, the current value of a current flowing from the voltage selection circuit 21 B to the decoder 23 B to a predetermined current value (for example, 10 uA) or smaller. In addition, in the reset operation OP 2 , in a case where the voltage selection circuit 21 B outputs the selection voltage Vnrst (for example, 0 V), the current limiting circuit 22 B operates not to limit the current, on the basis of the high-level signal Vncmp supplied from the microcontroller MCON. In addition, in the sense operation OP 3 , in a case where the voltage selection circuit 21 B outputs the selection voltage Vpsns (for example, 5 V), the current limiting circuit 22 B limits, on the basis of the signal Vpcmp that is an analog voltage supplied from the microcontroller MCON, the current value of a current flowing from the voltage selection circuit 21 B to the decoder 23 B to a predetermined current value (for example, 1 uA) or smaller.

As with the decoder 23 A, the decoder 23 B selectively applies, to the row selection lines RL 4 to RL 7 , the selection voltage supplied from the voltage selection circuit 21 B via the current limiting circuit 22 B on the basis of logic signals Vgr 4 to Vgr 7 supplied from the microcontroller MCON. The decoder 23 B includes transistors 226 to 233 . The transistors 226 to 233 are n-type MOS transistors. The transistor 226 has a gate supplied with the logic signal Vgr 4 , a source coupled to a node N 23 B, and a drain coupled to a drain of the transistor 227 and the row selection line RL 4 . The transistor 227 has a gate supplied with a logic signal Vgr 4 b that is an inverted signal of the logic signal Vgr 4 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 226 and the row selection line RL 4 . The transistor 228 has a gate supplied with a logic signal Vgr 5 b that is an inverted signal of the logic signal Vgr 5 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to a drain of the transistor 229 and the row selection line RL 5 . The transistor 229 has a gate supplied with the logic signal Vgr 5 , a source coupled to the node N 23 B, and the drain coupled to the drain of the transistor 228 and the row selection line RL 5 . The transistor 230 has a gate supplied with the logic signal Vgr 6 , a source coupled to the node N 23 B, and a drain coupled to a drain of the transistor 231 and the row selection line RL 6 . The transistor 231 has a gate supplied with a logic signal Vgr 6 b that is an inverted signal of the logic signal Vgr 6 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 230 and the row selection line RL 6 . The transistor 232 has a gate supplied with a logic signal Vgr 7 b that is an inverted signal of the logic signal Vgr 7 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to a drain of the transistor 233 and the row selection line RL 7 . The transistor 233 has a gate supplied with the logic signal Vgr 7 , a source coupled to the node N 23 B, and the drain coupled to the drain of the transistor 232 and the row selection line RL 7 .

As with the sense amplifier 24 A, the sense amplifier 24 B determines the resistance state RS of the memory cell MC on the basis of the signal Vsaen supplied from the microcontroller MCON. The sense amplifier 24 B has a configuration similar to that of the sense amplifier 24 A. The sense amplifier 24 B includes transistors 234 to 238 . The transistors 234 to 238 respectively correspond to the transistors 214 to 218 in the sense amplifier 24 A.

In the sense operation OP 3 , the sense amplifier 24 B generates a signal SAout 1 through causing the transistor 234 to function as a current source on the basis of the signal Vsaen that is an analog voltage supplied from the microcontroller MCON, and comparing the voltage at the node N 23 B and the voltage Vref. Then, the sense amplifier 24 B supplies this signal SAout 1 to the microcontroller MCON. In addition, in a case of not performing the sense operation OP 3 , the sense amplifier 24 B is turned off the transistor 234 on the basis of the low-level signal Vsaen supplied from the microcontroller MCON. This makes it possible for the sense amplifier 24 B to reduce power consumption.

(Column Selection Line Driver 30 )

FIG. 7 illustrates a configuration example of the column selection line driver 30 . The column selection line driver 30 includes voltage selection circuits 31 A and 31 B and decoders 32 A and 32 B. In addition, although not illustrated, the column selection line driver 30 also includes an inverting circuit that respectively generates, on the basis of the logic signals Vgcset 0 , Vgcset 1 , Vgcrst 0 , Vgcrst 1 , Vgcsns 0 , Vgcsns 1 , and Vgc 0 to Vgc 3 supplied from the microcontroller MCON, logic signals Vgcset 0 b , Vgcset 1 b , Vgcrst 0 b , Vgcrst 1 b , Vgcsns 0 b , Vgcsns 1 b , and Vgc 0 b to Vgc 3 b each of which is an inverted signal of a corresponding one of these logic signals. The voltage selection circuit 31 A and the decoder 32 A are included in a driver 30 A, and the voltage selection circuit 31 B and the decoder 32 B are included in a driver 30 B.

The voltage selection circuit 31 A outputs one of the selection voltages Vpset, Vnset, Vprst, Vnrst, Vpsns, and Vnsns on the basis of the logic signals Vgcset 0 , Vgcset 1 , Vgcrst 0 , Vgcrst 1 , Vgcsns 0 , and Vgcsns 1 supplied from the microcontroller MCON. The voltage selection circuit 31 A includes transistors 301 to 306 . The transistors 301 , 303 , and 305 are p-type MOS transistors, and the transistors 302 , 304 , and 306 are n-type MOS transistors. The transistor 301 has a gate supplied with the logic signal Vgcset 0 b that is the inverted signal of the logic signal Vgcset 0 , a source supplied with the selection voltage Vpset (for example, 6 V), and a drain coupled to a node N 32 A. The transistor 302 has a gate supplied with the logic signal Vgcset 1 , a source supplied with the selection voltage Vnset (for example, 0 V), and a drain coupled to the node N 32 A. The transistor 303 has a gate supplied with the logic signal Vgcrst 1 b that is the inverted signal of the logic signal Vgcrst 1 , a source supplied with the selection voltage Vprst (for example, 6 V), and a drain coupled to the node N 32 A. The transistor 304 has a gate supplied with the logic signal Vgcrst 0 , a source supplied with the selection voltage Vnrst (for example, 0 V), and a drain coupled to the node N 32 A. The transistor 305 has a gate supplied with the logic signal Vgcsns 0 b that is the inverted signal of the logic signal Vgcsns 0 , a source supplied with the selection voltage Vpsns (for example, 5 V), and a drain coupled to the node N 32 A. The transistor 306 has a gate supplied with the logic signal Vgcsns 1 , a source supplied with the selection voltage Vnsns (for example, 1 V), and a drain coupled to the node N 32 A.

In the set operation OP 1 , the voltage selection circuit 31 A outputs the selection voltage Vpset (for example, 6 V) on the basis of the low-level logic signal Vgcset 0 b corresponding to the high-level logic signal Vgcset 0 supplied from the microcontroller MCON, or outputs the selection voltage Vnset (for example, 0 V) on the basis of the high-level logic signal Vgcset 1 supplied from the microcontroller MCON. In addition, in the reset operation OP 2 , the voltage selection circuit 31 A outputs the selection voltage Vprst (for example, 6 V) on the basis of the low-level logic signal Vgcrst 1 b corresponding to the high-level logic signal Vgcrst 1 supplied from the microcontroller MCON, or outputs the selection voltage Vnrst (for example, 0 V) on the basis of the high-level logic signal Vgcrst 0 supplied from the microcontroller MCON. In addition, in the sense operation OP 3 , the voltage selection circuit 31 A outputs the selection voltage Vpsns (for example, 5 V) on the basis of the low-level logic signal Vgcsns 0 b corresponding to the high-level logic signal Vgcsns 0 supplied from the microcontroller MCON, or outputs the selection voltage Vnsns (for example, 1V) on the basis of the high-level logic signal Vgcsns 1 supplied from the microcontroller MCON.

The decoder 32 A selectively applies, to the column selection lines CL 0 and CL 1 , the selection voltage supplied from the voltage selection circuit 31 A on the basis of the logic signals Vgc 0 and Vgc 1 supplied from the microcontroller MCON. The decoder 32 A includes transistors 307 to 310 . The transistors 307 to 310 are n-type MOS transistors. The transistor 307 has a gate supplied with the logic signal Vgc 0 , a source coupled to the node N 32 A, and a drain coupled to a drain of the transistor 308 and the column selection line CL 0 . The transistor 308 has a gate supplied with the logic signal Vgc 0 b that is the inverted signal of the logic signal Vgc 0 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 307 and the column selection line CL 0 . The transistor 309 has a gate supplied with a logic signal Vgc 1 b that is an inverted signal of the logic signal Vgc 1 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to a drain of the transistor 310 and the column selection line CL 1 . The transistor 310 has a gate supplied with the logic signal Vgc 1 , a source coupled to the node N 32 A, and the drain coupled to the drain of the transistor 309 and the column selection line CL 1 .

As with the voltage selection circuit 31 A, the voltage selection circuit 31 B outputs one of the selection voltages Vpset, Vnset, Vprst, Vnrst, Vpsns, and Vnsns on the basis of the logic signals Vgcset 0 , Vgcset 1 , Vgcrst 0 , Vgcrst 1 , Vgcsns 0 , and Vgcsns 1 supplied from the microcontroller MCON. The voltage selection circuit 31 B includes transistors 321 to 326 . The transistors 321 , 323 , and 325 are p-type MOS transistors, and the transistors 322 , 324 , and 326 are n-type MOS transistors. The transistor 321 has a gate supplied with the logic signal Vgcset 1 b that is the inverted signal of the logic signal Vgcset 1 , a source supplied with the selection voltage Vpset (for example, 6 V), and a drain coupled to the node N 32 B. The transistor 322 has a gate supplied with the logic signal Vgcset 0 , a source supplied with the selection voltage Vnset (for example, 0 V), and a drain coupled to the node N 32 B. The transistor 323 has a gate supplied with the logic signal Vgcrst 0 b that is the inverted signal of the logic signal Vgcrst 0 , a source supplied with the selection voltage Vprst (for example, 6 V), and a drain coupled to the node N 32 B. The transistor 324 has a gate supplied with the logic signal Vgcrst 1 , a source supplied with the selection voltage Vnrst (for example, 0 V), and a drain coupled to the node N 32 B. The transistor 325 has a gate supplied with the logic signal Vgcsns 1 b that is the inverted signal of the logic signal Vgcsns 1 , a source supplied with the selection voltage Vpsns (for example, 5 V), and a drain coupled to the node N 32 B. The transistor 326 has a gate supplied with the logic signal Vgcsns 0 , a source supplied with the selection voltage Vnsns (for example, 1 V), and a drain coupled to the node N 32 B.

In the set operation OP 1 , the voltage selection circuit 31 B outputs the selection voltage Vpset (for example, 6 V) on the basis of the low-level logic signal Vgcset 1 b corresponding to the high-level logic signal Vgcset 1 supplied from the microcontroller MCON, or outputs the selection voltage Vnset (for example, 0 V) on the basis of the high-level logic signal Vgcset 0 supplied from the microcontroller MCON. In addition, in the reset operation OP 2 , the voltage selection circuit 31 B outputs the selection voltage Vprst (for example, 6 V) on the basis of the low-level logic signal Vgcrst 0 b corresponding to the high-level logic signal Vgcrst 0 supplied from the microcontroller MCON, or outputs the selection voltage Vnrst (for example, 0 V) on the basis of the high-level logic signal Vgcrst 1 supplied from the microcontroller MCON. In addition, in the sense operation OP 3 , the voltage selection circuit 31 B outputs the selection voltage Vpsns (for example, 5 V) on the basis of the low-level logic signal Vgcsns 1 b corresponding to the high-level logic signal Vgcsns 1 supplied from the microcontroller MCON, or outputs the selection voltage Vnsns (for example, 1 V) on the basis of the high-level logic signal Vgcsns 0 supplied from the microcontroller MCON.

As with the decoder 32 A, the decoder 32 B selectively applies, to column selection lines CL 2 and CL 3 , the selection voltage supplied from the voltage selection circuit 31 B, on the basis of logic signals Vgc 2 and Vgc 3 supplied from the microcontroller MCON. The decoder 32 B includes transistors 327 to 330 . The transistors 327 to 330 are n-type MOS transistors. The transistor 327 has a gate supplied with the logic signal Vgc 2 , a source coupled to the node N 32 B, and a drain coupled to a drain of the transistor 328 and the column selection line CL 2 . The transistor 328 has a gate supplied with a logic signal Vgc 2 b that is an inverted signal of the logic signal Vgc 2 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 327 and the column selection line CL 2 . The transistor 329 has a gate supplied with a logic signal Vgc 3 b that is an inverted signal of the logic signal Vgc 3 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to a drain of the transistor 330 and the column selection line CL 3 . The transistor 330 has a gate supplied with the logic signal Vgc 3 , a source coupled to the node N 32 B, and the drain coupled to the drain of the transistor 329 and the column selection line CL 3 .

With this configuration, as described later, for example, in the set operation OP 1 , the row selection line driver 20 in the array driver AD applies the selection voltage Vnset (for example, 0 V) to one of the row selection lines RL 0 to RL 3 , and applies the selection voltage Vpset (for example, 6 V) to one of the row selection lines RL 4 to RL 7 . Then, in the set operation OP 1 , the column selection line driver 30 in the array driver AD applies one of the selection voltage Vpset (for example, 6 V) and the selection voltage Vnset (for example, 0 V) to the column selection line CL 0 or the column selection line CL 1 , and applies the other of the selection voltage Vpset and the selection voltage nset to the column selection line CL 2 or the column selection line CL 3 . Thus, in the memory array MA, the storage elements VR in two memory cells MC of the 32 memory cells MC are selected. At the time, two current paths different from each other are formed in the memory array unit MAU. The same applies to the reset operation OP 2 and the sense operation OP 3 . This makes it possible to increase reliability in the data write operation and the data read operation in the storage device 1 .

Here, the memory array MA corresponds to a specific example of a “first storage section” in the present disclosure. The row selection lines RL 0 to RL 3 correspond to a specific example of a “plurality of first selection lines” in the present disclosure, and the row selection lines RL 4 to RL 7 correspond to a specific example of a “plurality of second selection lines” in the present disclosure. The column selection lines CL 0 and CL 1 correspond to a specific example of a “plurality of third selection lines” in the present disclosure, and the column selection lines CL 2 and CL 3 correspond to a specific example of a “plurality of fourth selection lines” in the present disclosure. The row selection line driver 20 corresponds to a specific example of a “first selection line driver” in the present disclosure. The driver 20 A corresponds to a specific example of a “first driver” in the present disclosure, and the driver 20 B corresponds to a specific example of a “second driver” in the present disclosure. The column selection line driver 30 corresponds to a specific example of a “second selection line driver” in the present disclosure. The driver 30 A corresponds to a specific example of a “third driver” in the present disclosure, and the driver 30 B corresponds to a specific example of a “fourth driver” in the present disclosure. For example, the selection voltage Vpset corresponds to a specific example of a “first selection voltage” in the present disclosure, and the selection voltage Vnset corresponds to a specific example of a “second selection voltage” in the present disclosure.

The decoder 23 A corresponds to a specific example of a “first voltage application section” in the present disclosure. The transistors 206 , 209 , 210 , and 213 correspond to a specific example of a “plurality of first switches” in the present disclosure. The logic signals Vgr 0 , Vgr 0 b , Vgr 1 , Vgr 1 b , Vgr 2 , Vgr 2 b , Vgr 3 , and Vgr 3 b each correspond to a specific example of a “first selection signal” in the present disclosure. The voltage selection circuit 21 A corresponds to a specific example of a “first supply section” in the present disclosure. The decoder 23 B corresponds to a specific example of a “second voltage application section” in the present disclosure. The transistors 226 , 229 , 230 , and 233 correspond to a specific example of a “plurality of second switches” in the present disclosure. The logic signals Vgr 4 , Vgr 4 b , Vgr 5 , Vgr 5 b , Vgr 6 , Vgr 6 b , Vgr 7 , and Vgr 1 b each correspond to a specific example of a “second selection signal” in the present disclosure. The voltage selection circuit 21 B corresponds to a specific example of a “second supply section” in the present disclosure. The decoder 32 A corresponds to a specific example of a “third voltage application section” in the present disclosure. The transistors 307 and 310 correspond to a specific example of a “plurality of third switches” in the present disclosure. The logic signals Vgc 0 , Vgc 0 b , Vgc 1 , and Vgc 1 b each correspond to a specific example of a “third selection signal” in the present disclosure. The voltage selection circuit 31 A corresponds to a specific example of a “third supply section” in the present disclosure. The decoder 32 B corresponds to a specific example of a “fourth voltage application section” in the present disclosure. The transistors 327 and 330 correspond to a specific example of a “plurality of fourth switches” in the present disclosure. The logic signals Vgc 2 , Vgc 2 b , Vgc 3 , and Vgc 3 b each correspond to a specific example of a “fourth selection signal” in the present disclosure. The voltage selection circuit 31 B corresponds to a specific example of a “fourth supply section” in the present disclosure.

[Workings and Effects]

Next, workings and effects of the storage device 1 according to the present embodiment are described.

(Overview of Overall Operation)

First, an overview of an overall operation of the storage device 1 is described with reference to FIGS. 1 and 2 . The interface circuit IF ( FIG. 1 ) communicates with the controller 99 , and performs arbitration for the microcontroller MCON in each of the banks BK. In each of the banks BK, the microcontroller MCON controls the operation of the plurality of memory array units MAU on the basis of the control signal from the interface circuit IF. In each of the memory array units MAU, the row selection line driver 20 in the array driver AD selectively applies a voltage to the row selection lines RL 0 to RL 7 on the basis of an instruction from the microcontroller MCON. The column selection line driver 30 in the array driver AD selectively applies a voltage to the column selection lines CL 0 to CL 3 on the basis of an instruction from the microcontroller MCON. The array driver AD writes data to the memory cell MC through performing the set operation OP 1 or the reset operation OP 2 . In addition, the array driver AD reads data stored in the memory cell MC through performing the sense operation OP 3 .

(Detailed Operation)

In the following, the set operation OP 1 , the reset operation OP 2 , and the sense operation OP 3 in a case where two memory cells MC (in this example, memory cells MC 6 and MC 25 ) are selected from 31 memory cells MC in the memory array unit MAU are described in detail.

(Set Operation OP 1 )

FIG. 8 schematically illustrates an operation in a case of performing the set operation OP 1 on the two memory cells MC 6 and MC 25 . In FIG. 8 , the selection line to which the selection voltage Vpset (in this example, 6 V) is applied is indicated by a wide solid line, the selection line to which the selection voltage Vnset (in this example, 0 V) is applied is indicated by a wide dashed line, and the selection line to which the non-selection voltage Vinh (in this example, 3 V) is applied is indicated by a narrow solid line. The voltages VCL 0 to VCL 3 indicate voltages at the column selection lines CL 0 to CL 3 , respectively, and the voltages VRL 0 to VRL 7 indicate voltages at the row selection lines RL 0 to RL 7 , respectively.

FIGS. 9A and 9B schematically illustrate an operation of the array driver AD in the set operation OP 1 . FIG. 9A illustrates an operation of the row selection line driver 20 , and FIG. 9B illustrates an operation of the column selection line driver 30 . In FIG. 9A , each of the transistors in the voltage selection circuits 21 A and 21 B, each of the transistors in the decoders 23 A and 23 B, the transistor 214 in the sense amplifier 24 A, and the transistor 234 in the sense amplifier 24 B are illustrated using switches that indicate operation states of the transistors. Likewise, in FIG. 9B , each of the transistors in the voltage selection circuits 31 A and 31 B and each of the transistors in the decoders 32 A and 32 B are illustrated using switches that indicate operation states of the transistors.

In the example in FIG. 8 , the row selection line driver 20 applies the selection voltage Vnset (in this example, 0 V) to the row selection line RL 1 , applies the selection voltage Vpset (in this example, 6 V) to the row selection line RL 6 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining row selection lines RL 0 , RL 2 to RL 5 , and RL 7 . In addition, the column selection line driver 30 applies the selection voltage Vnset (in this example, 0 V) to the column selection line CL 1 , applies the selection voltage Vpset (in this example, 6 V) to the column selection line CL 2 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining column selection lines CL 0 and CL 3 .

At this time, as illustrated in FIG. 9A , in the voltage selection circuit 21 A in the row selection line driver 20 , the transistor 201 is turned on while the transistors 202 and 203 are turned off. This causes the voltage selection circuit 21 A to output the selection voltage Vnset (in this example, 0 V). Meanwhile, in the voltage selection circuit 21 B, the transistor 221 is turned on while the transistors 222 and 223 are turned off. This causes the voltage selection circuit 21 B to output the selection voltage Vpset (in this example, 6 V). In other words, in the row selection line driver 20 , the gate of the transistor 201 is supplied with the logic signal Vgrset, and the gate of the transistor 221 is supplied with the logic signal Vgrsetb that is the inverted signal of the logic signal Vgrset. This sets the logic signal Vgrset to a high level, thus turning on the transistors 201 and 221 at the same time. As a result, each of the voltage selection circuits 21 A and 21 B outputs, out of the two selection voltages Vpset and Vnset used in the set operation OP 1 , one voltage different from the other.

Then, in the decoder 23 A, the transistors 207 , 209 , 211 , and 212 are turned on while the transistors 206 , 208 , 210 , and 213 are turned off. As a result, the decoder 23 A applies, to the row selection line RL 1 , the selection voltage Vnset (in this example, 0 V) supplied from the voltage selection circuit 21 A via the current limiting circuit 22 A, and applies the non-selection voltage Vinh (in this example, 3 V) to the row selection lines RL 0 , RL 2 , and RL 3 .

In addition, in the decoder 23 B, the transistors 227 , 228 , 230 , and 232 are turned on while the transistors 226 , 229 , 231 , and 233 are turned off. As a result, the decoder 23 B applies, to the row selection line RL 6 , the selection voltage Vpset (in this example, 6 V) supplied from the voltage selection circuit 21 B via the current limiting circuit 22 B, and applies the non-selection voltage Vinh (in this example, 3 V) to the row selection lines RL 4 , RL 5 , and RL 7 .

It is to be noted that in this set operation OP 1 , both the transistor 214 in the sense amplifier 24 A and the transistor 234 in the sense amplifier 24 B are off.

In addition, as illustrated in FIG. 9B , in the voltage selection circuit 31 A in the column selection line driver 30 , the transistor 302 is turned on while the transistors 301 and 303 to 306 are turned off. This causes the voltage selection circuit 31 A to output the selection voltage Vnset (in this example, 0 V). Meanwhile, in the voltage selection circuit 31 B, the transistor 321 is turned on while the transistors 322 to 326 are turned off. This causes the voltage selection circuit 31 B to output the selection voltage Vpset (in this example, 6 V). In other words, in the column selection line driver 30 , the gate of the transistor 302 is supplied with the logic signal Vgcset 1 , and the gate of the transistor 321 is supplied with the logic signal Vgcset 1 b that is the inverted signal of the logic signal Vgcset 1 . This sets the logic signal Vgcset 1 to the high level, thus turning on the transistors 302 and 321 at the same time. As a result, each of the voltage selection circuits 31 A and 31 B outputs, out of the two selection voltages Vpset and Vnset used in the set operation OP 1 , one voltage different from the other.

Then, in the decoder 32 A, the transistors 308 and 310 are turned on while the transistors 307 and 309 are turned off. As a result, the decoder 32 A applies, to the column selection line CL 1 , the selection voltage Vnset (in this example, 0 V) supplied from the voltage selection circuit 31 A, and applies the non-selection voltage Vinh (in this example, 3 V) to the column selection line CL 0 .

In addition, in the decoder 32 B, the transistors 327 and 329 are turned on while the transistors 328 and 330 are turned off. As a result, the decoder 32 B outputs, to the column selection line CL 2 , the selection voltage Vpset (in this example, 6 V) supplied from the voltage selection circuit 31 B, and applies the non-selection voltage Vinh (in this example, 3 V) to the column selection line CL 3 .

As a result, in the memory array unit MAU, as illustrated in FIG. 8 , the two memory cells MC 6 and MC 25 are selected as targets for the set operation OP 1 .

The memory cell MC 6 is the memory cell MC formed in the storage layer L 0 ; therefore, the selection voltage Vpset (in this example, 6 V) applied to the column selection line CL 2 is supplied to the terminal TU of the memory cell MC 6 , and the selection voltage Vnset (in this example, 0 V) applied to the row selection line RL 1 is supplied to the terminal TL of the memory cell MC 6 . As a result, in the memory cell MC 6 , as illustrated in FIG. 4 , the set current Iset (a set current Iset 1 ) flows from the terminal TU toward the terminal TL, thus setting the storage element VR. As illustrated in FIGS. 8, 9A, and 9B , the set current Iset 1 flows through the voltage selection circuit 31 B, the decoder 32 B, the column selection line CL 2 , the memory cell MC 6 , the row selection line RL 1 , the decoder 23 A, the current limiting circuit 22 A, and the voltage selection circuit 21 A in this order.

Meanwhile, the memory cell MC 25 is the memory cell MC formed in the storage layer L 1 ; therefore, the selection voltage Vpset (in this example, 6 V) applied to the row selection line RL 6 is supplied to the terminal TU of the memory cell MC 25 , and the selection voltage Vnset (in this example, 0 V) applied to the column selection line CL 1 is supplied to the terminal TL of the memory cell MC 25 . As a result, in the memory cell MC 25 , the set current Iset (a set current Iset 2 ) flows from the terminal TU toward the terminal TL, thus setting the storage element VR. As illustrated in FIGS. 8, 9A, and 9B , the set current Iset 2 flows through the voltage selection circuit 21 B, the current limiting circuit 22 B, the decoder 23 B, the row selection line RL 6 , the memory cell MC 25 , the column selection line CL 1 , the decoder 32 A, and the voltage selection circuit 31 A in this order.

Thus, in the memory array unit MAU, it is possible to perform the set operation OP 1 on two memory cells MC (in this example, MC 6 and MC 25 ) at the same time. At the time, as illustrated in FIGS. 8, 9A, and 9B , two current paths different from each other are formed in the memory array unit MAU.

It is to be noted that in this example, an example of performing the set operation OP 1 on the memory cells MC 6 and MC 25 has been described. Alternatively, for example, in a case of performing the set operation OP 1 on the memory cells MC 5 and MC 26 , the column selection line driver 30 applies the selection voltage Vpset (in this example, 6 V) to the column selection line CL 1 , applies the selection voltage Vnset (in this example, 0 V) to the column selection line CL 2 , and applies the non-selection voltage Vinh (in this example, 3V) to the remaining column selection lines CL 0 and CL 3 . Specifically, in the column selection line driver 30 ( FIG. 7 ), in a case where the high-level logic signal Vgcset 0 is supplied from the microcontroller MCON, the transistors 301 and 322 are turned on, thus causing the voltage selection circuit 31 A to output the selection voltage Vpset and causing the voltage selection circuit 31 B to output the selection voltage Vnset. Then, the decoder 32 A applies, to the column selection line CL 1 , the selection voltage Vpset (in this example, 6 V) supplied from the voltage selection circuit 31 A, and the decoder 32 B applies, to the column selection line CL 2 , the selection voltage Vnset (in this example, 0 V) supplied from the voltage selection circuit 31 B. Thus, it is possible for the array driver AD to perform the set operation OP 1 on the memory cells MC 5 and MC 26 .

In the memory array unit MAU, it is possible to access, at the same time, two memory cells MC that satisfy two conditions as described below. A first condition is that one of the two memory cells MC is coupled to one of the row selection lines RL 0 to RL 3 , and the other is coupled to one of the row selection lines RL 4 to RL 7 . In other words, one of the two memory cells MC is formed in the storage layer L 1 , and the other is formed in a storage layer L 2 . In addition, a second condition is that one of the two memory cells MC is coupled to one of the column selection lines CL 0 and CL 1 , and the other is coupled to one of the column selection lines CL 2 and CL 3 . In the storage device 1 , it is possible to access the two memory cells MC at the same time as long as the two memory cells MC satisfy these two conditions.

(Reset Operation OP 2 )

FIG. 10 schematically illustrates an operation in a case of performing the reset operation OP 2 on the two memory cells MC 6 and MC 25 . FIGS. 11A and 11B schematically illustrate an operation of the array driver AD in the reset operation OP 2 . FIG. 11A illustrates an operation of the row selection line driver 20 , and FIG. 11B illustrates an operation of the column selection line driver 30 . In FIG. 10 , the selection line to which the selection voltage Vprst (in this example, 6 V) is applied is indicated by a wide solid line, and the selection line to which the selection voltage Vnrst (in this example, 0 V) is applied is indicated by a wide dashed line.

In the example in FIG. 10 , the row selection line driver 20 applies the selection voltage Vprst (in this example, 6 V) to the row selection line RL 1 , applies the selection voltage Vnrst (in this example, 0 V) to the row selection line RL 6 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining row selection lines RL 0 , RL 2 to RL 5 , and RL 7 . In addition, the column selection line driver 30 applies the selection voltage Vprst (in this example, 6 V) to the column selection line CL 1 , applies the selection voltage Vnrst (in this example, 0 V) to the column selection line CL 2 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining column selection lines CL 0 and CL 3 .

At this time, as illustrated in FIG. 11A , in the voltage selection circuit 21 A in the row selection line driver 20 , the transistor 202 is turned on while the transistors 201 and 203 are turned off. This causes the voltage selection circuit 21 A to output the selection voltage Vprst (in this example, 6 V). Meanwhile, in the voltage selection circuit 21 B, the transistor 222 is turned on while the transistors 221 and 223 are turned off. This causes the voltage selection circuit 21 B to output the selection voltage Vnrst (in this example, 0 V). In other words, in the row selection line driver 20 , the gate of the transistor 202 is supplied with the logic signal Vgrrstb that is the inverted signal of the logic signal Vgrrst, and the gate of the transistor 222 is supplied with the logic signal Vgrrst. This sets the logic signal Vgrrst to the high level, thus turning on the transistors 202 and 222 at the same time. As a result, each of the voltage selection circuits 21 A and 21 B outputs, out of the two selection voltages Vprst and Vnrst used in the reset operation OP 2 , one voltage different from the other.

Then, the decoder 23 A applies, to the row selection line RL 1 , the selection voltage Vprst (in this example, 6 V) supplied from the voltage selection circuit 21 A via the current limiting circuit 22 A, and applies the non-selection voltage Vinh (in this example, 3 V) to the row selection lines RL 0 , RL 2 , and RL 3 . In addition, the decoder 23 B applies, to the row selection line RL 6 , the selection voltage Vnrst (in this example, 0 V) supplied from the voltage selection circuit 21 B via the current limiting circuit 22 B, and applies the non-selection voltage Vinh (in this example, 3 V) to the row selection lines RL 4 , RL 5 , and RL 7 .

In addition, as illustrated in FIG. 11B , in the voltage selection circuit 31 A in the column selection line driver 30 , the transistor 303 is turned on while the transistors 301 , 302 , and 304 to 306 are turned off. This causes the voltage selection circuit 31 A to output the selection voltage Vprst (in this example, 6 V). Meanwhile, in the voltage selection circuit 31 B, the transistor 324 is turned on while the transistors 321 to 323 , 325 , and 326 are turned off. This causes the voltage selection circuit 31 B to output the selection voltage Vnrst (in this example, 0 V). In other words, in the column selection line driver 30 , the gate of the transistor 303 is supplied with the logic signal Vgcrst 1 b that is the inverted signal of the logic signal Vgcrst 1 , and the gate of the transistor 324 is supplied with the logic signal Vgcrst 1 . This sets the logic signal Vgcrst 1 to the high level, thus turning on the transistors 303 and 324 at the same time. As a result, each of the voltage selection circuits 31 A and 31 B outputs, out of the two selection voltages Vprst and Vnrst used in the reset operation OP 2 , one voltage different from the other.

Then the decoder 32 A applies, to the column selection line CL 1 , the selection voltage Vprst (in this example, 6 V) supplied from the voltage selection circuit 31 A, and applies the non-selection voltage Vinh (in this example, 3 V) to the column selection line CL 0 . In addition, the decoder 32 B applies, to the column selection line CL 2 , the selection voltage Vnrst (in this example, 0 V) supplied from the voltage selection circuit 31 B, and applies the non-selection voltage Vinh (in this example, 3 V) to the column selection line CL 3 .

As a result, in the memory array unit MAU, as illustrated in FIG. 10 , the two memory cells MC 6 and MC 25 are selected as targets for the reset operation OP 2 .

The memory cell MC 6 is the memory cell MC formed in the storage layer L 0 ; therefore, the selection voltage Vnrst (in this example, 0 V) applied to the column selection line CL 2 is supplied to the terminal TU of the memory cell MC 6 , and the selection voltage Vprst (in this example, 6 V) applied to the row selection line RL 1 is supplied to the terminal TL of the memory cell MC 6 . As a result, in the memory cell MC 6 , as illustrated in FIG. 4 , a reset current Irst (a reset current Irst 1 ) flows from the terminal TL toward the terminal TU, thus resetting the storage element VR. As illustrated in FIGS. 10, 11A, and 11B , the reset current Irst 1 flows through the voltage selection circuit 21 A, the current limiting circuit 22 A, the decoder 23 A, the row selection line RL 1 , the memory cell MC 6 , the column selection line CL 2 , the decoder 32 B, and the voltage selection circuit 31 B in this order.

Meanwhile, the memory cell MC 25 is the memory cell MC formed in the storage layer L 1 ; therefore, the selection voltage Vnrst (in this example, 0 V) applied to the row selection line RL 6 is supplied to the terminal TU of the memory cell MC 25 , and the selection voltage Vprst (in this example, 6 V) applied to the column selection line CL 1 is supplied to the terminal TL of the memory cell MC 25 . As a result, in the memory cell MC 25 , the reset current Irst (a reset current Irst 2 ) flows from the terminal TL toward the terminal TU, thus resetting the storage element VR. As illustrated in FIGS. 10, 11A, and 11B , the reset current Irst 2 flows through the voltage selection circuit 31 A, the decoder 32 A, the column selection line CL 1 , the memory cell MC 25 , the row selection line RL 6 , the decoder 23 B, the current limiting circuit 22 B, and the voltage selection circuit 21 B in this order.

Thus, in the memory array unit MAU, it is possible to perform the reset operation OP 2 on two memory cells MC (in this example, MC 6 and MC 25 ) at the same time. At the time, as illustrated in FIGS. 10, 11A, and 11B , two current paths different from each other are formed in the memory array unit MAU.

(Sense Operation OP 3 )

FIG. 12 schematically illustrates an operation in a case of performing the sense operation OP 3 on the two memory cells MC 6 and MC 25 . FIGS. 13A and 13B schematically illustrate an operation of the array driver AD in the sense operation OP 3 . FIG. 13A illustrates an operation of the row selection line driver 20 , and FIG. 13B illustrates an operation of the column selection line driver 30 . In FIG. 12 , the selection line to which the selection voltage Vpsns (in this example, 5 V) is applied is indicated by a wide solid line, and the selection line to which the selection voltage Vnsns (in this example, 1 V) is applied is indicated by a wide dashed line.

In the example in FIG. 12 , the row selection line driver 20 applies the selection voltage Vnsns (in this example, 1 V) to the row selection line RL 1 , applies the selection voltage Vpsns (in this example, 5 V) to the row selection line RL 6 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining row selection lines RL 0 , RL 2 to RL 5 , and RL 7 . In addition, the column selection line driver 30 applies the selection voltage Vnsns (in this example, 1 V) to the column selection line CL 1 , applies the selection voltage Vpsns (in this example, 5 V) to the column selection line CL 2 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining column selection lines CL 0 and CL 3 .

At this time, as illustrated in FIG. 13A , in the voltage selection circuit 21 A in the row selection line driver 20 , the transistor 203 is turned on while the transistors 201 and 202 are turned off. This causes the voltage selection circuit 21 A to output the selection voltage Vnsns (in this example, 1 V). Meanwhile, in the voltage selection circuit 21 B, the transistor 223 is turned on while the transistors 221 and 222 are turned off. This causes the voltage selection circuit 21 B to output the selection voltage Vpsns (in this example, 5 V). In other words, in the row selection line driver 20 , the gate of the transistor 203 is supplied with the logic signal Vgrsns, and the gate of the transistor 223 is supplied with the logic signal Vgrsnsb that is the inverted signal of the logic signal Vgrsns. This sets the logic signal Vgrsns to the high level, thus turning on the transistors 203 and 223 at the same time. As a result, each of the voltage selection circuits 21 A and 21 B outputs, out of the two selection voltages Vpsns and Vnsns used in the sense operation OP 3 , one voltage different from the other.

Then, the decoder 23 A applies, to the row selection line RL 1 , the selection voltage Vnsns (in this example, 1 V) supplied from the voltage selection circuit 21 A via the current limiting circuit 22 A, and applies the non-selection voltage Vinh (in this example, 3 V) to the row selection lines RL 0 , RL 2 , and RL 3 . In addition, the decoder 23 B applies, to the row selection line RL 6 , the selection voltage Vpsns (in this example, 5 V) supplied from the voltage selection circuit 21 B via the current limiting circuit 22 B, and applies the non-selection voltage Vinh (in this example, 3V) to the row selection lines RL 4 , RL 5 , and RL 7 .

In addition, as illustrated in FIG. 13B , in the voltage selection circuit 31 A in the column selection line driver 30 , the transistor 306 is turned on while the transistors 301 to 305 are turned off. This causes the voltage selection circuit 31 A to output the selection voltage Vnsns (in this example, 1 V). Meanwhile, in the voltage selection circuit 31 B, the transistor 325 are turned on while the transistors 321 to 324 and 326 are turned off. This causes the voltage selection circuit 31 B to output the selection voltage Vpsns (in this example, 5 V). In other words, in the column selection line driver 30 , the gate of the transistor 306 is supplied with the logic signal Vgcsns 1 , and the gate of the transistor 325 is supplied with the logic signal Vgcsns 1 b that is the inverted signal of the logic signal Vgcsns 1 . This sets the logic signal Vgcsns 1 to the high level, thus turning on the transistors 306 and 325 at the same time. As a result, each of the voltage selection circuits 31 A and 31 B outputs, out of the two selection voltages Vpsns and Vnsns used in the sense operation OP 3 , one voltage different from the other.

Then, the decoder 32 A applies, to the column selection line CL 1 , the selection voltage Vnsns (in this example, 1 V) supplied from the voltage selection circuit 31 A, and applies the non-selection voltage Vinh (in this example, 3 V) to the column selection line CL 0 . In addition, the decoder 32 B applies, to the column selection line CL 2 , the selection voltage Vpsns (in this example, 5 V) supplied from the voltage selection circuit 31 B, and applies the non-selection voltage Vinh (in this example, 3 V) to the column selection line CL 3 .

As a result, in the memory array unit MAU, as illustrated in FIG. 12 , the two memory cells MC 6 and MC 25 are selected as targets for the sense operation OP 3 .

The memory cell MC 6 is the memory cell MC formed in the storage layer L 0 ; therefore, the selection voltage Vpsns (in this example, 5 V) applied to the column selection line CL 2 is supplied to the terminal TU of the memory cell MC 6 , and the selection voltage Vnsns (in this example, 1 V) applied to the row selection line RL 1 is supplied to the terminal TL of the memory cell MC 6 . As a result, in the memory cell MC 6 , as illustrated in FIG. 4 , a sense current Isns (a sense current Isns 1 ) flows from the terminal TU toward the terminal TL. As illustrated in FIGS. 12, 13A, and 13B , the sense current Isns 1 flows through the voltage selection circuit 31 B, the decoder 32 B, the column selection line CL 2 , the memory cell MC 6 , the row selection line RL 1 , the decoder 23 A, the current limiting circuit 22 A, and the voltage selection circuit 21 A in this order.

Meanwhile, the memory cell MC 25 is the memory cell MC formed in the storage layer L 1 ; therefore, the selection voltage Vpsns (in this example, 5 V) applied to the row selection line RL 6 is supplied to the terminal TU of the memory cell MC 25 , and the selection voltage Vnsns (in this example, 1 V) applied to the column selection line CL 1 is supplied to the terminal TL of the memory cell MC 25 . As a result, in the memory cell MC 25 , the sense current Isns (a sense current Isns 2 ) flows from the terminal TU toward the terminal TL. As illustrated in FIGS. 12, 13A, and 13B , the sense current Isns 2 flows through the voltage selection circuit 21 B, the current limiting circuit 22 B, the decoder 23 B, to the row selection line RL 6 , to the memory cell MC 25 , to the column selection line CL 1 , the decoder 32 A, and the voltage selection circuit 31 A in this order.

Thus, in the memory array unit MAU, it is possible to perform the sense operation OP 3 on two memory cells MC (in this example, MC 6 and MC 25 ) at the same time. At the time, as illustrated in FIGS. 12, 13A, and 13B , two current paths different from each other are formed in the memory array unit MAU.

In this sense operation OP 3 , as illustrated in FIG. 13A , in the sense amplifier 24 A in the row selection line driver 20 , the gate of the transistor 214 is supplied with the signal Vsaen that is an analog voltage. This causes the transistor 214 to function as a current source, and the sense amplifier 24 A generates the signal SAout 0 through comparing the voltage at the node N 23 A and the voltage Vref. This signal SAout 0 corresponds to the resistance state RS of the storage element VR in the memory cell MC 6 . In other words, in the foregoing description, for convenience of description, the voltage at the row selection line RL 1 is described as 1 V. However, actually, the current limiting circuit 22 A limits the current value of the current flowing from the decoder 23 A to the voltage selection circuit 21 A; therefore, the voltage at the row selection line RL 1 becomes a voltage higher than 1 V corresponding to the resistance state RS of the storage element VR in the memory cell M 6 . This makes it possible for the sense amplifier 24 A to read data stored in the memory cell MC 6 through comparing the voltage at the node N 23 A and the voltage Vref.

Likewise, in the sense amplifier 24 B, the gate of the transistor 234 is supplied with the signal Vsaen that is an analog voltage. This causes the sense amplifier 24 B to generate the signal SAout 1 through comparing the voltage at the node N 23 B and the voltage Vref. This signal SAout 1 corresponds to the resistance state RS of the storage element VR in the memory cell MC 25 . In other words, in the foregoing description, for convenience of description, the voltage at the row selection line RL 6 is described as 5 V. However, actually, the current limiting circuit 22 B limits the current value of the current flowing from the voltage selection circuit 21 B to the decoder 23 B; therefore, the voltage at the row selection line RL 6 becomes a voltage lower than 5 V corresponding to the resistance state RS of the storage element VR in the memory cell MC 25 . This makes it possible for the sense amplifier 24 B to read data stored in the memory cell MC 25 through comparing the voltage at the node N 23 B and the voltage Vref.

Thus, in the storage device 1 , the row selection line driver 20 is configured using dual drivers 20 A and 20 B, to cause these dual drivers 20 A and 20 B to output selection voltages different from each other. In addition, the column selection line driver 30 is configured using two drivers 30 A and 30 B, to cause these two drivers 30 A and 30 B to output voltages different from each other. This allows the storage device 1 to access two memory cells MC at the same time. Particularly, in a case of accessing two memory cells MC, two current paths different from each other are formed in the storage device 1 . This makes it possible to increase reliability in the data write operation and the data read operation in the storage device 1 , as compared to a comparative example described below.

In addition, in the storage device 1 , as illustrated in FIGS. 3 and 6 , the decoder 23 A drives the row selection lines RL 0 to RL 3 formed in the same layer. Accordingly, the voltage selection circuit 21 A, which supplies the selection voltage to the decoder 23 A, does not necessarily output the selection voltages Vpset, Vnrst, and Vpsns, thus making it possible to reduce the number of transistors. In other words, the row selection lines RL 0 to RL 3 are coupled to the terminals TL of the 16 memory cells MC 0 to MC 15 stored in the storage layer L 0 . Thus, to the row selection line RL related to the selected memory cell MC of the row selection lines RL 0 to RL 3 , the decoder 23 A applies the selection voltage Vnset in the set operation OP 1 , applies the selection voltage Vprst in the reset operation OP 2 , and applies the selection voltage Vnsns in the sense operation OP 3 . In other words, the decoder 23 A does not apply the selection voltage Vpset, Vnrst, or Vpsns to the row selection line RL related to the selected memory cell MC. Accordingly, the voltage selection circuit 21 A does not necessarily output the selection voltages Vpset, Vnrst, and Vpsns, thus making it possible to reduce the number of transistors, as compared to the voltage selection circuits 31 A and 31 B ( FIG. 7 ) that output the six selection voltages Vpset, Vnset, Vprst, Vnrst, Vpsns, and Vnsns. Likewise, as illustrated in FIGS. 3 and 6 , the decoder 23 B drives the row selection lines RL 4 to RL 7 formed in the same layer, and accordingly, the voltage selection circuit 21 B does not necessarily output the selection voltages Vnset, Vprst, and Vnsns, thus making it possible to reduce the number of transistors.

Comparative Example

Next, a storage device 1 R according to a comparative example is described. In the storage device 1 R, a row selection line driver is configured using a single driver, and a column selection line driver is configured using a single driver. As with the storage device 1 ( FIG. 1 ) according to the present embodiment, the storage device 1 R includes a memory array unit MAUR. As with the memory array unit MAU ( FIG. 2 ) according to the present embodiment, the memory array unit MAUR includes a row selection line driver 20 R and a column selection line driver 30 R.

FIG. 14 illustrates a configuration example of the row selection line driver 20 R. The row selection line driver 20 R includes a voltage selection circuit 21 R, a current limiting circuit 22 R, a decoder 23 R, and a sense amplifier 24 R. In addition, although not illustrated, the row selection line driver 20 A also includes an inverting circuit that respectively generates, on the basis of logic signals Vgrset 0 , Vgrset 1 , Vgrrst 0 , Vgrrst 1 , Vgrsns 0 , Vgrsns 1 , and Vgr 0 to Vgr 7 supplied from the microcontroller MCON, logic signals Vgrset 0 b , Vgrset 1 b , Vgrrst 0 b , Vgrrst 1 b , Vgrsns 0 b , Vgrsns 1 b , and Vgr 0 b to Vgr 7 b each of which is the inverted signal of a corresponding one of these logic signals.

The voltage selection circuit 21 R outputs one of the selection voltages Vpset, Vnset, Vprst, Vnrst, Vpsns, and Vnsns on the basis of the logic signals Vgrset 0 , Vgrset 1 , Vgrrst 0 , Vgrrst 1 , Vgrsns 0 , and Vgrsns 1 supplied from the microcontroller MCON. The voltage selection circuit 21 R includes transistors 251 to 256 . The transistors 251 , 253 , and 255 are p-type MOS transistors, and the transistors 252 , 254 , and 256 are n-type MOS transistors. The transistor 251 has a gate supplied with the logic signal Vgcset 1 b that is the inverted signal of the logic signal Vgrset 1 , a source supplied with the selection voltage Vpset (for example, 6 V), and a drain coupled to a node N 21 R. The transistor 252 has a gate supplied with the logic signal Vgrset 0 , a source supplied with the selection voltage Vnset (for example, 0 V), and a drain coupled to the node N 21 R. The transistor 253 has a gate supplied with the logic signal Vgrrst 0 b that is the inverted signal of the logic signal Vgrrst 0 , a source supplied with the selection voltage Vprst (for example, 6 V), and a drain coupled to the node N 21 R. The transistor 254 has a gate supplied with the logic signal Vgrrst 1 , a source supplied with the selection voltage Vnrst (for example, 0 V), and a drain coupled to the node N 21 R. The transistor 255 has a gate supplied with the logic signal Vgrsns 1 b that is the inverted signal of the logic signal Vgrsns 1 , a source supplied with the selection voltage Vpsns (for example, 5 V), and a drain coupled to the node N 21 R. The transistor 256 has a gate supplied with the logic signal Vgrsns 0 , a source supplied with the selection voltage Vnsns (for example, 1 V), and a drain coupled to the node N 21 R.

The current limiting circuit 22 R limits the current value of a current flowing between the voltage selection circuit 21 R and the decoder 23 R, on the basis of the signals Vpcmp and Vncmp supplied from the microcontroller MCON. The current limiting circuit 22 R includes transistors 257 and 258 . The transistor 257 is a p-type MOS transistor, and the transistor 258 is an n-type MOS transistor. The transistor 257 has a gate supplied with the signal Vpcmp, a source coupled to the node N 21 R, and a drain coupled to a node N 23 R. The transistor 258 has a gate supplied with the signal Vncmp, a source coupled to the node N 21 R, and a drain coupled to the node N 23 R.

In the set operation OP 1 , in a case where the voltage selection circuit 21 R outputs the selection voltage Vpset (for example, 6 V), the current limiting circuit 22 R limits, on the basis of the signal Vpcmp that is an analog voltage supplied from the microcontroller MCON, the current value of the current flowing from the voltage selection circuit 21 R to the decoder 23 R to a predetermined current value (for example, 10 uA) or smaller. In addition, in the set operation OP 1 , in a case where the voltage selection circuit 21 R outputs the selection voltage Vnset (for example, 0 V), the current limiting circuit 22 R limits, on the basis of the signal Vncmp that is an analog voltage supplied from the microcontroller MCON, the current value of the current flowing from the decoder 23 R to the voltage selection circuit 21 R to a predetermined current value (for example, 10 uA) or smaller. In addition, in the reset operation OP 2 , in a case where the voltage selection circuit 21 R outputs the selection voltage Vprst (for example, 6 V), the current limiting circuit 22 R operates not to limit the current, on the basis of the low-level signal Vpcmp supplied from the microcontroller MCON. In addition, in the reset operation OP 2 , in a case where the voltage selection circuit 21 R outputs the selection voltage Vnrst (for example, 0 V), the current limiting circuit 22 R operates not to limit the current, on the basis of the high-level signal Vncmp supplied from the microcontroller MCON. In addition, in the sense operation OP 3 , in a case where the voltage selection circuit 21 R outputs the selection voltage Vpsns (for example, 5 V), the current limiting circuit 22 R limits, on the basis of the signal Vpcmp that is an analog voltage supplied from the microcontroller MCON, the current value of the current flowing from the voltage selection circuit 21 R to the decoder 23 R to a predetermined current value (for example, 1 uA) or smaller. In addition, in the sense operation OP 3 , in a case where the voltage selection circuit 21 R outputs the selection voltage Vnsns (for example, 1 V), the current limiting circuit 22 R limits, on the basis of the signal Vncmp that is an analog voltage supplied from the microcontroller MCON, the current value of the current flowing from the decoder 23 R to the voltage selection circuit 21 R to a predetermined current value (for example, 1 uA) or smaller.

The decoder 23 R selectively applies, to the row selection lines RL 0 to RL 7 , the selection voltage supplied from the voltage selection circuit 21 R via the current limiting circuit 22 R, on the basis of the logic signals Vgr 0 to Vgr 7 supplied from the microcontroller MCON. The decoder 23 R includes transistors 259 to 274 . The transistors 259 to 274 are n-type MOS transistors. The transistor 259 has a gate supplied with the logic signal Vgr 0 , a source coupled to the node N 23 R, and a drain coupled to a drain of the transistor 260 and the row selection line RL 0 . The transistor 260 has a gate supplied with the logic signal Vgr 0 b that is the inverted signal of the logic signal Vgr 0 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 259 and the row selection line RL 0 . The transistor 261 has a gate supplied with the logic signal Vgr 1 b that is the inverted signal of the logic signal Vgr 1 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to a drain of the transistor 262 and the row selection line RL 1 . The transistor 262 has a gate supplied with the logic signal Vgr 1 , a source coupled to the node N 23 R, and the drain coupled to the drain of the transistor 261 and the row selection line RL 1 . The same applies to the transistors 263 to 274 .

As with the sense amplifiers 24 A and 24 B ( FIG. 6 ), the sense amplifier 24 R determines the resistance state RS of the memory cell MC on the basis of the signal Vsaen supplied from the microcontroller MCON. The sense amplifier 24 R has a configuration similar to those of the sense amplifiers 24 A and 24 B. The sense amplifier 24 R includes transistors 275 to 279 . For example, the transistors 275 to 279 respectively correspond to the transistors 214 to 218 in the sense amplifier 24 A.

FIG. 15 illustrates a configuration example of the column selection line driver 30 R. The column selection line driver 30 R includes a voltage selection circuit 31 R and a decoder 32 R. In addition, although not illustrated, the column selection line driver 30 R also includes an inverting circuit that respectively generates, on the basis of the logic signals Vgcset 0 , Vgcset 1 , Vgcrst 0 , Vgcrst 1 , Vgcsns 0 , Vgcsns 1 , and Vgc 0 to Vgc 3 supplied from the microcontroller MCON, the logic signals Vgcset 0 b , Vgcset 1 b , Vgcrst 0 b , Vgcrst 1 b , Vgcsns 0 b , Vgcsns 1 b , and Vgc 0 b to Vgc 3 b each of which is the inverted signal of a corresponding one of these logic signals.

The voltage selection circuit 31 R outputs one of the selection voltages Vpset, Vnset, Vprst, Vnrst, Vpsns, and Vnsns on the basis of the logic signals Vgcset 0 , Vgcset 1 , Vgcrst 0 , Vgcrst 1 , Vgcsns 0 , and Vgcsns 1 supplied from the microcontroller MCON. The voltage selection circuit 31 R has a configuration similar to that of the voltage selection circuit 31 A ( FIG. 7 ). The voltage selection circuit 31 R includes transistors 351 to 356 . The transistors 351 to 356 respectively correspond to the transistors 301 to 306 in the voltage selection circuit 31 A. The drains of the transistors 351 to 356 are coupled to the node N 32 R.

The decoder 32 R selectively applies, to the column selection lines CL 0 to CL 3 , the selection voltage supplied from the voltage selection circuit 31 R, on the basis of the logic signals Vgc 0 to Vgc 3 supplied from the microcontroller MCON. The decoder 32 R includes transistors 357 to 364 . The transistors 357 to 364 are n-type MOS transistors. The transistor 357 has a gate supplied with the logic signal Vgc 0 , a source coupled to the node N 32 R, and a drain coupled to a drain of the transistor 358 and the column selection line CL 0 . The transistor 358 has a gate supplied with the logic signal Vgc 0 b that is the inverted signal of the logic signal Vgc 0 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 357 and the column selection line CL 0 . The transistor 359 has a gate supplied with the logic signal Vgc 1 b that is the inverted signal of the logic signal Vgc 1 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to a drain of the transistor 360 and the column selection line CL 1 . The transistor 360 has a gate supplied with the logic signal Vgc 1 , a source coupled to the node N 32 R, and the drain coupled to the drain of the transistor 359 and the column selection line CL 1 . The same applies to the transistors 361 to 364 .

FIG. 16 schematically illustrates an operation in a case of performing the set operation OP 1 on two memory cells MC 5 and MC 6 . In FIG. 16 , the selection line to which the selection voltage Vpset (in this example, 6 V) is applied is indicated by a wide solid line, and the selection line to which the selection voltage Vnset (in this example, 0 V) is applied is indicated by a wide dashed line.

In this example, the row selection line driver 20 R applies the selection voltage Vnset (in this example, 0 V) to the row selection line RL 1 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining row selection lines RL 0 and RL 2 to RL 7 . In addition, the column selection line driver 30 R applies the selection voltage Vpset (in this example, 6 V) to the column selection lines CL 1 and CL 2 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining column selection lines CL 0 and CL 3 . As a result, in the memory array unit MAUR, as illustrated in FIG. 16 , the two memory cells MC 5 and MC 6 are selected as targets for the set operation OP 1 .

At this time, the set current Iset (the set current Iset 1 ) for setting the storage element VR in the memory cell MC 5 flows through the voltage selection circuit 31 R, the decoder 32 R, the column selection line CL 1 , the memory cell MC 5 , the row selection line RL 1 , the decoder 23 R, the current limiting circuit 22 R, and the voltage selection circuit 21 R. In addition, the set current Iset (the set current Iset 2 ) for setting the storage element VR in the memory cell MC 6 flows through the voltage selection circuit 31 R, the decoder 32 R, the column selection line CL 2 , the memory cell MC 6 , the row selection line RL 1 , the decoder 23 R, the current limiting circuit 22 R, and the voltage selection circuit 21 R. Thus, the currents for setting the two memory cells MC flow through the row selection line RL 1 , the voltage selection circuit 31 R, the current limiting circuit 22 R, and the voltage selection circuit 21 R, which causes a possibility that a larger voltage drops and the storage elements VR in the memory cells MC 5 and MC 6 are not settable sufficiently. In addition, for example, in a case where there is a variation in the characteristics of the memory cells MC 5 and MC 6 due to process variation, there is a possibility that the current flows intensively to one of the memory cells MC 5 and MC 6 . In this case, there is a possibility that the storage element VR in the other of the memory cells MC 5 and MC 6 is not sufficiently set. It is to be noted that in this example, the set operation OP 1 has been described, but the same applies to the reset operation OP 2 . Thus, in the storage device 1 R according to the comparative example, there is a possibility of decreasing reliability in the data write operation.

In contrast, in the storage device 1 according to the present embodiment, the row selection line driver 20 is configured using the dual drivers 20 A and 20 B, to cause these dual drivers 20 A and 20 B to output voltages different from each other. In addition, the column selection line driver 30 is configured using the dual drivers 30 A and 30 B, to cause these dual drivers 30 A and 30 B to output voltages different from each other. Accordingly, in the memory array unit MAU, in a case where two memory cells MC are accessed at the same time in the set operation OP 1 (for example, FIGS. 8, 9A, and 9B ) and the reset operation OP 2 (for example, FIGS. 10, 11A, and 11B ), two current paths different from each other are formed. For example, this prevents the currents related to the two memory cells MC from flowing to one circuit, one row selection line RL, one column selection line CL, and so on, thus making it possible to suppress a voltage drop, and to reduce a possibility of occurrence of a write error.

Furthermore, in the storage device 1 , in the memory array unit MAU, in a case where two memory cells MC are accessed at the same time in the sense operation OP 3 (for example, FIGS. 12, 13A, and 13B ), two current paths different from each other are formed. This makes it possible to suppress a voltage drop, and to reduce a possibility of occurrence of a read error.

Thus, in the storage device 1 , it is possible to suppress a voltage drop, thus making it possible to reduce the possibility of occurrence of the write error and the read error. As a result, it is possible to increase reliability in the data write operation and the data read operation.

In addition, in the storage device 1 , it is thus possible to increase reliability, thus making it possible to reduce write delay time in the data write operation. As a result, this makes it possible to increase data transfer speed in the write operation. In addition, increasing a read current makes it possible to reduce read delay time in the data read operation. As a result, it is possible to increase data transfer speed in the read operation. In addition, for example, miniaturizing the memory cell MC or increasing the number of stacked layers allows for reduction in cost per bit.

[Effects]

As described above, in the present embodiment, the row selection line driver is configured using dual drivers, to cause these dual drivers to output selection voltages different from each other, while the column selection line driver is configured using dual drivers, to cause these dual drivers to output selection voltages different from each other. In a case where two memory cells are accessed at the same time, two current paths different from each other are formed, thus making it possible to increase reliability in the data write operation and the data read operation. In addition, for example, it is possible to increase reliability in this manner, thus making it possible to increase the data transfer speed in the data write operation and the data read operation, or to reduce cost per bit.

Modification Example 1-1

In the foregoing embodiment, two memory cells MC are accessed at the same time, but it is not necessary to constantly access two memory cells MC at the same time. For example, only one memory cell MC may be accessed where necessary, or three or more memory cells MC may be accessed at the same time where necessary. In the following, the present modification example is described in detail.

FIG. 17 schematically illustrates an operation in a case of performing the set operation OP 1 on one memory cell MC (in this example, the memory cell MC 6 ). FIGS. 18A and 18B schematically illustrate an operation of the array driver AD in the set operation OP 1 . FIG. 18A illustrates an operation of the row selection line driver 20 , and FIG. 18B illustrates an operation of the column selection line driver 30 . FIGS. 17, 18A, and 18B respectively correspond to FIGS. 8, 9A, and 9B according to the foregoing embodiment.

In the example in FIG. 17 , the row selection line driver 20 applies the selection voltage Vnset (in this example, 0 V) to the row selection line RL 1 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining row selection lines RL 0 and RL 2 to RL 7 . In addition, the column selection line driver 30 applies the selection voltage Vpset (in this example, 6 V) to the column selection line CL 2 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining column selection lines CL 0 , CL 1 , and CL 3 .

At this time, as illustrated in FIG. 18A , in the voltage selection circuit 21 A in the row selection line driver 20 , the transistor 201 is turned on while the transistors 202 and 203 are turned off. This causes the voltage selection circuit 21 A to output the selection voltage Vnset (in this example, 0 V). Meanwhile, in the voltage selection circuit 21 B, the transistor 221 is turned on while the transistors 222 and 223 are turned off. This causes the voltage selection circuit 21 B to output the selection voltage Vpset (in this example, 6 V).

Then, in the decoder 23 A, the transistors 207 , 209 , 211 , and 212 are turned on while the transistors 206 , 208 , 210 , and 213 are turned off. As a result, the decoder 23 A applies, to the row selection line RL 1 , the selection voltage Vnset (in this example, 0 V) supplied from the voltage selection circuit 21 A via the current limiting circuit 22 A, and applies the non-selection voltage Vinh (in this example, 3 V) to the row selection lines RL 0 , RL 2 , and RL 3 .

In addition, in the decoder 23 B, the transistors 227 , 228 , 231 , and 232 are turned on while the transistors 226 , 229 , 230 , and 233 are turned off. In other words, in the example ( FIG. 9A ) in the foregoing embodiment, the transistor 230 is turned on while the transistor 231 is turned off, but in the present modification example ( FIG. 18A ), the transistor 231 is turned on while the transistor 230 is turned off. As a result, the decoder 23 B applies the non-selection voltage Vinh (in this example, 3 V) to four row selection lines RL 4 to RL 7 .

In addition, as illustrated in FIG. 18B , in the voltage selection circuit 31 A in the column selection line driver 30 , the transistor 302 is turned on while the transistors 301 and 303 to 306 are turned off. This causes the voltage selection circuit 31 A to output the selection voltage Vnset (in this example, 0 V). Meanwhile, in the voltage selection circuit 31 B, the transistor 321 is turned on while the transistors 322 to 326 are turned off. This causes the voltage selection circuit 31 B to output the selection voltage Vpset (in this example, 6 V).

Then, in the decoder 32 A, the transistors 308 and 309 are turned on while the transistors 307 and 310 are turned off. In other words, in the example ( FIG. 9B ) in the foregoing embodiment, the transistor 310 is turned on while the transistor 309 is turned off, but in the present modification example ( FIG. 18B ), the transistor 309 is turned on while the transistor 310 is turned off. As a result, the decoder 32 A applies the non-selection voltage Vinh (in this example, 3 V) to two column selection lines CL 0 and CL 1 .

In addition, in the decoder 32 B, the transistors 327 and 329 are turned on while the transistors 328 and 330 are turned off. As a result, the decoder 32 B applies, to the column selection line CL 2 , the selection voltage Vpset (in this example, 6 V) supplied from the voltage selection circuit 31 B, and applies the non-selection voltage Vinh (in this example, 3 V) to the column selection line CL 3 .

As a result, in the memory array unit MAU, as illustrated in FIG. 17 , one memory cell MC 6 is selected as a target for the set operation OP 1 . Then, in the memory array unit MAU, as illustrated in FIGS. 17, 18A, and 18B , the set current Iset (the set current Iset 1 ) through the voltage selection circuit 31 B, the decoder 32 B, the column selection line CL 2 , the memory cell MC 6 , the row selection line RL 1 , the decoder 23 A, the current limiting circuit 22 A, and the voltage selection circuit 21 A in this order.

Next, an example of a case of accessing three or more memory cells MC at the same time is described in detail.

FIG. 19 schematically illustrates an operation in a case of performing the set operation OP 1 on six memory cells MC (in this example, the memory cells MC 6 , MC 7 , MC 10 , MC 11 , MC 21 , and MC 25 ). FIGS. 20A and 20B schematically illustrate an operation of the array driver AD in the set operation OP 1 . FIG. 20A illustrates an operation of the row selection line driver 20 , and FIG. 20B illustrates an operation of the column selection line driver 30 . FIGS. 19, 20A , and 20 B respectively correspond to FIGS. 8, 9A, and 9B .

In the example in FIG. 19 , the row selection line driver 20 applies the selection voltage Vnset (in this example, 0 V) to the row selection lines RL 1 and RL 2 , applies the selection voltage Vpset (in this example, 6 V) to the row selection lines RL 5 and RL 6 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining row selection lines RL 0 , RL 3 , RL 4 , and RL 7 . In addition, the column selection line driver 30 applies the selection voltage Vpset (in this example, 6 V) to the column selection lines CL 2 and CL 3 , applies the selection voltage Vnset (in this example, 0 V) to the column selection line CL 1 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining column selection line CL 0 .

At this time, as illustrated in FIG. 20A , in the decoder 23 A in the row selection line driver 20 , the transistors 207 , 209 , 210 , and 212 are turned on while the transistors 206 , 208 , 211 , and 213 are turned off. As a result, the decoder 23 A applies, to the row selection lines RL 1 and RL 2 , the selection voltage Vnset (in this example, 0 V) supplied from the voltage selection circuit 21 A via the current limiting circuit 22 A, and applies the non-selection voltage Vinh (in this example, 3 V) to the row selection lines RL 0 and RL 3 .

In addition, in the decoder 23 B, the transistors 227 , 229 , 230 , and 232 are turned on while the transistors 226 , 228 , 231 , and 233 are turned off. As a result, the decoder 23 B applies, to the row selection lines RL 5 and RL 6 , the selection voltage Vpset (in this example, 6 V) supplied from the voltage selection circuit 21 B via the current limiting circuit 22 B, and applies the non-selection voltage Vinh (in this example, 3 V) to the row selection lines RL 4 and RL 7 .

In addition, as illustrated in FIG. 20B , in the decoder 32 A in the column selection line driver 30 , the transistors 308 and 310 are turned on while the transistors 307 and 309 are turned off. As a result, the decoder 32 A applies the selection voltage Vnset (in this example, 0 V) to the column selection line CL 1 , and applies the non-selection voltage Vinh (in this example, 3 V) to the column selection line CL 0 .

In addition, in the decoder 32 B, the transistors 327 and 330 are turned on while the transistors 328 and 329 are turned off. As a result, the decoder 32 B applies, to the column selection lines CL 2 and CL 3 , the selection voltage Vpset (in this example, 6 V) supplied from the voltage selection circuit 31 B.

As a result, in the memory array unit MAU, as illustrated in FIG. 19 , six memory cells MC 6 , MC 7 , MC 10 , MC 11 , MC 21 , and MC 25 are selected as targets for the set operation OP 1 . At this time, a total current of a set current Iset 5 related to the memory cell MC 21 and a set current Iset 6 related to the memory cell MC 25 flows through the column selection line CL 1 , a total current of the set current Iset 1 related to the memory cell MC 6 and a set current Iset 3 related to the memory cell MC 10 flows through the column selection line CL 2 , and a total current of the set current Iset 2 related to the memory cell MC 7 and a set current Iset 4 related to the memory cell MC 11 flows through the column selection line CL 3 . In addition, a total current of the set currents Iset 1 and Iset 2 flows through the row selection line RL 1 , a total current of the set currents Iset 3 and Iset 4 flows through the row selection line RL 2 , the set current Iset 5 flows through the row selection line RL 5 , and the set current Iset 6 flows through the row selection line RL 6 .

In this case, compared to the case of selecting two memory cells MC as in the set operation OP 1 ( FIGS. 8, 9A, and 9B ) according to the foregoing embodiment, for example, a significant voltage may drop due to the row selection lines RL 1 and RL 2 and the column selection lines CL 1 to CL 3 . However, for example, if a write error is at an acceptable level, the operation may be performed in this manner.

In other words, for example, in a case of performing the set operation OP 1 on the six memory cells MC using the storage device 1 R according to the foregoing comparative example, as illustrated in FIG. 21 , for example, it is possible to select the memory cells MC 5 to MC 7 and MC 9 to MC 11 . At this time, a total current of the set current Iset 1 related to the memory cell MC 5 and the set current Iset 4 related to the memory cell MC 9 flows through the column selection line CL 1 , a total current of the set current Iset 2 related to the memory cell MC 6 and the set current Iset 5 related to the memory cell MC 10 flows through the column selection line CL 2 , and a total current of the set current Iset 3 related to the memory cell MC 7 and the set current Iset 6 related to the memory cell MC 11 flows through the column selection line CL 3 . In addition, a total current of the set currents Iset 1 to Iset 3 flows through the row selection line RL 1 , and a total current of the set currents Iset 4 to Iset 6 flows through the row selection line RL 2 . Thus, in this example, for example, the currents related to three memory cells MC 5 , MC 6 , and MC 7 flow through the row selection line RL 1 , and for example, the currents related to three memory cells MC 9 , MC 10 , and MC 11 flow through the row selection line RL 2 , thus causing a possibility that a significant voltage drops. In contrast, in the storage device 1 ( FIG. 19 ), for example, the currents related to the two memory cells MC 5 and MC 6 flow through the row selection line RL 1 .

Thus, in the storage device 1 , even in a case of accessing three or more memory cells MC at the same time, it is possible to suppress an amount of the current flowing through one row selection line RL or one column selection line CL. This makes it possible to increase reliability in the data write operation and the data read operation. [Modification Example 1-2]

In the foregoing embodiment, the row selection line driver 20 applies the non-selection voltage Vinh (for example, 3 V) to the row selection line RL that is not selected from the row selection lines RL 0 to RL 7 , and the column selection line driver 30 applies the non-selection voltage Vihn (for example, 3 V) to the column selection line CL that is not selected from the column selection lines CL 0 to CL 3 , but this is not limitative. Alternatively, the row selection line RL and the column selection line CL that are not selected may be set to a floating state. In the following, a storage device 1 A according to the present modification example is described in detail.

As with the storage device 1 ( FIG. 1 ) according to the foregoing embodiment, the storage device 1 A includes a memory array unit MAUL As with the memory array unit MAU ( FIG. 2 ) according to the foregoing embodiment, the memory array unit MAU 1 , includes an array driver AD 1 that includes a row selection line driver 40 and a column selection line driver 50 .

FIG. 22 illustrates a configuration example of the row selection line driver 40 . The row selection line driver 40 includes decoders 43 A and 43 B. The decoder 43 A corresponds to the decoder 23 A ( FIG. 6 ) according to the foregoing embodiment from which the four transistors 207 , 208 , 211 , and 212 are omitted. Likewise, the decoder 43 B corresponds to the decoder 23 B ( FIG. 6 ) according to the foregoing embodiment from which the four transistors 227 , 228 , 231 , and 232 are omitted. The voltage selection circuit 21 A, the current limiting circuit 22 A, the decoder 43 A, and the sense amplifier 24 A are included in a driver 40 A, and the voltage selection circuit 21 B, the current limiting circuit 22 B, the decoder 43 B, and the sense amplifier 24 B are included in a driver 40 B.

FIG. 23 illustrates a configuration example of the column selection line driver 50 . The column selection line driver 50 includes decoders 52 A and 52 B. The decoder 52 A corresponds to the decoder 32 A ( FIG. 7 ) according to the foregoing embodiment from which the two transistors 308 and 309 are omitted. Likewise, the decoder 52 B corresponds to the decoder 32 B ( FIG. 7 ) according to the foregoing embodiment from which the two transistors 328 and 329 are omitted. The voltage selection circuit 31 A and the decoder 52 A are included in a driver 50 A, and the voltage selection circuit 31 B and the decoder 52 B are included in a driver 50 B.

In the storage device 1 A, this configuration makes it possible to reduce the number of transistors. As the number of the row selection lines RL and the number of the column selection lines CL are larger, the present modification example is more effective.

Modification Example 1-3

In the foregoing embodiment, as illustrated in FIG. 6 , the voltage selection circuits 21 A and 21 B in the row selection line driver 20 supply the selection voltage to the decoders 23 A and 23 B, and as illustrated in FIG. 7 , the voltage selection circuits 31 A and 31 B in the column selection line driver 30 supply the selection voltage to the decoders 32 A and 32 B, but this is not limitative. Alternatively, for example, the voltage selection circuits 31 A and 31 B may be omitted and the voltage selection circuits 21 A and 21 B may supply the selection voltage to the decoders 23 A and 23 B and the decoders 32 A and 32 B, or the voltage selection circuits 21 A and 21 B may be omitted and the voltage selection circuits 31 A and 31 B may supply the selection voltage to the decoders 23 A and 23 B and the decoders 32 A and 32 B. In the following, an example in which the voltage selection circuits 21 A and 21 B supply the selection voltage to the decoders 23 A and 23 B and the decoders 32 A and 32 B is described in detail.

As with the storage device 1 ( FIG. 1 ) according to the foregoing embodiment, a storage device 1 B according to the present modification example includes a memory array unit MAU 2 . As with the memory array unit MAU ( FIG. 2 ) according to the foregoing embodiment, the memory array unit MAU 2 , includes an array driver AD 2 that includes a row selection line driver 60 and a column selection line driver 70 .

FIG. 24 illustrates a configuration example of the row selection line driver 60 . The row selection line driver 60 includes the voltage selection circuits 21 A and 21 B. The voltage selection circuit 21 A also supplies the selection voltage to the column selection line driver 70 , and the voltage selection circuit 21 B also supplies the selection voltage to the column selection line driver 70 . The voltage selection circuit 21 A, the current limiting circuit 22 A, the decoder 23 A, and the sense amplifier 24 A are included in a driver 60 A, and the voltage selection circuit 21 B, the current limiting circuit 22 B, the decoder 23 B, and the sense amplifier 24 B are included in a driver 60 B.

FIG. 25 illustrates a configuration example of the column selection line driver 70 . The column selection line driver 70 includes transistors 71 to 74 . In addition, although not illustrated, the column selection line driver 70 also includes an inverting circuit that respectively generates, on the basis of logic signals Vgsw and Vgc 0 to Vgc 3 supplied from the microcontroller MCON, logic signals Vgswb and Vgc 0 b to Vgc 3 b each of which is an inverted signal of a corresponding one of these logic signals.

The transistor 71 has a gate supplied with the logic signal Vgswb that is the inverted signal of the logic signal Vgsw, a source coupled to the node N 21 A of the voltage selection circuit 21 A, and a drain coupled to the node N 32 A. The transistor 72 has a gate supplied with the logic signal Vgswb that is the inverted signal of the logic signal Vgsw, a source coupled to the node N 21 B of the voltage selection circuit 21 B, and a drain coupled to the node N 32 B. The transistor 73 has a gate supplied with the logic signal Vgsw, a source coupled to the node N 21 A of the voltage selection circuit 21 A, and a drain coupled to the node N 32 B. The transistor 74 has a gate supplied with the logic signal Vgsw, a source coupled to the node N 21 B of the voltage selection circuit 21 B, and a drain coupled to the node N 32 A. The decoder 32 A is included in a driver 70 A, and the decoder 32 B is included in a driver 70 B.

Here, a circuit including the transistors 71 to 74 correspond to a specific example of a “fifth supply section” in the present disclosure. The logic signals Vgsw and Vgswb correspond to a specific example of a “fifth selection signal line” in the present disclosure.

Next, as in the case illustrated in FIG. 8 , an operation of the array driver AD 2 in a case of performing the set operation OP 1 on the two memory cells MC 6 and MC 25 is described.

FIGS. 26A and 26B schematically illustrate an operation of the array driver AD 2 in the set operation OP 1 . FIG. 26A illustrates an operation of the row selection line driver 60 , and FIG. 26B illustrates an operation of the column selection line driver 70 .

In this example, as illustrated in FIG. 8 , the row selection line driver 60 applies the selection voltage Vnset (in this example, 0 V) to the row selection line RL 1 , applies the selection voltage Vpset (in this example, 6 V) to the row selection line RL 6 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining row selection lines RL 0 , RL 2 to RL 5 , and RL 7 . In addition, the column selection line driver 70 applies the selection voltage Vnset (in this example, 0 V) to the column selection line CL 1 , applies the selection voltage Vpset (in this example, 6 V) to the column selection line CL 2 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining column selection lines CL 0 and CL 3 .

At this time, as illustrated in FIG. 26A , in the voltage selection circuit 21 A in the row selection line driver 60 , the transistor 201 is turned on while the transistors 202 and 203 are turned off. This causes the voltage selection circuit 21 A to output the selection voltage Vnset (in this example, 0 V). Then, the voltage selection circuit 21 A supplies the selection voltage Vnset (in this example, 0 V) to the decoder 23 A via the current limiting circuit 22 A, and to the column selection line driver 70 . Meanwhile, in the voltage selection circuit 21 B, the transistor 221 is turned on while the transistors 222 and 223 are turned off. This causes the voltage selection circuit 21 B to output the selection voltage Vpset (in this example, 6 V). Then, the voltage selection circuit 21 B supplies the selection voltage Vpset (in this example, 6 V) to the decoder 23 B via the current limiting circuit 22 B, and to the column selection line driver 70 .

The decoder 23 A applies, to the row selection line RL 1 , the selection voltage Vnset (in this example, 0 V) supplied from the voltage selection circuit 21 A via the current limiting circuit 22 A, and applies the non-selection voltage Vinh (in this example, 3 V) to the row selection lines RL 0 , RL 2 , and RL 3 . In addition, the decoder 23 B applies, to the row selection line RL 6 , the selection voltage Vpset (in this example, 6 V) supplied from the voltage selection circuit 21 B via the current limiting circuit 22 B, and applies the non-selection voltage Vinh (in this example, 3V) to the row selection lines RL 4 , RL 5 , and RL 7 .

In addition, as illustrated in FIG. 26B , in the column selection line driver 70 , the transistors 71 and 72 are turned on while the transistors 73 and 74 are turned off. Accordingly, the decoder 32 A is supplied with the selection voltage Vnset (for example, 0 V) outputted by the voltage selection circuit 21 A, and the decoder 32 B is supplied with the selection voltage Vpset (for example, 6 V) outputted by the voltage selection circuit 21 B.

Then, the decoder 32 A applies, to the column selection line CL 1 , the selection voltage Vnset (in this example, 0 V) supplied from the voltage selection circuit 21 A, and applies the non-selection voltage Vinh (in this example, 3 V) to the column selection line CL 0 . In addition, the decoder 32 B applies, to the column selection line CL 2 , the selection voltage Vpset (in this example, 6 V) supplied from the voltage selection circuit 21 B, and applies the non-selection voltage Vinh (in this example, 3 V) to the column selection line CL 3 .

As a result, in the memory array unit MAU 2 , as illustrated in FIG. 8 , the two memory cells MC 6 and MC 25 are selected as targets for the set operation OP 1 .

It is to be noted that in this example, an example of performing the set operation OP 1 on the memory cells MC 6 and MC 25 has been described. Alternatively, for example, in a case of performing the set operation OP 1 on the memory cells MC 5 and MC 26 , in the column selection line driver 70 , the transistors 73 and 74 are turned on while the transistors 71 and 72 are turned off. Accordingly, the decoder 32 A is supplied with the selection voltage Vpset (for example, 6 V) outputted by the voltage selection circuit 21 B in the row selection line driver 60 , and the decoder 32 B is supplied with the selection voltage Vnset (for example, 0 V) outputted by the voltage selection circuit 21 A in the row selection line driver 60 . This causes the decoder 32 A to apply, to the column selection line CL 1 , the selection voltage Vpset (in this example, 6 V) supplied from the voltage selection circuit 21 B, and applies the non-selection voltage Vinh (in this example, 3 V) to the column selection line CL 0 . In addition, the decoder 32 B applies, to the column selection line CL 2 , the selection voltage Vnset (in this example, 0 V) supplied from the voltage selection circuit 21 A, and applies the non-selection voltage Vinh (in this example, 3V) to the column selection line CL 3 . Thus, in the array driver AD 2 , it is possible to perform the set operation OP 1 on the memory cells MC 5 and MC 26 .

In the storage device 1 B, this configuration makes it possible to reduce the number of transistors.

Modification Example 1-4

In the foregoing embodiment, as illustrated in FIGS. 3 and 6 , the decoder 23 A in the row selection line driver 20 drives the row selection lines RL 0 to RL 3 formed in the same layer, and the decoder 23 B drives the row selection lines RL 4 to RL 7 formed in the same layer, but this is not limitative. Alternatively, for example, each decoder may drive, from the row selection lines RL 0 to RL 7 , a row selection line RL that is formed in a different layer. In the following, a storage device 1 C according to the present modification example is described in detail.

As with the storage device 1 ( FIG. 1 ) according to the foregoing embodiment, the storage device 1 C includes a memory array unit MAU 3 . As with the memory array unit MAU ( FIG. 2 ) according to the foregoing embodiment, the memory array unit MAU 3 includes an array driver AD 3 that includes a row selection line driver 80 and the column selection line driver 30 .

FIG. 27 illustrates a configuration example of the row selection line driver 80 . The row selection line driver 80 includes voltage selection circuits 81 A and 81 B and decoders 83 A and 83 B. In addition, although not illustrated, the row selection line driver 80 also includes an inverting circuit that respectively generates, on the basis of the logic signals Vgrset 0 , Vgrset 1 , Vgrrst 0 , Vgrrst 1 , Vgrsns 0 , Vgrsns 1 , and Vgr 0 to Vgr 7 supplied from the microcontroller MCON, the logic signals Vgrset 0 b , Vgrset 1 b , Vgrrst 0 b , Vgrrst 1 b , Vgrsns 0 b , Vgrsns 1 b , and Vgr 0 b to Vgr 7 b each of which is the inverted signal of a corresponding one of these logic signals.

The voltage selection circuit 81 A outputs one of the selection voltages Vpset, Vnset, Vprst, Vnrst, Vpsns, and Vnsns on the basis of the logic signals Vgrset 0 , Vgrset 1 , Vgrrst 0 , Vgrrst 1 , Vgrsns 0 , and Vgrsns 1 supplied from the microcontroller MCON. In other words, in the example ( FIG. 6 ) in the foregoing embodiment, the voltage selection circuit 21 A outputs one of the three selection voltages Vnset, Vprst, and Vnsns. In contrast, in the present modification example ( FIG. 27 ), the voltage selection circuit 81 A outputs one of the six selection voltages Vpset, Vnset, Vprst, Vnrst, Vpsns, and Vnsns. The voltage selection circuit 81 A includes transistors 201 P, 201 N, 202 P, 202 N, 203 P, and 203 N. The transistors 201 P, 202 P, and 203 P are p-type MOS transistors, and the transistors 201 N, 202 N, and 203 N are n-type MOS transistors. The transistor 201 P has a gate supplied with the logic signal Vgcset 1 b that is the inverted signal of the logic signal Vgrset 1 , a source supplied with the selection voltage Vpset (for example, 6 V), and a drain coupled to the node N 21 A. The transistor 201 N has a gate supplied with the logic signal Vgrset 0 , a source supplied with the selection voltage Vnset (for example, 0 V), and a drain coupled to the node N 21 A. The transistor 202 P has a gate supplied with the logic signal Vgrrst 0 b that is the inverted signal of the logic signal Vgrrst 0 , a source supplied with the selection voltage Vprst (for example, 6 V), and a drain coupled to the node N 21 A. The transistor 202 N has a gate supplied with the logic signal Vgrrst 1 , a source supplied with the selection voltage Vnrst (for example, 0 V), and a drain coupled to the node N 21 A. The transistor 203 P has a gate supplied with the logic signal Vgrsns 1 b that is the inverted signal of the logic signal Vgrsns 1 , a source supplied with the selection voltage Vpsns (for example, 5 V), and a drain coupled to the node N 21 A. The transistor 203 N has a gate supplied with the logic signal Vgrsns 0 , a source supplied with the selection voltage Vnsns (for example, 1 V), and a drain coupled to the node N 21 A.

The decoder 83 A selectively applies, to the row selection lines RL 0 , RL 1 , RL 4 , and RL 5 , the selection voltage supplied from the voltage selection circuit 21 A via the current limiting circuit 22 A, on the basis of the logic signals Vgr 0 , Vgr 1 , Vgr 4 , and Vgr 5 supplied from the microcontroller MCON. In other words, in the example ( FIG. 6 ) in the foregoing embodiment, the decoder 23 A selectively applies the selection voltage to the row selection lines RL 0 to RL 3 on the basis of the logic signals Vgr 0 to Vgr 3 . In contrast, in the present modification example ( FIG. 27 ), the decoder 83 A selectively applies the selection voltage to the row selection lines RL 0 , RL 1 , RL 4 , and RL 5 on the basis of the logic signals Vgr 0 , Vgr 1 , Vgr 4 , and Vgr 5 . In the decoder 83 A, the transistor 210 has the gate supplied with the logic signal Vgr 4 , the source coupled to the node N 23 A, and the drain coupled to the drain of the transistor 211 and the row selection line RL 4 . The transistor 211 has the gate supplied with the logic signal Vgr 4 b that is the inverted signal of the logic signal Vgr 4 , the source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 210 and the row selection line RL 4 . The transistor 212 has the gate supplied with the logic signal Vgr 5 b that is the inverted signal of the logic signal Vgr 5 , the source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 213 and the row selection line RL 5 . The transistor 213 has the gate supplied with the logic signal Vgr 5 , the source coupled to the node N 23 A, and the drain coupled to the drain of the transistor 212 and the row selection line RL 5 .

As with the voltage selection circuit 81 A, the voltage selection circuit 81 B outputs one of the selection voltages Vpset, Vnset, Vprst, Vnrst, Vpsns, and Vnsns on the basis of the logic signals Vgrset 0 , Vgrset 1 , Vgrrst 0 , Vgrrst 1 , Vgrsns 0 , and Vgrsns 1 supplied from the microcontroller MCON. The voltage selection circuit 81 B includes transistors 221 P, 221 N, 222 P, 222 N, 223 P, and 223 N. The transistors 221 P, 222 P, and 223 P are p-type MOS transistors, and the transistors 221 N, 222 N, and 223 N are n-type MOS transistors. The transistor 221 P has a gate supplied with the logic signal Vgcset 0 b that is the inverted signal of the logic signal Vgrset 0 , a source supplied with the selection voltage Vpset (for example, 6 V), and a drain coupled to the node N 21 B. The transistor 221 N has a gate supplied with the logic signal Vgrset 1 , a source supplied with the selection voltage Vnset (for example, 0 V), and a drain coupled to the node N 21 B. The transistor 222 P has a gate supplied with the logic signal Vgrrst 1 b that is the inverted signal of the logic signal Vgrrst 1 , a source supplied with the selection voltage Vprst (for example, 6 V), and a drain coupled to the node N 21 B. The transistor 222 N has a gate supplied with the logic signal Vgrrst 0 , a source supplied with the selection voltage Vnrst (for example, 0 V), and a drain coupled to the node N 21 B. The transistor 223 P has a gate supplied with the logic signal Vgrsns 0 b that is the inverted signal of the logic signal Vgrsns 0 , a source supplied with the selection voltage Vpsns (for example, 5 V), and a drain coupled to the node N 21 B. The transistor 223 N has a gate supplied with the logic signal Vgrsns 1 , a source supplied with the selection voltage Vnsns (for example, 1 V), and a drain coupled to the node N 21 B.

As with the decoder 83 A, the decoder 83 B selectively applies, to the row selection lines RL 2 , RL 3 , RL 6 , and RL 7 , the selection voltage supplied from the voltage selection circuit 21 B via the current limiting circuit 22 B on the basis of the logic signals Vgr 2 , Vgr 3 , Vgr 6 , and Vgr 7 supplied from the microcontroller MCON. In the decoder 83 B, the transistor 226 has the gate supplied with the logic signal Vgr 2 , the source coupled to the node N 23 B, and the drain coupled to the drain of the transistor 227 and the row selection line RL 2 . The transistor 227 has the gate supplied with the logic signal Vgr 2 b that is the inverted signal of the logic signal Vgr 2 , the source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 226 and the row selection line RL 2 . The transistor 228 has the gate supplied with the logic signal Vgr 3 b that is the inverted signal of the logic signal Vgr 3 , the source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 229 and the row selection line RL 3 . The transistor 229 has the gate supplied with the logic signal Vgr 3 , the source coupled to the node N 23 B, and the drain coupled to the drain of the transistor 228 and the row selection line RL 3 .

The voltage selection circuit 81 A, the current limiting circuit 22 A, the decoder 83 A, and the sense amplifier 24 A are included in a driver 80 A, and the voltage selection circuit 81 B, the current limiting circuit 22 B, the decoder 83 B, and the sense amplifier 24 B are included in a driver 80 B. For example, as illustrated in FIG. 28 , the driver 80 A is formed, in the substrate surface S, in a region SA below the row selection lines RL 0 , RL 1 , RL 4 , and RL 5 Likewise, the driver 80 B is formed, in the substrate surface S, in a region SB below the row selection lines RL 2 , RL 3 , RL 6 , and RL 7 . Thus, in the storage device 1 C, it is possible to simplify wiring between the row selection line driver 80 and the row selection lines RL 0 to RL 8 .

Modification Example 1-5

In the foregoing embodiment, as illustrated in FIGS. 1 and 2 , in each of the memory array units MAU, the row selection line driver 20 and the column selection line driver 30 drive the memory array MA in the memory array unit MAU, but this is not limitative. Alternatively, for example, the driver 20 A in the row selection line driver 20 may drive two memory arrays MA in memory array units MAU different from each other, or the driver 20 B may drive two memory arrays MA in memory array units MAU different from each other. Likewise, the driver 30 A in the column selection line driver 30 may drive two memory arrays MA in memory array units MAU different from each other, or the driver 30 B may drive two memory arrays MA in memory array units MAU different from each other. In the following, the present modification example is described with reference to an example.

FIG. 29 illustrates a configuration example of a storage device 1 D according to the present modification example. In this example, the driver 30 A drives the column selection lines CL 0 and CL 1 in two memory arrays MA (for example, an (n−1)th memory array MA(n−1) and an n-th memory array MA(n)). In addition, the driver 30 B drives the column selection lines CL 2 and CL 3 in two memory arrays MA (for example, the n-th memory array MA(n) and an (n+1)th memory array MA(n+1)). Accordingly, for example, in the (n−1)th memory array MA(n−1) and the n-th memory array MA(n), the same selection voltage is applied to the same column selection line CL out of the column selection lines CL 0 and CL 1 . Likewise, for example, in the n-th memory array MA(n) and the (n+1)th memory array MA(n+1), the same selection voltage is applied to the same column selection line CL out of the column selection lines CL 2 and CL 3 . In the storage device 1 D, this configuration makes it possible to reduce the number of the column selection line drivers 30 . It is to be noted that in this example, the present technology is applied to the drivers 30 A and 30 B in the column selection line driver 30 , but may be applied to the drivers 20 A and 20 B in the row selection line driver 20 in a similar manner.

Modification Example 1-6

In the foregoing embodiment, as illustrated in FIG. 6 , for example, the decoder 23 A in the row selection line driver 20 selectively applies the selection voltage to the row selection lines RL 0 to RL 3 through selectively turning on the transistors 206 , 209 , 210 , and 213 , and for example, the decoder 23 B selectively applies the selection voltage to the row selection lines RL 4 to RL 7 through selectively turning on the transistors 226 , 229 , 230 , and 233 , but this is not limitative. In the following, a storage device 1 E according to the present modification example is described in detail. As with the storage device 1 ( FIG. 1 ) according to the foregoing embodiment, the storage device 1 E includes a memory array unit MAU 5 .

FIG. 30 illustrates a configuration example of the memory array unit MAU 5 . The memory array unit MAU 5 includes a memory array MA 5 and an array driver ADS.

The memory array MA 5 includes a plurality of row selection lines RL (in this example, 16 row selection lines RL 0 to RL 15 ), a plurality of column selection lines CL (in this example, four column selection lines CL 0 to CL 3 ), and a plurality of memory cells MC (in this example, 64 memory cells MC 0 to MC 63 ). As with the memory array MA ( FIG. 3 ) according to the foregoing embodiment, the memory cells MC 0 to MC 31 are formed in the storage layer L 0 , and the memory cells MC 32 to MC 63 are formed in the storage layer L 1 .

The array driver ADS includes a row selection line driver 100 and the column selection line driver 30 . The row selection line driver 100 selectively applies a voltage to the row selection lines RL 0 to RL 15 on the basis of an instruction from the microcontroller MCON. As with the row selection line driver 20 ( FIG. 6 ) according to the foregoing embodiment, the row selection line driver 100 includes the voltage selection circuits 21 A and 21 B, the current limiting circuits 22 A and 22 B, decoders 103 A and 103 B, and the sense amplifiers 24 A and 24 B. In addition, although not illustrated, the row selection line driver 100 also includes an inverting circuit that respectively generates, on the basis of the logic signals Vgr 0 to Vgr 7 and Vgr 11 to Vgr 14 supplied from the microcontroller MCON, the logic signals Vgr 0 b to Vgr 7 b and Vgr 11 b to Vgr 14 b each of which is the inverted signal of a corresponding one of these logic signals.

FIG. 31A illustrates a configuration example of the decoder 103 A. The decoder 103 A selectively applies, to the row selection lines RL 0 to RL 7 , the selection voltage supplied from the voltage selection circuit 21 A via the current limiting circuit 22 A, on the basis of the logic signals Vgr 0 to Vgr 3 , Vgr 11 , and Vgr 12 supplied from the microcontroller MCON. The decoder 103 A includes transistors 401 to 420 . The transistors 401 to 420 are n-type MOS transistors. The transistor 401 has a gate supplied with the logic signal Vgr 11 , a source coupled to the node N 23 A, and a drain coupled to a node N 401 . The transistor 402 has a gate supplied with the logic signal Vgr 11 b that is the inverted signal of the logic signal Vgr 11 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to the node N 401 . The transistor 403 has a gate supplied with the logic signal Vgr 12 b that is the inverted signal of the logic signal Vgr 12 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to a node N 404 . The transistor 404 has a gate supplied with the logic signal Vgr 12 , a source coupled to the node N 23 A, and a drain coupled to the node N 404 .

The transistor 405 has a gate supplied with the logic signal Vgr 0 , a source coupled to the node N 401 , and a drain coupled to a drain of the transistor 406 and the row selection line RL 0 . The transistor 406 has a gate supplied with the logic signal Vgr 0 b that is the inverted signal of the logic signal Vgr 0 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 405 and the row selection line RL 0 . The transistor 407 has a gate supplied with the logic signal Vgr 1 b that is the inverted signal of the logic signal Vgr 1 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to a drain of the transistor 408 and the row selection line RL 1 . The transistor 408 has a gate supplied with the logic signal Vgr 1 , a source coupled to the node N 401 , and the drain coupled to the drain of the transistor 407 and the row selection line RL 1 . The transistor 409 has a gate supplied with the logic signal Vgr 2 , a source coupled to the node N 401 , and a drain coupled to a drain of the transistor 410 and the row selection line RL 2 . The transistor 410 has a gate supplied with the logic signal Vgr 2 b that is the inverted signal of the logic signal Vgr 2 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 409 and the row selection line RL 2 . The transistor 411 has a gate supplied with the logic signal Vgr 3 b that is the inverted signal of the logic signal Vgr 3 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to a drain of the transistor 412 and the row selection line RL 3 . The transistor 412 has a gate supplied with the logic signal Vgr 3 , a source coupled to the node N 401 , and the drain coupled to the drain of the transistor 411 and the row selection line RL 3 .

The transistor 413 has a gate supplied with the logic signal Vgr 0 , a source coupled to the node N 404 , and a drain coupled to a drain of the transistor 414 and the row selection line RL 4 . The transistor 414 has a gate supplied with the logic signal Vgr 0 b that is the inverted signal of the logic signal Vgr 0 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 413 and the row selection line RL 4 . The transistor 415 has a gate supplied with the logic signal Vgr 1 b that is the inverted signal of the logic signal Vgr 1 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to a drain of the transistor 416 and the row selection line RL 5 . The transistor 416 has a gate supplied with the logic signal Vgr 1 , a source coupled to the node N 404 , and the drain coupled to the drain of the transistor 415 and the row selection line RL 5 . The transistor 417 has a gate supplied with the logic signal Vgr 2 , a source coupled to the node N 404 , and a drain coupled to a drain of the transistor 418 and the row selection line RL 6 . The transistor 418 has a gate supplied with the logic signal Vgr 2 b that is the inverted signal of the logic signal Vgr 2 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 417 and the row selection line RL 6 . The transistor 419 has a gate supplied with the logic signal Vgr 3 b that is the inverted signal of the logic signal Vgr 3 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to a drain of the transistor 420 and the row selection line RL 7 . The transistor 420 has a gate supplied with the logic signal Vgr 3 , a source coupled to the node N 404 , and the drain coupled to the drain of the transistor 419 and the row selection line RL 7 .

FIG. 31B illustrates a configuration example of the decoder 103 B. The decoder 103 B selectively applies, to the row selection lines RL 8 to RL 15 , the selection voltage supplied from the voltage selection circuit 21 B via the current limiting circuit 22 B, on the basis of the logic signals Vgr 4 to Vgr 7 , Vgr 13 , and Vgr 14 supplied from the microcontroller MCON. The decoder 103 B has a configuration similar to that of the decoder 103 A. The decoder 103 B includes transistors 421 to 440 . The transistors 421 to 440 respectively correspond to the transistors 401 to 420 in the decoder 103 A.

FIG. 32 illustrates an operation example of the decoder 103 A in a case of applying, to the row selection line RL 0 , the selection voltage supplied to the node N 23 A (in this example, the selection voltage Vpset). In this case, in the decoder 103 A, the transistors 401 and 403 are turned on while the transistors 402 and 404 are turned off. Accordingly, the selection voltage Vpset is applied to the node N 401 , and the non-selection voltage Vinh is applied to the node N 404 .

In addition, the transistors 405 , 407 , 410 , and 411 are turned on while the transistors 406 , 408 , 409 , and 412 are turned off. This causes the decoder 103 A to apply, to the row selection line RL 0 , the selection voltage Vpset supplied to the node N 401 , and applies the non-selection voltage Vinh to the row selection lines RL 1 to RL 3 .

In addition, the transistors 413 , 415 , 418 , and 419 are turned on while the transistors 414 , 416 , 417 , and 420 are turned off. The same applies to the transistors 415 to 420 . This causes the decoder 103 B to apply the non-selection voltage Vinh to the row selection lines RL 4 to RL 7 .

In other words, for example, the gates of the transistors 405 and 413 are supplied with the same logic signal Vgr 0 , thus turning on the transistor 413 as with the transistor 405 , and for example, the gates of the transistors 406 and 414 are supplied with the same logic signal Vgr 0 b , thus turning off the transistor 414 as with the transistor 406 . The node N 401 is supplied with the selection voltage Vpset, thus causing the transistor 405 , which is on, to supply the selection voltage Vpset to the row selection line RL 0 . In other words, the selection voltage supplied to the node N 23 A is supplied to the row selection line RL 0 via the two transistors 401 and 405 . Meanwhile, the non-selection voltage Vinh is supplied to the node N 404 , thus causing the transistor 413 , which is on, to supply the non-selection voltage Vinh to the row selection line RL 4 .

In the storage device 1 E, this configuration makes it possible to reduce the number of wiring lines between the microcontroller MCON and the array driver ADS. In other words, for example, in a case of a configuration like a decoder 103 AR illustrated in FIG. 33 , eight logic signals Vgr 0 to Vgr 7 are supplied to the decoder 103 AR from the microcontroller MCON. In contrast, in the decoder 103 A ( FIG. 31A ) according to the present modification example, six logic signals Vgr 0 to Vgr 3 , Vgr 11 , and Vgr 12 are supplied to the decoder 103 A from the microcontroller MCON. The same applies to the decoder 103 B. As the number of the row selection lines RL is larger, the present modification example is more effective. As a result, in the storage device 1 E, it is possible to reduce the number of wiring lines between the microcontroller MCON and the array driver ADS. It is to be noted that in this example, the present technology is applied to the row selection line driver 20 , but may also be applied to the column selection line driver 30 .

Modification Example 1-7

In the foregoing embodiment, as illustrated in FIG. 6 , the row selection line driver 20 selectively applies the selection voltage to the row selection lines RL 0 to RL 7 on the basis of the logic signals Vgr 0 to Vgr 7 , but this is not limitative. Alternatively, for example, the row selection line driver may selectively apply the selection voltage to the row selection lines RL 0 to RL 7 on the basis of the logic signals Vgr 0 to Vgr 3 . In the following, a storage device IF according to the present modification example is described in detail.

As with the storage device 1 ( FIG. 1 ) according to the foregoing embodiment, the storage device 1 F includes a memory array unit MAU 6 . As with the memory array unit MAU ( FIG. 2 ) according to the foregoing embodiment, the memory array unit MAU 6 includes an array driver AD 6 that includes a row selection line driver 120 and the column selection line driver 30 .

FIG. 34 illustrates a configuration example of the row selection line driver 120 . The row selection line driver 120 includes a decoder 123 B. In addition, although not illustrated, the row selection line driver 120 also includes an inverting circuit that respectively generates, on the basis of the logic signals Vgrset, Vgrrst, Vgrsns, and Vgr 0 to Vgr 3 supplied from the microcontroller MCON, the logic signals Vgrsetb, Vgrrstb, Vgrsnsb, and Vgr 0 b to Vgr 3 b each of which is the inverted signal of a corresponding one of these logic signals.

As with the decoder 23 A, the decoder 123 B selectively applies, to the row selection lines RL 4 to RL 7 , the selection voltage supplied from the voltage selection circuit 21 B via the current limiting circuit 22 B, on the basis of the logic signals Vgr 0 to Vgr 3 supplied from the microcontroller MCON. In other words, in the example ( FIG. 6 ) in the foregoing embodiment, the decoder 23 B selectively applies the selection voltage to the row selection lines RL 4 to RL 7 on the basis of the logic signals Vgr 4 to Vgr 7 . In contrast, in the present modification example ( FIG. 34 ), the decoder 123 B selectively applies the selection voltage to the row selection lines RL 4 to RL 7 on the basis of the logic signals Vgr 0 to Vgr 3 . The transistor 226 has the gate supplied with the logic signal Vgr 0 , the source coupled to the node N 23 B, and the drain coupled to the drain of the transistor 227 and the row selection line RL 4 . The transistor 227 has the gate supplied with the logic signal Vgr 0 b that is the inverted signal of the logic signal Vgr 0 , the source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 226 and the row selection line RL 4 . The transistor 228 has the gate supplied with the logic signal Vgr 1 b that is the inverted signal of the logic signal Vgr 1 , the source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 229 and the row selection line RL 5 . The transistor 229 has the gate supplied with the logic signal Vgr 1 , the source coupled to the node N 23 B, and the drain coupled to the drain of the transistor 228 and the row selection line RL 5 . The transistor 230 has the gate supplied with the logic signal Vgr 2 , the source coupled to the node N 23 B, and the drain coupled to the drain of the transistor 231 and the row selection line RL 6 . The transistor 231 has the gate supplied with the logic signal Vgr 2 b that is the inverted signal of the logic signal Vgr 2 , the source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 230 and the row selection line RL 6 . The transistor 232 has the gate supplied with the logic signal Vgr 3 b that is the inverted signal of the logic signal Vgr 3 , the source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 233 and the row selection line RL 7 . The transistor 233 has the gate supplied with the logic signal Vgr 4 , the source coupled to the node N 23 B, and the drain coupled to the drain of the transistor 232 and the row selection line RL 7 .

The voltage selection circuit 21 A, the current limiting circuit 22 A, the decoder 23 A, and the sense amplifier 24 A are included in a driver 120 A, and the voltage selection circuit 21 B, the current limiting circuit 22 B, the decoder 123 B, and the sense amplifier 24 B are included in a driver 120 B.

FIG. 35 schematically illustrates an operation in a case of performing the set operation OP 1 on two memory cells MC 6 and MC 21 . FIG. 36 illustrates an operation of the row selection line driver 120 in the set operation OP 1 . The operation of the column selection line driver 30 is similar to that in FIG. 9B .

In this example, the row selection line driver 120 applies the selection voltage Vnset (in this example, 0 V) to the row selection line RL 1 , applies the selection voltage Vpset (in this example, 6 V) to the row selection line RL 5 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining row selection lines RL 0 , RL 2 to RL 4 , RL 6 , and RL 7 . In addition, the column selection line driver 30 applies the selection voltage Vnset (in this example, 0 V) to the column selection line CL 1 , applies the selection voltage Vpset (in this example, 6 V) to the column selection line CL 2 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining column selection lines CL 0 and CL 3 .

At this time, as illustrated in FIG. 36 , in the decoder 23 A in the row selection line driver 120 , the transistors 207 , 209 , 211 , and 212 are turned on while the transistors 206 , 208 , 210 , and 213 are turned off. As a result, the decoder 23 A applies, to the row selection line RL 1 , the selection voltage Vnset (in this example, 0 V) supplied from the voltage selection circuit 21 A via the current limiting circuit 22 A, and applies the non-selection voltage Vinh (in this example, 3 V) to the row selection lines RL 0 , RL 2 , and RL 3 .

In addition, in the decoder 123 B, the transistors 227 , 229 , 231 , and 232 are turned on while the transistors 226 , 228 , 230 , and 233 are turned off. In other words, for example, the gates of the transistors 209 and 229 are supplied with the same logic signal Vgr 1 , thus turning on the transistor 229 as with the transistor 209 , and for example, the gates of the transistors 208 and 228 are supplied with the same logic signal Vgr 1 b , thus turning off the transistor 228 as with the transistor 208 . As a result, the decoder 123 B applies, to the row selection line RL 5 , the selection voltage Vpset (in this example, 6 V) supplied from the voltage selection circuit 21 B via the current limiting circuit 22 B, and applies the non-selection voltage Vinh (in this example, 3 V) to the row selection lines RL 4 , RL 6 , and RL 7 .

In addition, as illustrated in FIG. 9B , the voltage selection circuit 31 A in the column selection line driver 30 outputs the selection voltage Vnset (in this example, 0 V), and the voltage selection circuit 31 B outputs the selection voltage Vpset (in this example, 6 V). Then, in the decoder 32 A, the transistors 308 and 310 are turned on while the transistors 307 and 309 are turned off. As a result, the decoder 32 A applies the selection voltage Vnset (in this example, 0 V) to the column selection line CL 1 , and applies the non-selection voltage Vinh (in this example, 3 V) to column selection line CL 0 . In addition, in the decoder 32 B, the transistors 327 and 329 are turned on while the transistors 328 and 330 are turned off. As a result, the decoder 32 B applies, to the column selection line CL 2 , the selection voltage Vpset (in this example, 6 V) supplied from the voltage selection circuit 31 B, and applies the non-selection voltage Vinh (in this example, 3 V) to the column selection line CL 3 .

As a result, in the memory array unit MAU 6 , as illustrated in FIG. 35 , the two memory cells MC 6 and MC 21 are selected as targets for the set operation OP 1 . In the memory array unit MAU 6 , this causes the set current Iset (the set current Iset 1 ) to flow through the voltage selection circuit 31 B, the decoder 32 B, the column selection line CL 2 , the memory cell MC 6 , the row selection line RL 1 , the decoder 23 A, the current limiting circuit 22 A, and the voltage selection circuit 21 A in this order, and causes the set current Iset (the set current Iset 2 ) to flow through the voltage selection circuit 21 B, the current limiting circuit 22 B, the decoder 123 B, the row selection line RL 5 , the memory cell MC 21 , the column selection line CL 1 , the decoder 32 A, and the voltage selection circuit 31 A in this order.

FIG. 37 schematically illustrates an operation in a case of performing the set operation OP 1 on one memory cell MC 6 . FIG. 38 illustrates an operation of the row selection line driver 120 in the set operation OP 1 . The operation of the column selection line driver 30 is similar to that in FIG. 18B .

In this example, the row selection line driver 120 applies the selection voltage Vnset (in this example, 0 V) to the row selection line RL 1 , applies the selection voltage Vpset (in this example, 6 V) to the row selection line RL 5 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining row selection lines RL 0 , RL 2 to RL 4 , RL 6 , and RL 7 . In addition, the column selection line driver 30 applies the selection voltage Vpset (in this example, 6 V) to the column selection line CL 2 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining column selection lines CL 0 , CL 1 , and CL 3 .

At this time, as illustrated in FIG. 38 , the decoder 23 A in the row selection line driver 120 applies, to the row selection line RL 1 , the selection voltage Vnset (in this example, 0 V) supplied from the voltage selection circuit 21 A via the current limiting circuit 22 A, and applies the non-selection voltage Vinh (in this example, 3 V) to the row selection lines RL 0 , RL 2 , and RL 3 . In addition, the decoder 123 B applies, to the row selection line RL 5 , the selection voltage Vpset (in this example, 6 V) supplied from the voltage selection circuit 21 B via the current limiting circuit 22 B, and applies the non-selection voltage Vinh (in this example, 3 V) to the row selection lines RL 4 , RL 6 , and RL 7 .

In addition, as illustrated in FIG. 18B , the voltage selection circuit 31 A in the column selection line driver 30 outputs the selection voltage Vnset (in this example, 0 V), and the voltage selection circuit 31 B outputs the selection voltage Vpset (in this example, 6 V). Then, in the decoder 32 A, the transistors 308 and 309 are turned on while the transistors 307 and 310 are turned off. As a result, the decoder 32 A applies the non-selection voltage Vinh (in this example, 3 V) to the two column selection line CL 0 and CL 1 . In addition, in the decoder 32 B, the transistors 327 and 329 are turned on while the transistors 328 and 330 are turned off. As a result, the decoder 32 B applies, to the column selection line CL 2 , the selection voltage Vpset (in this example, 6 V) supplied from the voltage selection circuit 31 B, and applies the non-selection voltage Vinh (in this example, 3 V) to the column selection line CL 3 .

As a result, in the memory array unit MAU 6 , as illustrated in FIG. 37 , one memory cell MC 6 is selected as a target for the set operation OP 1 . In the memory array unit MAU 6 , this causes the set current Iset (the set current Iset 1 ) to flow through the voltage selection circuit 31 B, the decoder 32 B, the column selection line CL 2 , the memory cell MC 6 , the row selection line RL 1 , the decoder 23 A, the current limiting circuit 22 A, and the voltage selection circuit 21 A in this order.

In the storage device 1 F, this configuration makes it possible to reduce the number of wiring lines between the microcontroller MCON and the array driver AD 6 . As the number of the row selection lines RL is larger, the present modification example is more effective. It is to be noted that in this example, the present technology is applied to the row selection line driver 20 , but may also be applied to the column selection line driver 30 .

In addition, the present technology may be applied to both the row selection line driver 20 and the column selection line driver 30 . In the following, a storage device 1 G according to the present modification example is described in detail.

As with the storage device 1 ( FIG. 1 ) according to the foregoing embodiment, the storage device 1 G includes a memory array unit MAU 1 . As with the memory array unit MAU ( FIG. 2 ) according to the foregoing embodiment, the memory array unit MAU 1 includes an array driver AD 7 that includes the row selection line driver 120 and a column selection line driver 130 .

FIG. 39 illustrates a configuration example of the column selection line driver 130 . The column selection line driver 130 includes voltage selection circuits 131 A and 131 B, and a decoder 132 B. In addition, although not illustrated, the column selection line driver 130 also includes an inverting circuit that respectively generates, on the basis of the logic signals Vgc 0 and Vgc 1 supplied from the microcontroller MCON, the logic signals Vgc 0 b and Vgc 1 b each of which is the inverted signal of a corresponding one of these logic signals.

The voltage selection circuit 131 A outputs one of the selection voltages Vpset, Vnset, Vprst, Vnrst, Vpsns, and Vnsns and the non-selection voltage Vinh on the basis of the logic signals Vgcset 0 b , Vgcset 1 , Vgcrst 0 , Vgcrst 1 b , Vgcsns 0 b , Vgcsns 1 , and Vgcinh 0 supplied from the microcontroller MCON. In other words, in the foregoing embodiment ( FIG. 7 ), the voltage selection circuit 31 A outputs one of the six selection voltages Vpset, Vnset, Vprst, Vnrst, Vpsns, and Vnsns on the basis of the six logic signals Vgcset 0 , Vgcset 1 , Vgcrst 0 , Vgcrst 1 , Vgcsns 0 , and Vgcsns 1 . In contrast, in the present modification example ( FIG. 39 ), the voltage selection circuit 131 A outputs one of the six selection voltages Vpset, Vnset, Vprst, Vnrst, Vpsns, and Vnsns and the non-selection voltage Vinh on the basis of the seven logic signals Vgcset 0 b , Vgcset 1 , Vgcrst 0 , Vgcrst 1 b , Vgcsns 0 b , Vgcsns 1 , and Vgcinh 0 . The voltage selection circuit 131 A includes a transistor 311 . The transistor 311 is an n-type MOS transistor. The transistor 311 has a gate supplied with the logic signal Vgcinh 0 , a source supplied with the non-selection voltage Vinh, and a drain coupled to the node N 32 A.

As with the voltage selection circuit 131 A, the voltage selection circuit 131 B outputs one of the selection voltages Vpset, Vnset, Vprst, Vnrst, Vpsns, and Vnsns and the non-selection voltage Vinh on the basis of the logic signals Vgcset 2 b , Vgcset 3 , Vgcrst 2 , Vgcrst 3 b , Vgcsns 2 b , Vgcsns 3 , and Vgcinh 1 supplied from the microcontroller MCON. The voltage selection circuit 131 B includes a transistor 331 . The transistor 331 is an n-type MOS transistor. The transistor 331 has a gate supplied with the logic signal Vgcinh 1 , a source supplied with the non-selection voltage Vinh, and a drain coupled to the node N 32 B. The transistor 321 has the gate supplied with the logic signal Vgcset 2 b that is the inverted signal of the logic signal Vgcset 2 , the source supplied with the selection voltage Vpset (for example, 6 V), and the drain coupled to the node N 32 B. The transistor 322 has the gate supplied with the logic signal Vgcset 3 , the source supplied with the selection voltage Vnset (for example, 0 V), and the drain coupled to the node N 32 B. The transistor 323 has the gate supplied with the logic signal Vgcrst 3 b that is the inverted signal of the logic signal Vgcrst 3 , the source supplied with the selection voltage Vprst (for example, 6 V), and the drain coupled to the node N 32 B. The transistor 324 has the gate supplied with the logic signal Vgcrst 2 , the source supplied with the selection voltage Vnrst (for example, 0 V), and the drain coupled to the node N 32 B. The transistor 325 has the gate supplied with logic signal Vgcsns 2 b that is the inverted signal of the logic signal Vgcsns 2 , the source supplied with the selection voltage Vpsns (for example, 5 V), and the drain coupled to the node N 32 B. The transistor 326 has the gate supplied with the logic signal Vgcsns 3 , the source supplied with the selection voltage Vnsns (for example, 1 V), and the drain coupled to the node N 32 B.

As with the decoder 32 A, the decoder 132 B applies, to one of the column selection lines CL 2 and CL 3 , the selection voltage supplied from the voltage selection circuit 31 B, on the basis of the logic signals Vgc 0 and Vgc 1 supplied from the microcontroller MCON. In other words, in the example ( FIG. 7 ) in the foregoing embodiment, the decoder 32 B selectively applies the selection voltage to the column selection lines CL 2 and CL 3 on the basis of the logic signals Vgc 2 and Vgc 3 . In contrast, in the present modification example ( FIG. 39 ), the decoder 132 B selectively applies the selection voltage to the column selection lines CL 2 and CL 3 on the basis of the logic signals Vgc 0 and Vgc 1 . The transistor 327 has the gate supplied with the logic signal Vgc 0 , the source coupled to the node N 32 B, and the drain coupled to the drain of the transistor 328 and the column selection lines CL 2 . The transistor 328 has the gate supplied with the logic signal Vgc 0 b that is the inverted signal of the logic signal Vgc 0 , the source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 327 and the column selection line CL 2 . The transistor 329 has the gate supplied with the logic signal Vgc 1 b that is the inverted signal of the logic signal Vgc 1 , the source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 330 and the column selection line CL 3 . The transistor 330 has the gate supplied with the logic signal Vgc 1 , the source coupled to the node N 32 B, and the drain coupled to the drain of the transistor 329 and the column selection line CL 3 .

The voltage selection circuit 131 A and the decoder 32 A are included in a driver 130 A, and the voltage selection circuit 131 B and the decoder 132 B are included in a driver 130 B.

FIG. 40 schematically illustrates an operation in a case of performing the set operation OP 1 on two memory cells MC 6 and MC 20 . FIG. 41 illustrates an operation of the column selection line driver 130 in the set operation OP 1 . The operation of the row selection line driver 120 is similar to that in FIG. 36 .

In this example, the row selection line driver 120 applies the selection voltage Vnset (in this example, 0 V) to the row selection line RL 1 , applies the selection voltage Vpset (in this example, 6 V) to the row selection line RL 5 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining row selection lines RL 0 , RL 2 to RL 4 , RL 6 , and RL 7 . In addition, the column selection line driver 130 applies the selection voltage Vnset (in this example, 0 V) to the column selection line CL 0 , applies the selection voltage Vpset (in this example, 6 V) to the column selection line CL 2 , and applies non-selection voltage Vinh (in this example, 3 V) to the remaining column selection lines CL 1 and CL 3 .

At this time, as illustrated in FIG. 41 , in the voltage selection circuit 131 A in the column selection line driver 130 , the transistor 302 is turned on while the transistors 301 , 303 to 306 , and 311 are turned off. This causes the voltage selection circuit 131 A to output the selection voltage Vnset (in this example, 0 V). Meanwhile, in the voltage selection circuit 131 B, the transistor 321 is turned on while the transistors 322 to 326 and 331 are turned off. This causes the voltage selection circuit 131 B to output the selection voltage Vpset (in this example, 6 V).

Then, in the decoder 32 A, the transistors 307 and 309 are turned on while the transistors 308 and 310 are turned off. As a result, the decoder 32 A applies, to the column selection line CL 1 , the selection voltage Vnset (in this example, 0 V) supplied from the voltage selection circuit 131 A, and applies the non-selection voltage Vinh (in this example, 3 V) to the column selection line CL 0 .

In addition, in the decoder 132 B, the transistors 327 and 329 are turned on while the transistors 328 and 330 are turned off. In other words, for example, the transistors 307 and 327 are supplied with the same logic signal Vgc 0 , thus turning on the transistor 327 as with the transistor 307 , and for example, the transistors 308 and 328 are supplied with the same logic signal Vgc 0 b , thus turning off the transistor 328 as with the transistor 308 . As a result, the decoder 132 B applies, to the column selection line CL 2 , the selection voltage Vpset (in this example, 6 V) supplied from the voltage selection circuit 131 B, and applies the non-selection voltage Vinh (in this example, 3 V) to the column selection line CL 3 .

As a result, in the memory array unit MAU 7 , as illustrated in FIG. 40 , the two memory cells MC 6 and MC 20 are selected as targets for the set operation OP 1 . In the memory array unit MAU 7 , this causes the set current Iset (the set current Iset 1 ) to flow through the voltage selection circuit 131 B, the decoder 132 B, the column selection line CL 2 , the memory cell MC 6 , the row selection line RL 1 , the decoder 23 A, the current limiting circuit 22 A, and the voltage selection circuit 21 A in this order, and causes the set current Iset (the set current Iset 2 ) to flow through the voltage selection circuit 21 B, the current limiting circuit 22 B, the decoder 123 B, the row selection line RL 5 , the memory cell MC 20 , the column selection line CL 0 , the decoder 32 A, and the voltage selection circuit 131 A in this order.

FIG. 42 schematically illustrates an operation in a case of performing the set operation OP 1 on one memory cell MC 6 . FIG. 43 illustrates an operation of the column selection line driver 130 in the set operation OP 1 . The operation of the row selection line driver 120 is similar to that in FIG. 38 .

In this example, the row selection line driver 120 applies the selection voltage Vnset (in this example, 0 V) to the row selection line RL 1 , applies the selection voltage Vpset (in this example, 6 V) to the row selection line RL 5 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining row selection lines RL 0 , RL 2 to RL 4 , RL 6 , and RL 7 . In addition, the column selection line driver 130 applies the selection voltage Vpset (in this example, 6 V) to the column selection line CL 2 , and applies the non-selection voltage Vinh (in this example, 3 V) to the remaining column selection lines CL 0 , CL 1 , and CL 3 .

At this time, as illustrated in FIG. 43 , in the voltage selection circuit 131 A in the column selection line driver 130 , the transistor 311 is turned on while the transistors 301 to 306 are turned off. This causes the voltage selection circuit 131 A to output the non-selection voltage Vinh (in this example, 3 V). Meanwhile, in the voltage selection circuit 131 B, the transistor 321 is turned on while the transistors 322 to 326 and 331 are turned off. This causes the voltage selection circuit 131 B to output the selection voltage Vpset (in this example, 6 V).

Then, in the decoder 32 A, the transistors 307 and 309 are turned on while the transistors 308 and 310 are turned off. As a result, the decoder 32 A applies the non-selection voltage Vinh (in this example, 3 V) to the column selection lines CL 0 and CL 1 .

In addition, in the decoder 132 B, the transistors 327 and 329 are turned on while the transistors 328 and 330 are turned off. As a result, the decoder 132 B applies to the column selection line CL 2 , the selection voltage Vpset (in this example, 6 V) supplied from the voltage selection circuit 131 B, and applies the non-selection voltage Vinh (in this example, 3 V) to the column selection line CL 3 .

As a result, in the memory array unit MAU 7 , as illustrated in FIG. 42 , the one memory cell MC 6 is selected as a target for the set operation OP 1 . In the memory array unit MAU 7 , this causes the set current Iset (the set current Iset 1 ) to flow through the voltage selection circuit 31 B, the decoder 132 B, the column selection line CL 2 , the memory cell MC 6 , the row selection line RL 1 , the decoder 23 A, the current limiting circuit 22 A, and the voltage selection circuit 21 A in this order.

In the storage device 1 G, this configuration makes it possible to reduce the number of wiring lines between the microcontroller MCON and the array driver AD 7 . As the numbers of the row selection lines RL and the column selection lines CL are larger, the present modification example is more effective.

Other Modification Example

In addition, two or more of these modification examples may be combined.

2. Second Embodiment

Next, a storage device 2 according to a second embodiment is described. The present embodiment is different from the foregoing first embodiment in the number of storage layers in the memory array. It is to be noted that substantially the same components as those in the storage device 1 according to the foregoing first embodiment are denoted by the same reference numerals, and the descriptions thereof are omitted where appropriate. As illustrated in FIG. 1 , the storage device 2 includes a memory array unit MAU 10 .

FIG. 44 illustrates a configuration example of the memory array unit MAU 10 . The memory array unit MAU 10 includes a memory array MA 10 and an array driver AD 10 .

The memory array MA 10 includes eight row selection lines RL 0 to RL 7 , four row selection lines RL 10 to RL 13 , eight column selection lines CL 0 to CL 7 , and 64 memory cells MC 0 to MC 63 . Each of the row selection lines RL 0 to RL 7 and the column selection lines CL 0 to CL 4 has one end coupled to the array driver AD 10 . Each of the row selection lines RL 0 to RL 3 has another end coupled to one end of each of the row selection lines RL 10 to RL 13 .

FIG. 45 illustrates a configuration example of the memory array MA 10 . The row selection lines RL 0 to RL 7 and RL 10 to RL 13 are formed to extend in the x-direction in the x-y plane. In addition, the column selection lines CL 0 to CL 7 are formed to extend in the y-direction in the x-y plane. The row selection lines RL 0 to RL 3 are formed in the same layer, the column selection lines CL 0 to CL 3 are formed in a layer above the layer in which the row selection lines RL 0 to RL 3 are formed, the row selection lines RL 4 to RL 7 are formed in a layer above the layer in which the column selection lines CL 0 to CL 3 are formed, the column selection lines CL 4 to CL 7 are formed in a layer above the layer in which the row selection lines RL 4 to RL 7 are formed, and the row selection lines RL 10 to RL 13 are formed in a layer above the layer in which the column selection lines CL 4 to CL 7 are formed. Thus, in the memory array MA 10 , a layer in which the row selection lines RL are formed and a layer in which the column selection lines CL are formed are alternately disposed.

In the storage layer L 0 between the layer in which the four row selection lines RL 0 to RL 3 are formed and the layer in which the four column selection lines CL 0 to CL 3 are formed, 16 (=4×4) memory cells MC (MC 0 to MC 15 ) are formed. Likewise, 16 (=4×4) memory cells MC (MC 16 to MC 31 ) are formed in the storage layer L 1 between the layer in which the four column selection lines CL 0 to CL 3 are formed and the layer in which the four row selection lines RL 4 to RL 7 are formed, 16 (=4×4) memory cells MC (MC 32 to MC 47 ) are formed in the storage layer L 2 between the layer in which the four row selection lines RL 4 to RL 7 are formed and the layer in which the four column selection lines CL 4 to CL 7 are formed, and 16 (=4×4) memory cells MC (MC 48 to MC 63 ) are formed in a storage layer L 3 between the layer in which the four column selection lines CL 4 to CL 7 are formed and the layer in which the four row selection lines RL 10 to RL 13 are formed.

In the memory cell MC (memory cells MC 0 to MC 15 ) formed in the storage layer L 0 , the terminal TU is coupled to one of the column selection lines CL 0 to CL 3 , and the terminal TL is coupled to one of the row selection lines RL 0 to RL 3 . Likewise, in the memory cell MC (memory cells MC 16 to MC 31 ) formed in the storage layer L 1 , the terminal TU is coupled to one of the row selection lines RL 4 to RL 7 , and the terminal TL is coupled to one of the column selection lines CL 0 to CL 3 . In addition, in the memory cell MC (memory cells MC 32 to MC 47 ) formed in the storage layer L 2 , the terminal TU is coupled to one of the column selection lines CL 4 to CL 7 , and the terminal TL is coupled to one of the row selection lines RL 4 to RL 7 . In addition, in the memory cell MC (memory cells MC 48 to MC 63 ) formed in the storage layer L 3 , the terminal TU is coupled to one of the row selection lines RL 10 to RL 13 , and the terminal TL is coupled to one of the column selection lines CL 4 to CL 7 . In other words, in the memory cell MC, irrespective of which one of the storage layers L 0 to L 3 the memory cell MC is formed in, the storage element VR is formed above the selection element SE.

The array driver AD 10 ( FIG. 44 ) writes data to the memory cell MC or reads data from the memory cell MC through selectively applying a voltage to the row selection lines RL 0 to RL 7 and the column selection lines CL 0 to CL 7 on the basis of an instruction from the microcontroller MCON. The array driver AD 10 includes a row selection line driver 140 and a column selection line driver 150 .

FIG. 46 illustrates a configuration example of the row selection line driver 140 . The row selection line driver 140 includes the voltage selection circuits 81 A and 81 B, the current limiting circuits 22 A and 22 B, the decoders 23 A and 23 B, and the sense amplifiers 24 A and 24 B. In addition, although not illustrated, the row selection line driver 20 also includes an inverting circuit that respectively generates, on the basis of the logic signals Vgrset 0 , Vgrset 1 , Vgrrst 0 , Vgrrst 1 , Vgrsns 0 , Vgrsns 1 , and Vgr 0 to Vgr 7 supplied from the microcontroller MCON, the logic signals Vgrset 0 b , Vgrset 1 b , Vgrrst 0 b , Vgrrst 1 b , Vgrsns 0 b , Vgrsns 1 b , and Vgr 0 b to Vgr 7 b each of which is the inverted signal of a corresponding one of these logic signals. The voltage selection circuit 81 A, the current limiting circuit 22 A, the decoder 23 A, and the sense amplifier 24 A are included in a driver 140 A, and the voltage selection circuit 81 B, the current limiting circuit 22 B, the decoder 23 B, and the sense amplifier 24 B are included in a driver 140 B.

FIG. 47 illustrates a configuration example of the column selection line driver 150 . The column selection line driver 150 includes the voltage selection circuits 31 A and 31 B and decoders 152 A and 152 B. In addition, although not illustrated, the column selection line driver 150 also includes an inverting circuit that respectively generates, on the basis of the logic signals Vgcset 0 , Vgcset 1 , Vgcrst 0 , Vgcrst 1 , Vgcsns 0 , Vgcsns 1 , and Vgc 0 to Vgc 7 supplied from the microcontroller MCON, the logic signals Vgcset 0 b , Vgcset 1 b , Vgcrst 0 b , Vgcrst 1 b , Vgcsns 0 b , Vgcsns 1 b , and Vgc 0 b to Vgc 7 b each of which is the inverted signal of a corresponding one of these logic signals. The voltage selection circuit 31 A and the decoder 152 A are included in a driver 150 A, and the voltage selection circuit 31 B and the decoder 152 B are included in a driver 150 B.

The decoder 152 A selectively applies, to the column selection lines CL 0 to CL 3 , the selection voltage supplied from the voltage selection circuit 31 A, on the basis of the logic signals Vgc 0 to Vgc 3 supplied from the microcontroller MCON. The decoder 152 A includes transistors 371 to 378 . The transistors 371 to 378 are n-type MOS transistors. The transistor 371 has a gate supplied with the logic signal Vgc 0 , a source coupled to the node N 32 A, and a drain coupled to a drain of the transistor 372 and the column selection line CL 0 . The transistor 372 has a gate supplied with the logic signal Vgc 0 b that is the inverted signal of the logic signal Vgc 0 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 371 and the column selection line CL 0 . The transistor 373 has a gate supplied with the logic signal Vgc 1 b that is the inverted signal of the logic signal Vgc 1 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to a drain of the transistor 374 and the column selection line CL 1 . The transistor 374 has a gate supplied with the logic signal Vgc 1 , a source coupled to the node N 32 A, and the drain coupled to the drain of the transistor 373 and the column selection line CL 1 . The transistor 375 has a gate supplied with the logic signal Vgc 2 , a source coupled to the node N 32 A, and a drain coupled to a drain of the transistor 376 and the column selection line CL 2 . The transistor 376 has a gate supplied with the logic signal Vgc 2 b that is the inverted signal of the logic signal Vgc 2 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 375 and the column selection line CL 2 . The transistor 377 has a gate supplied with the logic signal Vgc 3 b that is the inverted signal of the logic signal Vgc 3 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to a drain of the transistor 378 and the column selection line CL 3 . The transistor 378 has a gate supplied with the logic signal Vgc 3 , a source coupled to the node N 32 A, and the drain coupled to the drain of the transistor 377 and the column selection line CL 3 .

As with the decoder 152 A, the decoder 152 B selectively applies, to the column selection lines CL 4 to CL 7 , the selection voltage supplied from the voltage selection circuit 31 B on the basis of the logic signals Vgc 4 to Vgc 7 supplied from the microcontroller MCON. The decoder 152 B includes transistors 391 to 398 . The transistors 391 to 398 are n-type MOS transistors. The transistor 391 has a gate supplied with the logic signal Vgc 4 , a source coupled to the node N 32 B, and a drain coupled to a drain of the transistor 392 and the column selection line CL 4 . The transistor 392 has a gate supplied with the logic signal Vgc 4 b that is the inverted signal of the logic signal Vgc 4 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 391 and the column selection line CL 4 . The transistor 393 has a gate supplied with the logic signal Vgc 5 b that is the inverted signal of the logic signal Vgc 5 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to a drain of the transistor 394 and the column selection line CL 5 . The transistor 394 has a gate supplied with the logic signal Vgc 5 , a source coupled to the node N 32 B, and the drain coupled to the drain of the transistor 393 and the column selection line CL 5 . The transistor 395 has a gate supplied with the logic signal Vgc 6 , a source coupled to the node N 32 B, and a drain coupled to a drain of the transistor 396 and the column selection line CL 6 . The transistor 396 has a gate supplied with the logic signal Vgc 6 b that is the inverted signal of the logic signal Vgc 6 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 395 and the column selection line CL 6 . The transistor 397 has a gate supplied with the logic signal Vgc 7 b that is the inverted signal of the logic signal Vgc 7 , a source supplied with the non-selection voltage Vinh (for example, 3 V), and a drain coupled to a drain of the transistor 398 and the column selection line CL 7 . The transistor 398 has a gate supplied with the logic signal Vgc 7 , a source coupled to the node N 32 B, and the drain coupled to the drain of the transistor 397 and the column selection line CL 7 .

As described above, in the storage device 2 , the number of the storage layers L 0 to L 3 is increased, which makes it possible to increase storage capacity and to reduce in cost per bit.

As described above, in the present embodiment, it is possible to increase storage capacity and to reduce cost per bit. Other effects are similar to those in the foregoing first embodiment.

Modification Example 2-1

In the foregoing embodiment, as illustrated in FIGS. 45 to 47 , the decoder 23 A in the row selection line driver 140 drives the row selection lines RL 0 to RL 3 formed in the same layer, and the decoder 23 B drives the row selection lines RL 4 to RL 7 formed in the same layer. In addition, the decoder 152 A in the column selection line driver 150 drives the column selection lines CL 0 to CL 3 formed in the same layer, and the decoder 152 B drives the column selection lines CL 4 to CL 7 formed in the same layer. However, this is not limitative. In the following, a storage device 2 A according to the present modification example is described in detail.

As with the storage device 2 according to the foregoing embodiment, the storage device 2 A includes a memory array unit MAU 11 . As with the memory array unit MAU 10 ( FIG. 44 ), the memory array unit MAU 11 includes an array driver AD 11 that includes a row selection line driver 160 and a column selection line driver 170 .

FIG. 48 illustrates a configuration example of the row selection line driver 160 . The row selection line driver 160 includes the decoders 83 A and 83 B.

The decoder 83 A selectively applies, to the row selection lines RL 0 , RL 1 , RL 4 , and RL 5 , the selection voltage supplied from the voltage selection circuit 21 A via the current limiting circuit 22 A, on the basis of the logic signals Vgr 0 , Vgr 1 , Vgr 4 , and Vgr 5 supplied from the microcontroller MCON. In other words, in the example ( FIG. 46 ) in the foregoing embodiment, the decoder 23 A selectively applies the selection voltage to the row selection lines RL 0 to RL 3 on the basis of the logic signals Vgr 0 to Vgr 3 . In contrast, in the present modification example ( FIG. 48 ), the decoder 83 A selectively applies the selection voltage to the row selection lines RL 0 , RL 1 , RL 4 , and RL 5 on the basis of the logic signals Vgr 0 , Vgr 1 , Vgr 4 , and Vgr 5 .

As with the decoder 83 A, the decoder 83 B selectively applies, to the row selection lines RL 2 , RL 3 , RL 6 , and RL 7 , the selection voltage supplied from the voltage selection circuit 21 B via the current limiting circuit 22 B, on the basis of the logic signals Vgr 2 , Vgr 3 , Vgr 6 , and Vgr 7 supplied from the microcontroller MCON.

FIG. 49 illustrates a configuration example of the column selection line driver 170 . The column selection line driver 170 includes decoders 172 A and 172 B.

The decoder 172 A selectively applies, to the column selection lines CL 0 , CL 1 , CL 4 , and CL 5 , the selection voltage supplied from the voltage selection circuit 31 A, on the basis of the logic signals Vgc 0 , Vgc 1 , Vgc 4 , and Vgc 5 supplied from the microcontroller MCON. In other words, in the example ( FIG. 47 ) in the foregoing embodiment, the decoder 152 A selectively applies the selection voltage to the column selection lines CL 0 to CL 3 on the basis of the logic signals Vgc 0 to Vgc 3 . In contrast, in the present modification example ( FIG. 49 ), the decoder 172 A selectively applies the selection voltage to the column selection lines CL 0 , CL 1 , CL 4 , and CL 5 on the basis of the logic signals Vgc 0 , Vgc 1 , Vgc 4 , and Vgc 5 . In the decoder 172 A, the transistor 375 has the gate supplied with the logic signal Vgc 4 , the source coupled to the node N 32 A, and the drain coupled to the drain of the transistor 376 and the column selection line CL 4 . The transistor 376 has the gate supplied with the logic signal Vgc 4 b that is the inverted signal of the logic signal Vgc 4 , the source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 375 and the column selection line CL 4 . The transistor 377 has the gate supplied with the logic signal Vgc 5 b that is the inverted signal of the logic signal Vgc 5 , the source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 378 and the column selection line CL 5 . The transistor 378 has the gate supplied with the logic signal Vgc 5 , the source coupled to the node N 32 A, and the drain coupled to the drain of the transistor 377 and the column selection line CL 5 .

As with the decoder 172 A, the decoder 172 B selectively applies, to the column selection lines CL 2 , CL 3 , CL 6 , and CL 7 , the selection voltage supplied from the voltage selection circuit 31 B, on the basis of the logic signals Vgc 2 , Vgc 3 , Vgc 6 , and Vgc 7 supplied from the microcontroller MCON. The transistor 391 has the gate supplied with the logic signal Vgc 2 , the source coupled to the node N 32 B, and the drain coupled to the drain of the transistor 392 and the column selection line CL 2 . The transistor 392 has the gate supplied with the logic signal Vgc 2 b that is the inverted signal of the logic signal Vgc 2 , the source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 391 and the column selection line CL 2 . The transistor 393 has the gate supplied with the logic signal Vgc 3 b that is the inverted signal of the logic signal Vgc 3 , the source supplied with the non-selection voltage Vinh (for example, 3 V), and the drain coupled to the drain of the transistor 394 and the column selection line CL 3 . The transistor 394 has the gate supplied with the logic signal Vgc 3 , the source coupled to the node N 32 B, and the drain coupled to the drain of the transistor 393 and the column selection line CL 3 .

In the row selection line driver 160 ( FIG. 48 ), the voltage selection circuit 81 A, the current limiting circuit 22 A, the decoder 83 A, and the sense amplifier 24 A are included in a driver 160 A, and the voltage selection circuit 81 B, the current limiting circuit 22 B, the decoder 83 B, and the sense amplifier 24 B are included in a driver 160 B. In addition, in the column selection line driver 170 ( FIG. 49 ), the voltage selection circuit 31 A and the decoder 172 A are included in a driver 170 A, and the voltage selection circuit 31 B and the decoder 172 B are included in a driver 170 B. As with the storage device 1 C ( FIG. 28 ), each of the drivers 160 A and 160 B and the drivers 170 A and 170 B is disposed in an appropriate region in the substrate surface. In the storage device 2 A, this makes it possible to simplify wiring between the array driver AD 11 and each of the row selection lines RL 0 to RL 8 and the column selection lines CL 0 to CL 7 .

Modification Example 2-2

In the foregoing embodiment, the four storage layers L 0 to L 4 are formed, but this is not limitative. Five or more storage layers may be formed.

Modification Example 2-3

Each of the modification examples of the foregoing first embodiment may be applied to the storage device 2 according to the foregoing embodiment.

Although the present technology has been described above referring to some embodiments and modification examples, the technology is not limited to these embodiments, etc., and may be modified in a variety of ways.

For example, in the foregoing embodiments, the selection voltage Vpset is set to the same voltage as the selection voltage Vprst, and the selection voltage Vnset is set to the same voltage as the selection voltage Vnrst, but this is not limitative. Alternatively, the selection voltage Vpset may be set to a voltage different from the selection voltage Vprst, and the selection voltage Vnset may be set to a voltage different from the selection voltage Vnrst.

In addition, for example, in the foregoing embodiments, the storage element VR possibly takes two identifiable resistance states RS (the high resistance state HRS and the low resistance state LRS), but this is not limitative. Alternatively, for example, the storage element VR may possibly take three or more identifiable resistance states RS.

In addition, for example, in the foregoing embodiments, the storage element VR is configured using a stack of the ion source layer and the resistance change layer, but this is not limitative. Alternatively, for example, a phase-change storage element may be used, or a resistive random access element such as a transition metal oxide may be used. In addition, for example, a spin-transfer torque (STT; Spin Transfer Torque) magnetic tunnel junction (MTJ; Magnetic Tunnel Junction) element may be used.

It is to be noted that effects described herein are merely illustrative and are not limitative, and may have other effects.

It is to be noted that the present technology may have the following configurations.

(1)

A storage device, including:

a first storage section that includes a plurality of first wiring lines, a plurality of second wiring lines, and a plurality of first memory cells, the plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines, the plurality of second wiring lines extending in a second direction that intersects with the first direction and including a plurality of third selection lines and a plurality of fourth selection lines, and the plurality of first memory cells each being inserted between a corresponding one of the plurality of first wiring lines and a corresponding one of the plurality of second wiring lines;

a first selection line driver that applies a first voltage to one or more selection lines of the plurality of first selection lines and applies a second voltage to one or more selection lines of the plurality of second selection lines, the first voltage being one of a first selection voltage and a second selection voltage, and the second voltage being one of the first selection voltage and the second selection voltage and being different from the first voltage; and

a second selection line driver that applies a third voltage to one or more selection lines of the plurality of third selection lines and applies a fourth voltage to one or more selection lines of the plurality of fourth selection lines, the third voltage being one of the first selection voltage and the second selection voltage, and the fourth voltage being one of the first selection voltage and the second selection voltage and being different from the third voltage.

(2)

The storage device according to (1), in which

the first selection line driver includes

a first driver that applies the first voltage to the one or more selection lines of the plurality of first selection lines, and

a second driver that applies the second voltage to the one or more selection lines of the plurality of second selection lines, and

the second selection line driver includes

a third driver that applies the third voltage to the one or more selection lines of the plurality of third selection lines, and

a fourth driver that applies the fourth voltage to the one or more selection lines of the plurality of fourth selection lines.

(3)

The storage device according to (2), in which

the first driver includes a first voltage application section that includes a plurality of first switches provided corresponding to the plurality of first selection lines, and applies the first voltage to the one or more selection lines of the plurality of first selection lines through selectively turning on the plurality of first switches on the basis of a first selection signal, and

the second driver includes a second voltage application section that includes a plurality of second switches provided corresponding to the plurality of second selection lines, and applies the second voltage to the one or more selection lines of the plurality of second selection lines through selectively turning on the plurality of second switches on the basis of a second selection signal.

(4)

The storage device according to (3), in which the second selection signal is a signal other than the first selection signal.

(5)

The storage device according to (3), in which

the first selection signal includes a plurality of signals including a first signal, and

the second selection signal includes a plurality of signals including the first signal.

(6)

The storage device according to any one of (3) to (5), in which

the first driver further includes a first supply section that supplies the first voltage to the first voltage application section, and

the second driver further includes a second supply section that supplies the second voltage to the second voltage application section.

(7)

The storage device according to (6), in which the first supply section selects and outputs, as the first voltage, one of the first selection voltage and the second selection voltage on the basis of a voltage selection signal.

(8)

The storage device according to (6), in which the first supply section outputs, as the first voltage, a fixed one of the first selection voltage and the second selection voltage.

(9)

The storage device according to any one of (3) to (8), in which

the third driver includes a third voltage application section that includes a plurality of third switches provided corresponding to the plurality of third selection lines, and applies the third voltage to the one or more selection lines of the plurality of third selection lines through selectively turning on the plurality of third switches on the basis of a third selection signal, and

the fourth driver includes a fourth voltage application section that includes a plurality of fourth switches provided corresponding to the plurality of fourth selection lines, and applies the fourth voltage to the one or more selection lines of the plurality of fourth selection lines through selectively turning on the plurality of fourth switches on the basis of a fourth selection signal.

(10)

The storage device according to (9), in which the fourth selection signal is a signal other than the third selection signal.

(11)

The storage device according to (9), in which

the third selection signal includes a plurality of signals including a second signal, and

the fourth selection signal includes a plurality of signals including the second signal.

(12)

The storage device according to any one of (9) to (11), in which

the third driver further includes a third supply section that supplies the third voltage to the third voltage application section, and

the fourth driver further includes a fourth supply section that supplies the fourth voltage to the fourth voltage application section.

(13)

The storage device according to any one of (9) to (11), in which

the first driver further includes a first voltage supply section that supplies the first voltage to the first voltage application section and the second selection line driver,

the second driver further includes a second voltage supply section that supplies the second voltage to the second voltage application section and the second selection line driver, and

the second selection line driver further includes a fifth supply section that selectively supplies the first voltage supplied from the first voltage supply section and the second voltage supplied from the second voltage supply section as the third voltage and the fourth voltage to the third voltage application section and the fourth voltage application section on the basis of a fifth selection signal.

(14)

The storage device according to any one of (2) to (13), further including a second storage section including a plurality of third wiring lines, a plurality of fourth wiring lines, and a plurality of second memory cells, the plurality of third wiring lines extending in the first direction and including a plurality of fifth selection lines and a plurality of sixth selection lines, the plurality of fourth wiring lines extending in the second direction and including a plurality of seventh selection lines and a plurality of eighth selection lines, and the plurality of second memory cells each being inserted between a corresponding one of the plurality of third wiring lines and a corresponding one of the plurality of fourth wiring lines, in which

each of the plurality of eighth selection lines is coupled to a corresponding one of the plurality of fourth selection lines.

(15)

The storage device according to any one of (2) to (14), in which

the first driver applies a non-selection voltage to a selection line other than the one or more selection lines of the plurality of first selection lines,

the second driver applies the non-selection voltage to a selection line other than the one or more selection lines of the plurality of second selection lines,

the third driver applies the non-selection voltage to a selection line other than the one or more selection lines of the plurality of third selection lines and,

the fourth driver applies the non-selection voltage to a selection line other than the one or more selection lines of the plurality of fourth selection lines.

(16)

The storage device according to (15), in which the non-selection voltage is a voltage between the first selection voltage and the second selection voltage.

(17)

The storage device according to any one of (2) to (14), in which

the first driver sets a selection line other than the one or more selection lines of the plurality of first selection lines to a floating state,

the second driver sets a selection line other than the one or more selection lines of the plurality of second selection lines to the floating state,

the third driver sets a selection line other than the one or more selection lines of the plurality of third selection lines to the floating state, and

the fourth driver sets a selection line other than the one or more selection lines of the plurality of fourth selection lines to the floating state.

(18)

The storage device according to any one of (1) to (6), in which

the plurality of first wiring lines is formed in a plurality of first wiring layers,

the plurality of second wiring lines is formed in one or a plurality of second wiring layers,

the plurality of first wiring layers and the one or the plurality of second wiring layers are alternately stacked,

in the plurality of first wiring layers, the plurality of first selection lines and the plurality of second selection lines are formed in wiring layers different from each other, and

the plurality of first memory cells is formed to have same orientation in a stacking direction.

(19)

The storage device according to any one of (1) to (6), in which

the plurality of first wiring lines is formed in a plurality of first layer wiring lines,

the plurality of second wiring lines is formed in one or a plurality of second layer wiring lines,

the plurality of first wiring layers and the one or the plurality of second wiring layers are alternately formed,

in the plurality of first wiring layers, the plurality of first selection lines and the plurality of second selection lines are formed in the same wiring layer, and

the plurality of first memory cells is provided to have same orientation in a stacking direction.

(20)

The storage device according to any one of (1) to (19), in which each of the plurality of first memory cells includes a storage element that possibly takes a plurality of identifiable resistance states including a first resistance state and a second resistance state.

(21)

The storage device according to (20), in which

each of the plurality of first memory cells has a first terminal and a second terminal,

in a case where the first selection voltage is applied to the first terminal and the second selection voltage is applied to the second terminal, a resistance state of the storage element is set to the first resistance state, and

in a case where the second selection voltage is applied to the first terminal and the first selection voltage is applied to the second terminal, the resistance state of the storage element is set to the second resistance state.

(22)

A control method, including:

with respect to a first storage section that includes a plurality of first wiring lines, a plurality of second wiring lines, and a plurality of first memory cells, the plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines, the plurality of second wiring lines extending in a second direction that intersects with the first direction and including a plurality of third selection lines and a plurality of fourth selection lines, and the plurality of first memory cells each being inserted between a corresponding one of the plurality of first wiring lines and a corresponding one of the plurality of second wiring lines,

applying a first voltage to one or more selection lines of the plurality of first selection lines while applying a second voltage to one or more selection lines of the plurality of second selection lines, the first voltage being one of a first selection voltage and a second selection voltage, and the second voltage being one of the first selection voltage and the selection voltage and being different from the first voltage; and

applying a third voltage to one or more selection lines of the plurality of third selection lines while applying a fourth voltage to one or more selection lines of the plurality of fourth selection lines, the third voltage being one of the first selection voltage and the second selection voltage, and the fourth voltage being one of the first selection voltage and the second selection voltage and being different from the third voltage.

This application claims the benefit of Japanese Priority Patent Application JP2016-251416 filed with the Japan Patent Office on Dec. 26, 2016, the entire contents of which are incorporated herein by reference.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations, and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.