Multi-phase converter and associated control circuit and control method for undershoot improvement

This application claims the benefit of CN application No. 201810679831.4, filed on Jun. 27, 2018, and incorporated herein by reference.

The present invention relates to electrical circuit, more particularly but not exclusively relates to multi-phase converter.

A multi-phase converter comprises a plurality of switching circuits coupled in parallel with each other to satisfy a demand of high load current. In order to optimize the efficiency of the multi-phase converter, auto phase shedding is usually required. In phase shedding mode, a number of switching circuits under power operation is determined by a magnitude of the load current. When the load current is small, only part of the switching circuits are under power operation and transfer power to a load. Once the load reduces, the number of the switching circuits under power operation will reduce. However, due to delay of control, a large undershoot will happen on an output voltage of the multi-phase converter.

It is one of the objects of the present invention to provide multi-phase converter and associated control circuit and control method.

One embodiment of the present invention discloses a multi-phase converter, configured to receive an input voltage, and configured to provide an output voltage and a load current to a load, the multi-phase converter comprising: a plurality of switching circuits coupled in parallel between the input voltage and the load, wherein a number of the plurality of switching circuits under power operation is determined based on the load current; and a control circuit, configured to provide a set signal to successively turn ON the specific plurality of switching circuits under power operation based on the output voltage, a reference signal and a nonlinear control signal; wherein when the number of the plurality of switching circuits under power operation decreases, the nonlinear control signal increases to a preset value from an initial value, and then the nonlinear control signal decreases to the initial value with a preset slew rate.

Another embodiment of the present invention discloses a control method for a multi-phase converter, wherein the multi-phase converter is configured to receive an input voltage, and configured to provide an output voltage and a load current to a load, and wherein the multi-phase converter comprises a plurality of switching circuits coupled in parallel between the input voltage and the load, the control method comprising: determining what specific number of the plurality of switching circuits under power operation based on the load current; providing a nonlinear control signal based on the number of the plurality of switching circuits under power operation, the nonlinear control signal having an initial value; and providing a set signal to successively turn ON the plurality of switching circuits under power operation based on the output voltage, a reference signal and the nonlinear control signal; wherein when the number of the plurality of switching circuits under power operation decreases, the nonlinear control signal equals a preset value, and then the nonlinear control signal decreases to the initial value with a preset slew rate.

Yet another embodiment of the present invention discloses a control circuit for a multi-phase converter, wherein the multi-phase converter is configured to receive an input voltage, and configured to provide an output voltage and a load current to a load, and wherein the multi-phase converter comprises a plurality of switching circuits coupled in parallel between the input voltage and the load, the control circuit comprising: a load current comparison unit, configured to receive a current sense signal indicative of the load current, and configured to provide a plurality of current comparison signals to control a number of the plurality of switching circuits under power operation via respectively comparing the current sense signal with a plurality of thresholds; a nonlinear control signal generation unit, configured to provide a nonlinear control signal, wherein when the number of the plurality of switching circuits under power operation decreases, the nonlinear control signal increases to a preset value from an initial value, and then the nonlinear control signal decreases to the initial value with a preset slew rate; a general comparison unit, configured to receive a feedback signal indicative of the output voltage, the general comparison unit is configured to provide a set signal to successively turn ON the specific plurality of switching circuits under power operation via comparing the feedback signal with a sum of a reference signal and the nonlinear control signal; and a logic control unit, coupled to the load current comparison unit to receive the plurality of current comparison signals, and coupled to the general comparison unit to receive the set signal, the logic control unit is configured to provide multiple control signals to respectively control the plurality of switching circuits based on the plurality of current comparison signals and the set signal.

Embodiments of the present invention, providing a nonlinear control signal which varies with decreasing of the number of switching circuits under power operation, could conspicuous reduce an undershoot of the output voltage once the number of switching circuits under power operation decreases.

Non-limiting and non-exhaustive embodiments are described with reference to the following drawings.

FIG. 1 illustrates a multi-phase converter 100 according to an embodiment of the present invention.

FIG. 2 shows waveforms of multi-phase converter 100 while four switching circuits are under power operation according to an embodiment of the present invention.

FIG. 3 shows waveforms of multi-phase converter 100 while two switching circuits are under power operation according to an embodiment of the present invention.

FIG. 4 schematically illustrates a comparison unit 103 according to an embodiment of the present invention.

FIG. 5 diagrammatically shows generating of nonlinear control signal Vnl according to an embodiment of the present invention.

FIG. 6 schematically illustrates a nonlinear control signal generation unit 106 according to an embodiment of the present invention.

FIG. 7 diagrammatically shows generating of digital signal Dnl according to an embodiment of the present invention.

FIG. 8 schematically illustrates a three-phase converter 100 A according to an embodiment of the present invention.

FIG. 9 schematically illustrates a logic control unit 104 A as shown in FIG. 8 according to an embodiment of the present invention.

FIG. 10 shows a flow chart 800 of a control method of multi-phase converter 100 as shown in FIG. 1 according to an embodiment of the present invention.

The use of the same reference label in different drawings indicates the same or like components.

In the present application, numerous specific details are provided, such as examples of circuits, components, and methods, to provide a thorough understanding of embodiments of the invention. These embodiments are exemplary, not to confine the scope of the invention. Persons of ordinary skill in the art will recognize, however, that the invention can be practiced without one or more of the specific details. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention. Some phrases are used in some exemplary embodiments. However, the usage of these phrases is not confined to these embodiments.

FIG. 1 illustrates a multi-phase converter 100 according to an embodiment of the present invention. Multi-phase converter 100 receives an input voltage Vin, and provides an output voltage Vo and a load current Io to a load. Multi-phase converter 100 comprises a plurality of switching circuits ( 10 - 1 , 10 - 2 , . . . , 10 - n ) coupled in parallel between input voltage Vin and the load, a control circuit 11 , a voltage feedback unit 107 , a current feedback unit 108 , and an output capacitor 105 coupled between an output terminal of multi-phase converter 100 and a reference ground. Voltage feedback unit 107 is coupled to the load, and provides a feedback signal Vfb indicative of output voltage Vo. Current feedback unit 108 provides current sense signal Isen indicative of load current Io flowing through the load. Control circuit 11 comprises: an ON-time generation unit 101 , a load current comparison unit 102 , a general comparison unit 103 , a logic control unit 104 , and a nonlinear control signal generation unit 106 . Multi-phase converter 100 controls a number of switching circuits under power operation, that is controlling phase of switching circuits for providing power. Control circuit 11 provides a set signal Set to successively turn ON the switching circuits under power operation based on output voltage Vo, a reference signal Vref, and a nonlinear control signal Vnl. In one embodiment, when the number of switching circuits under power operation decreases, nonlinear control signal Vnl increases to a preset value from an initial value, and then, nonlinear control signal Vnl decreases to the initial value with a preset slew rate; and when the number of switching circuits under power operation increases or is unchanged, nonlinear control signal Vnl is maintained at the initial value. In one embodiment, the initial value is zero. In one embodiment, the preset value and/or the preset slew rate can be adjusted in advance.

ON-time generation unit 101 provides an ON-time threshold TON to control ON-time periods of the corresponding transistors inside the switching circuits under power operation. ON-time threshold TON could be set as a constant, or a value variable with the input voltage Vin or output voltage Vout.

Load current comparison unit 102 is coupled to current feedback unit 108 to receive current sense signal Isen. Load current comparison unit 102 is configured to determine the number of switching circuits under power operation based on current sense signal Isen. In one embodiment, load current comparison unit 102 compares current sense signal Isen respectively with a plurality of threshold (e.g., Vth_ 1 , Vth_ 2 , . . . , Vth_n−1) to generate a plurality of current comparison signals (e.g., Ph 1 , Ph 2 , . . . , Phn−1) to determine the number of switching circuits under power operation.

General comparison unit 103 is configured to receive feedback signal Vfb indicative of output voltage Vout, reference signal Vref, and nonlinear control signal Vnl, and configured to provide set signal Set via comparing feedback signal Vfb with sum of reference signal Vref and nonlinear control signal Vnl (i.e., Vref+Vnl). When sum of reference signal Vref and nonlinear control signal Vnl is larger than feedback signal Vfb (i.e., Vref+Vnl>Vfb), set signal Set turns ON one of the switching circuits under power operation.

Logic control unit 104 is coupled to ON-time generation unit 101 , load current comparison unit 102 , and general comparison unit 103 , and logic control unit 104 is configured to provide control signals (e.g., PWM 1 , PWM 2 , . . . , PWMn) based on set signal Set, ON-time threshold TON, and current comparison signals Ph 1 -Phn−1 to respectively control switching circuits (e.g., 10 - 1 , 10 - 2 , . . . , 10 - n ).

In one embodiment, logic control unit 104 determines the number of switching circuits under power operation based on current comparison signals Ph 1 -Phn−1, and all of the switching circuits or only part of the switching circuits enter power operation due to load current Io. In one embodiment, switching circuits under power operation will be interleaved turned ON by controlling of control signals PVVM 1 -PWMn. FIG. 2 shows waveforms of multi-phase converter 100 while four switching circuits are under power operation according to an embodiment of the present invention. And FIG. 3 shows waveforms of multi-phase converter 100 while two switching circuits are under power operation according to an embodiment of the present invention. Those switching circuits not under power operation remain OFF or in a high resistance state. As shown in FIG. 2 and FIG. 3 , positive pulses of set signal SET are successively provided to one of the switching circuits under power operation to turn ON corresponding transistor of the one of the switching circuits under power operation, and the corresponding transistor is turned OFF when ON-time period of the corresponding transistor equals ON-time threshold.

Logic control unit 104 is further configured to provide power indicating signal Cdrop to indicate phase shedding of multi-phase converter 100 , that is decreasing of the number of switching circuits under power operation based on current comparison signals Ph 1 -Phn−1.

Nonlinear control signal generation unit 106 is coupled to logic control unit 104 to receive power indicating signal Cdrop, and nonlinear control signal generation unit 106 is configured to provide nonlinear control signal Vnl. When power indicating signal Cdrop indicates that the number of switching circuits under power operation decreases, i.e., once phase shedding happens, nonlinear control signal Vnl increases to the preset value from the initial value, and then decreases to the initial value with the preset slew rate; and when power indicating signal Cdrop indicates that the number of switching circuits under power operation increases or is unchanged, nonlinear control signal Vnl is maintained at the initial value. Undershoot of output voltage Vo will be significantly reduced at the time that the number of switching circuits under power operation decreases when introducing nonlinear control signal Vnl.

FIG. 4 schematically illustrates general comparison unit 103 according to an embodiment of the present invention. As shown in FIG. 4 , general comparison unit 103 comprises an arithmetic circuit 21 and a comparator 22 . Arithmetic circuit 21 is configured to receive reference signal Vref and nonlinear control signal Vnl, and is configured to provide arithmetic signal Vref 2 based on the sum of reference signal Vref and nonlinear control signal Vnl (Vref+Vnl). Comparator 22 comprises a non-inverting terminal configured to receive arithmetic signal Vref 2 , an inverting terminal configured to receive feedback signal Vfb, and an output terminal configured to provide set signal Set. Comparator 22 is configured to provide set signal Set via comparing feedback signal Vfb with the sum of reference signal Vref and nonlinear control signal Vnl (Vref+Vnl).

FIG. 5 diagrammatically shows generating of nonlinear control signal Vnl according to an embodiment of the present invention. As shown in FIG. 5 , a positive pulse of a power indication signal Cdrop indicates that the number of switching circuits under power operation decreases, e.g., reducing from 6-phase switching circuits operation to 5-phase switching circuits operation, and reducing from 5-phase switching circuits operation to 3-phase switching circuits operation as shown in FIG. 5 . In the embodiment shown in FIG. 5 , the initial value of nonlinear control signal Vnl is zero. When power indication signal Cdrop indicates that the number of switching circuits under power operation decreases, nonlinear control signal Vnl increases to preset value Vpk from the initial value, and then decreases to the initial value with preset slew rate Vslew. That is once the number of switching circuits under power operation decreases, a triple wave of nonlinear control signal Vnl is added to reference signal Vref for compensation to reduce undershoot of output voltage Vo. In one embodiment, preset value Vpk and preset slew rate Vslew are adjustable and could affect undershoot performance of output voltage Vo. When the number of switching circuits under power operation increases or is unchanged, e.g., increasing from 3-phase switching circuits operation to 4-phase switching circuits operation as shown in FIG. 5 , power indication signal Cdrop keeps unchanged, and nonlinear control signal Vnl is maintained at the initial value.

FIG. 6 schematically illustrates a nonlinear control signal generation unit 106 according to an embodiment of the present invention. In the embodiment shown in FIG. 6 , nonlinear control signal generation circuit 106 comprises a digital control unit 41 and a digital-to-analog conversion unit 42 . Digital control unit 41 provides a digital signal Dnl, and digital signal Dnl has a first digital value DO. When the number of switching circuits under power operation decreases, digital signal Dnl equals a second digital value Dpk, and then digital control unit 41 is configured to decrease digital signal Dnl in a plurality of steps until digital signal Dnl equals the first digital value DO. Digital-to-analog conversion unit 42 is configured to convert digital signal Dnl into nonlinear control signal Vnl via digital to analog converting.

FIG. 7 diagrammatically shows generating of digital signal Dnl according to an embodiment of the present invention. As shown in FIG. 7 , digital signal Dnl has first digital value DO, and when the number of switching circuits under power operation decreases, power indication signal Cdrop provides a positive pulse, digital signal Dnl equals second digital value Dpk, and then digital signal Dnl is decreased in a plurality of steps until digital signal Dnl equals first digital value DO. In one embodiment, digital control unit 41 is configured to decrease digital signal Dnl by a preset digital value Step 1 during each of the plurality of steps. In one embodiment, at least one of a time period T 1 of each of the plurality of steps and preset digital value Step 1 is adjustable. Thus, slew rate of digital signal Dnl is determined by time period T 1 of each of the plurality of steps and preset digital value Step 1 .

FIG. 8 schematically illustrates a three-phase converter 100 A according to an embodiment of the present invention. In the embodiment shown in FIG. 8 , switching circuits 10 A- 1 , 10 A- 2 , and 10 A- 3 employ synchronous step-down topology, however one of an ordinary skill in the art should know that other suitable topologies could also be used without detracting merits of the spirit of this invention. ON-time generation unit 101 , load current comparison unit 102 , general comparison unit 103 , logic control unit 104 A, and nonlinear control signal generation unit 106 are integrated in control circuit 11 A. ON-time generation unit 101 , general comparison unit 103 , and nonlinear control signal generation unit 106 are the same as shown in FIG. 1 .

As shown in FIG. 8 , load current comparison unit 102 A comprises comparators 81 - 83 . Comparators 81 - 83 respectively compare current sense signal Isen with thresholds Vth_ 1 and Vth_ 2 to determine the number of switching circuits under power operation. In one embodiment, threshold Vth_ 1 is larger than threshold Vth_ 2 (Vth_ 1 >Vth_ 2 ). When current sense signal Isen is larger than threshold Vth_ 1 , i.e., Isen>Vth_ 1 >Vth_ 2 , current comparison signal Ph 1 =1, current comparison signal Ph 2 =1, all of switching circuits 10 A- 1 , 10 A- 2 , and 10 A- 3 enter power operation. When current sense signal Isen is less than threshold Vth_ 1 , and larger than threshold Vth_ 2 , i.e., Vth_ 1 >Isen>Vth_ 2 , current comparison signal Ph 1 =0, current comparison signal Ph 2 =1, two of switching circuits 10 A- 1 , 10 A- 2 , and 10 A- 3 enter power operation. i.e., switching circuits 10 A- 1 and 10 A- 2 are under power operation and switching circuit 10 A- 3 exits power operation, transistors in switching circuit 10 A- 3 are high impedance. Structure and operating principle of load current comparison unit 102 for multi-phase converter 100 is similar with load current comparison unit 102 A.

FIG. 9 schematically illustrates a logic control unit 104 A as shown in FIG. 8 according to an embodiment of the present invention. Logic control unit 104 of multi-phase converter 100 is similar with logic control unit 104 A. As shown in FIG. 9 , logic control unit 104 A comprises a frequency dividing unit 161 , sub-control units 162 _ 1 , 162 _ 2 , and 162 _ 3 , and a phase dropping detection unit 163 .

Frequency dividing unit 161 is configured to receive set signal Set and current comparison signals Ph 1 and Ph 2 , and frequency dividing unit 161 is configured to distribute pulses of set signal Set to set signals SET 1 -SET 3 . In one embodiment, when current comparison signals Ph 1 and Ph 2 indicate that the number of switching circuits under power operation is three, pulses of set signal SET is distributed to set signals SET 1 -SET 3 to successively turn ON switching circuits 10 A- 1 , 10 A- 2 , and 10 A- 3 . When current comparison signals Ph 1 and Ph 2 indicate that the number of two switching circuits under power operation is two, pulses of set signal Set is distributed to two of set signals SET 1 -SET 3 to successively turn on two of switching circuits 10 A- 1 , 10 A- 2 , and 10 A- 3 . And when current comparison signals Ph 1 and Ph 2 indicate that the number of switching circuits under power operation is only one, pulses of set signal Set is distributed to one of set signals SET 1 -SET 3 to turn on one of switching circuits 10 A- 1 , 10 A- 2 , and 10 A- 3 , e.g., turn ON switching circuit 10 A- 1 based on set signal Set.

Each of sub-control units 162 _ 1 , 162 _ 2 , and 162 _ 3 comprises a first input terminal, a second input terminal and an output terminal. The first input terminal of sub-control unit 162 _ 1 is coupled to frequency dividing unit 161 to receive set signal SET 1 , the second input terminal of sub-control unit 162 _ 1 is coupled to ON-time generation unit 101 to receive ON-time threshold TON, and the output terminal of sub-control unit 162 _ 1 is configured to provide a control signal PWM 1 to control switching circuit 10 A- 1 . The first input terminal of sub-control unit 162 _ 2 is coupled to frequency dividing unit 161 to receive set signal SET 2 , the second input terminal of sub-control unit 162 _ 2 is coupled to ON-time generation unit 101 to receive ON-time threshold TON, and the output terminal of sub-control unit 162 _ 2 is configured to provide a control signal PWM 2 to control switching circuit 10 A- 2 . The first input terminal of sub-control unit 162 _ 3 is coupled to frequency dividing unit 161 to receive set signal SET 3 , the second input terminal of sub-control unit 162 _ 3 is coupled to ON-time generation unit 101 to receive ON-time threshold TON, and the output terminal of sub-control unit 162 _ 3 is configured to provide a control signal PWM 3 to control switching circuit 10 A- 3 . In one embodiment, each of sub-control units 162 _ 1 , 162 _ 2 , and 162 _ 3 comprises a SR flip-flop. Take sub-control unit 162 _ 1 as one example, the SR flip-flop of sub-control unit 162 _ 1 comprises a set terminal, a reset terminal, and an output terminal, wherein the set terminal S is configured to receive set signal SET 1 , the reset terminal R is configured to receive ON-time threshold TON, and the output terminal Q is configured to provide control signal PWM 1 .

Phase dropping detection unit 163 is configured to provide power indicating signal Cdrop. For example, when current comparison signals Ph 1 and Ph 2 indicate that the number of switching circuits under power operation decreases, phase dropping detection unit 163 is configured to provide a pulse on power indicating signal Cdrop. In the embodiment shown in FIG. 9 , phase dropping detection unit 163 comprises delay units 91 and 92 , comparison units 93 and 94 , and an OR gate 95 . Delay unit 91 receives current comparison signal Ph 1 , and provides delay signal Dl 1 by delaying current comparison signal Ph 1 a first time period. Comparison unit 93 compares delay signal Dl 1 with current comparison signal Ph 1 , and provides comparison signal Cm 1 accordingly. Delay unit 92 receives current comparison signal Ph 2 , and provides delay signal Dl 2 by delaying current comparison signal Ph 2 a second time period. The first time period may equal the second time period. Comparison unit 94 compares delay signal Dl 2 with current comparison signal Ph 2 , and provides comparison signal Cm 2 accordingly. OR gate 95 receives comparison signals Cm 1 and Cm 2 , and provides a signal at an output terminal of OR gate 95 via OR operating. A pulse generation circuit 96 is coupled to the output terminal of OR gate, and pulse generation circuit 96 is configured to provide power indicating signal Cdrop.

FIG. 10 shows a flow chart 800 of a control method of multi-phase converter 100 as shown in FIG. 1 according to an embodiment of the present invention. The control method shown in FIG. 10 comprises steps S 81 -S 84 .

At step S 81 , determining the number of switching circuits under power operation based on load current Io of multi-phase converter 100 .

At step S 82 , providing nonlinear control signal Vnl based on a variation of the number of switching circuits under power operation.

At step S 83 , providing set signal Set to successively turn ON switching circuits under power operation based on output voltage Vo, reference signal Vref and nonlinear control signal Vnl.

At step S 84 , controlling the ON-time period of a switching circuit under operation based on ON-time threshold TON.

While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.