Circuit module for modelling a digital circuit and simulation device including the circuit module

The present application claims priority under 35 U.S.C. § 119(a) to a Korean Patent Application No. 10-2018-0079299, filed on Jul. 9, 2018, which are incorporated herein by reference in its entirety.

1. Technical Field

Various embodiments generally relate to a circuit module for modeling a digital circuit and a simulation device including the circuit module.

2. Related Art

Various techniques for modelling an operation of a digital circuit in accordance with a transition of an input signal have been developed.

Commercial chips include a large number of digital circuits. Spice simulation, which is commonly used, takes a very long time for simulation. Therefore, it is very difficult to verify chip operations when a simulation speed is slow. Accordingly, there is a demand for a technique of efficiently reducing a simulation time for a digital circuit.

In accordance with the present teachings, a circuit module includes a model circuit configured to generate an output signal based on one or more input signals and correspond to a digital circuit, and a look-up table (LUT) storing one or more control signals and one or more operation parameters that are to be used to implement the model circuit, the one or more control signals and the one or more operation parameters corresponding to an index determined by a combination of the one or more input signals and the output signal.

In accordance with the present teachings, a simulation devices includes a model circuit configured to generate an output signal based on one or more input signals and correspond to a digital circuit, a look-up table (LUT) storing one or more control signals and one or more operation parameters that are to be used to implement the model circuit, the one or more control signals and the one or more operation parameters corresponding to an index determined by a combination of the one or more input signals and the output signal, and a control circuit configured to simulate the digital circuit by controlling the model circuit and the LUT.

The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views, together with the detailed description below, are incorporated in and form part of the specification, and serve to further illustrate embodiments of concepts that include the claimed novelty, and explain various principles and advantages of those embodiments.

FIG. 1 shows a block diagram illustrating a digital circuit.

FIG. 2 shows a block diagram illustrating a simulation device according to an embodiment of the present disclosure.

FIGS. 3 and 4 show circuit diagrams illustrating variable delay circuits according to embodiments of the present disclosure.

FIGS. 5 to 8 show tables illustrating a structure of a Look-Up Table (LUT) according to an embodiment of the present disclosure.

FIG. 9 shows a flow chart illustrating a method of generating a circuit module according to an embodiment of the present disclosure.

FIG. 10 shows an example of simulation according to an embodiment of the present disclosure.

FIG. 11 shows a graph illustrating an operation of a simulation device according to an embodiment of the present disclosure.

FIG. 12 shows a block diagram illustrating a digital circuit having a plurality of output signals according to an embodiment of the present disclosure.

FIG. 13 shows a block diagram illustrating an equivalent digital circuit of the digital circuit shown in FIG. 12 according to an embodiment of the present disclosure.

The following detailed description references the accompanying figures in describing illustrative embodiments consistent with this disclosure. The embodiments are provided for illustrative purposes and are not exhaustive. Additional embodiments not explicitly illustrated or described are possible. Further, modifications can be made to presented embodiments within the scope of the present teachings. The detailed description is not meant to limit this disclosure. Rather, the scope of the present disclosure is defined in accordance with the presented claims and equivalents thereof.

FIG. 1 shows a block diagram illustrating a digital circuit 1 .

Referring to FIG. 1 , the digital circuit 1 may generate an output signal y 1 based on two input signals a 1 and a 2 .

The digital circuit 1 may include a digital gate circuit such as a NAND gate, a NOR gate, or the like.

The digital circuit 1 may include a plurality of logic gates that are combined to generate one output signal y 1 based on the two input signals a 1 and a 2 .

Hereinafter, it is assumed that the digital circuit 1 is a NAND gate.

FIG. 2 shows a block diagram illustrating a simulation device according to an embodiment of the present disclosure.

The simulation device performs a simulation using a circuit module which models the digital circuit 1 of FIG. 1 .

In this embodiment, the circuit module includes a model circuit 10 and a look-up table (LUT) 20 .

In this embodiment, the simulation device further includes a control circuit 30 for controlling the model circuit 10 and the LUT 20 to perform a simulation operation.

The control circuit 30 may provide one or more control signals or one or more operation parameters to the model circuit 10 by referring to the LUT 20 in accordance with the change of an input signal, e.g., a 1 and/or a 2 , inputted to the circuit module during the simulation operation.

The LUT 20 stores a plurality of control signals and operation parameters for controlling an operation of the model circuit 10 , which are determined to correspond to combinations of the input signals a 1 and a 2 and the output signal y 1 .

The model circuit 10 includes a plurality of delay inverter circuits 100 and 200 each delaying a corresponding input signal a 1 or a 2 and a switching circuit 300 connecting one of the delay inverter circuits 100 and 200 with an output node N 1 where an output signal y 1 is provided.

The model circuit 10 may further include a capacitor 400 connected to the output node N 1 .

The capacitance C of the capacitor 400 may be stored in the LUT 20 .

The first delay inverter circuit 100 includes a first variable delay circuit 110 for delaying the first input signal a 1 in accordance with a first delay control signal D 1 and a first inverter circuit 120 for inverting an output of the first variable delay circuit 110 .

The second delay inverter circuit 200 includes a second variable delay circuit 210 for delaying the second input signal a 2 in accordance with a second delay control signal D 2 and a second inverter circuit 220 for inverting an output of the second variable delay circuit 210 .

A delay amount of the first variable delay circuit 110 is set by the first delay control signal D 1 provided from the LUT 20 , and a delay amount of the second variable delay circuit 210 is set by the second delay control signal D 2 provided from the LUT 20 .

At this time, the first and second delay control signals D 1 and D 2 may have values for directly designating the delay amounts of the first and second variable delay circuits 110 and 210 , respectively.

In another embodiment, the first variable delay circuit 110 has the configuration shown in FIG. 3 , and the second variable delay circuit 210 has the configuration shown in FIG. 4 .

At this time, the first and second variable delay circuits 110 and 210 have substantially the same configuration.

Referring to FIG. 3 , the first variable delay circuit 110 includes a plurality of delay circuits 111 and 112 for delaying the first input signal a 1 according to different delay amounts and a selection circuit 113 for selecting one of outputs of the plurality of delay circuits 111 and 112 .

Although the two delay circuits 111 and 112 are shown in FIG. 3 , the number of delay circuits included in the first variable delay circuit 110 can be set differently according to embodiments.

A selection signal SEL 1 provided to the selection circuit 113 is stored in the LUT 20 . This will be described in detail below.

In the present embodiment, the first inverter circuit 120 included in the first delay inverter circuit 100 includes a PMOS transistor P 1 and an NMOS transistor N 1 whose gates are connected in common to an input node and whose drains are connected in common to an output node. The input node of the first inverter circuit 120 is connected to the first variable delay circuit 110 , and the output node of the first inverter circuit 120 is connected to the switching circuit 300 .

In this embodiment, the LUT 20 stores operation parameters of the PMOS transistor P 1 and the NMOS transistor N 1 .

The operation parameters provided to the first inverter circuit 120 set a rising or falling transition time of the output signal y 1 .

The operation parameters of the PMOS transistor P 1 includes transconductance GMP 1 and a threshold voltage THP 1 , and the operation parameters of the NMOS transistor N 1 includes transconductance GMN 1 and a threshold voltage THN 1 .

Referring to FIG. 4 , the second variable delay circuit 210 includes a plurality of delay circuits 211 and 212 for delaying the second input signal a 2 by different delay amounts and a selection circuit 213 for selecting one of outputs of the plurality of delay circuits 211 and 212 .

Although the two delay circuits 211 and 212 are shown in FIG. 4 , the number of delay circuits included in the second variable delay circuit 210 may vary according to embodiments.

A selection signal SEL 2 provided to the selection circuit 213 is stored in the LUT 20 . This will be described in detail below.

In the present embodiment, the second inverter circuit 220 included in the second delay inverter circuit 200 includes a PMOS transistor P 2 and an NMOS transistor N 2 whose gates are connected in common to an input node and whose drains are connected in common to an output node. The input node of the second inverter circuit 220 is connected to the second variable delay circuit 210 , and the output node of the second inverter circuit 220 is connected to the switching circuit 300 .

The operation parameters provided to the second inverter circuit 220 sets the rising or falling transition time of the output signal y 1 .

In this embodiment, the LUT 20 stores operation parameters of the PMOS transistor P 2 and the NMOS transistor N 2 .

The operation parameters of the PMOS transistor P 2 include transconductance GMP 2 and a threshold voltage THP 2 , and the operation parameters of the NMOS transistor N 2 include transconductance GMN 2 and a threshold voltage THN 2 .

The number of delay inverter circuits included in the model circuit 10 corresponds to the number of input signals.

For example, if there are N (N is a natural number) input signals, N delay inverter circuits may be included in the model circuit 10 .

The switching circuit 300 includes a first switch 310 for providing the output of the first delay inverter circuit 100 to the output node N 1 in response to a first switch signal SW 1 and a second switch 320 for providing the output of the second delay inverter circuit 200 to the output node N 1 in response to a second switch signal SW 2 .

The number of switches included in the switching circuit 300 corresponds to the number of delay inverter circuits included in the model circuit 10 .

For example, if there are N delay inverter circuits in the model circuit 10 , N switches may be included in the switching circuit 300 .

In this case, each of the switches provides the output of the corresponding delay inverter circuit to the output node N 1 in response to the corresponding switch signal.

When there is one delay inverter circuit, the switching circuit 300 may include one switch, and thus the output of the delay inverter circuit may be directly connected to the output node N 1 via the one switch.

The value of the output node N 1 corresponds to the output signal y 1 .

FIGS. 5 to 8 shows tables illustrating the LUT 20 of FIG. 2 according to an embodiment of the present disclosure.

Hereinafter, a method for generating the LUT 20 is disclosed assuming that the digital circuit 1 is a NAND gate.

FIG. 5 shows a table for setting state variables corresponding to combinations of the input signals a 1 and a 2 .

Hereinafter, the table shown in FIG. 5 may be referred to as a first table 21.

In the present embodiment, state 1 corresponds to a case where the input signals a 1 and a 2 are (0, 0), state 2 corresponds to a case where the input signals a 1 and a 2 are (0, 1), state 3 corresponds to a case where the input signals a 1 and a 2 are (1, 0), and state 4 corresponds to a case where the input signals a 1 and a 2 are (1, 1).

Thus, each of the states in the first table 21 corresponds to a corresponding combination of the input signals a 1 and a 2 .

FIG. 6 shows a table for setting an index variable corresponding to the change of a state causing the change of the output signal y 1 .

Hereinafter, the table shown in FIG. 6 may be referred to as a second table 22.

In FIG. 5 , a case where the output signal y 1 changes from 1 to 0 corresponds to a case where the current state is one of 1, 2, and 3 and the next state is 4, and a case where the output signal y 1 changes from 0 to 1 corresponds to a case where the current state is 4 and the next state is one of 1, 2, and 3.

In the second table 22 of FIG. 6 , an index value is given for each of six combinations of the current state and the next state.

In the present embodiment, index 1 corresponds to a case where the current state is 1 and the next state is 4, index 2 corresponds to a case where the current state is 2 and the next state is 4, index 3 corresponds to a case where the current state is 3 and the next state is 4, index 4 corresponds to a case where the current state is 4 and the next state is 1, index 5 corresponds to a case where the current state is 4 and the next state is 2, and index 6 corresponds to a case where the current state is 4 and the next state is 3.

FIGS. 7 and 8 show tables for storing control signals and operation parameters provided to the model circuit 10 of FIG. 2 for each index in FIG. 6 .

Hereinafter, the tables shown in FIGS. 7 and 8 may be referred to as third tables 23 and 23-1, respectively.

Each index in FIG. 6 corresponds to a case where the output signal y 1 transitions as shown in FIG. 5 .

Each index in FIG. 6 corresponds to a case where the output signal y 1 transitions as shown in FIG. 5 .

The third table 23-1 of FIG. 8 stores the selection signals SEL 1 and SEL 2 , the first and second switch signals SW 1 and SW 2 , and the operation parameters GMP 1 , THP 1 , GMP 2 , THP 2 , and C to be provided to the model circuit 10 at the time when the output signal y 1 transitions. The third table 23-1 of FIG. 8 may further store the operation parameters GMN 1 , THN 1 , GMN 2 , and THN 2 .

Hereinafter, an operation of the control circuit 30 when the input signal changes will be described.

The control circuit 30 identifies that a case where the input signals a 1 and a 2 change from (0, 0) to (1, 1) corresponds to a case where the state variable changes from 1 to 4, and corresponds to the index 1 by referring to the first and second tables 21 and 22 respectively shown in FIGS. 5 and 6 .

When the control circuit 30 identifies that the change of the input signals a 1 and a 2 corresponds to the index 1, the control circuit 30 provides the delay control signals or selection signals, switch signals, and operation parameters corresponding to the index 1 to the model circuit 10 with reference to the third table 23 or 23-1.

When the state variable changes from 1 to 4, the output signal y 1 changes from 1 to 0, which corresponds to inverting the input signal a 1 . The input signal a 1 changes from 0 to 1.

Accordingly, the first and second switch signals SW 1 and SW 2 corresponding to the index 1 in the third table 23 or 23-1 are set such that the first switch 310 is turned on and the second switch 320 is turned off.

In this embodiment, the LUT 20 may include the first table 21, the second table 22, and the third table 23 or 23-1 described above.

The structure of each table included in the LUT 20 may vary according to embodiments.

FIG. 9 shows a flow chart illustrating a method of generating a circuit module according to an embodiment of the present disclosure.

First, a pre-simulation is performed at S 100 .

In the pre-simulation process, a spice simulation for the digital circuit 1 is performed using a spice model corresponding to an actual manufacturing process.

At this time, logic values of the output signal y 1 for all combinations of the input signals a 1 and a 2 , a delay amount, and a transition time of the output signal y 1 based on the change of the input signals a 1 and a 2 can be obtained from the result of the pre-simulation process.

Next, the LUT 20 is generated at S 200 .

For example, the first table 21 shown in FIG. 5 is generated by assigning a state value to each combination of the input signals a 1 and a 2 , and the second table 22 shown in FIG. 6 is generated by assigning an index value to each combination of state changes.

Then, the third table 23 or 23-1 respectively shown in FIG. 7 or 8 is generated so that control signals and operation parameters corresponding to each index may be allocated.

The specific values of the control signals and operation parameters corresponding to each index of the third tables 23 and 23-1 are not determined yet.

Next, the model circuit 10 is generated at S 300 .

The model circuit 10 has a structure as shown in FIG. 2 .

The model circuit 10 includes the first and second delay inverter circuits 100 and 200 corresponding to the number of input signals a 1 and a 2 as described above.

The model circuit 10 may further include the switching circuit 300 for selectively providing one of the outputs of the first and second delay inverter circuits 100 and 200 to the output node N 1 and the capacitor 400 connected to the output node N 1 .

Next, the control signals and operation parameters for controlling the model circuit 10 are extracted at S 400 .

In this embodiment, the control signals include the delay control signals D 1 and D 2 , the selection signals SEL 1 and SEL 2 , and the switch signals SW 1 and SW 2 .

In this embodiment, the operation parameters include the transconductances GMP 1 , GMN 1 , GMP 2 , and GMN 2 , the threshold voltages THP 1 , THN 1 , THP 2 , and THN 2 , and the capacitance C of the capacitor 400 .

The logic values, delay time information, and transition time information obtained in the pre-simulation step S 100 can be used to generate equations with variables corresponding to the above control signals and the operation parameters.

For example, the delay control signals D 1 and D 2 and the switch signals SW 1 and SW 2 can be determined based on the logic values and the delay amount of the output signal y 1 for the input signals a 1 and a 2 , the logic values and the delay amount of the output signal y 1 being obtained from the pre-simulation process.

The operating parameters such as the transconductances GMP 1 , GMP 2 , GMN 1 , and GMN 2 , the threshold voltages THP 1 , THN 1 , THP 2 , and THN 2 , and the capacitance C of the capacitor 400 can be determined from the delay amount and the transition time.

The equations and the above determining method are easily known to the ordinarily skilled in the art, so that specific examples thereof are omitted.

The operation parameters may be determined by applying numerical methods so that an error occurring in the pre-simulation is minimized when the exact solution cannot be obtained from the equations.

These control signals and operation parameters are determined for each index, and the control circuit 30 can provide the control signals and operation parameters stored in the third table 23 or 23-1 to the model circuit 10 with reference to the corresponding index.

FIG. 10 shows an example of simulation where the output signal y 1 transitions according to the change of the input signals a 1 and a 2 .

In FIG. 10 , the input signals a 1 and a 2 change from (0, 1) to (1, 1).

When the input signals a 1 and a 2 change from (0, 1) to (1, 1), the control circuit 30 refers to the first table 21 shown in FIG. 5 and identifies that the change of the input signals a 1 and a 2 corresponds to the state change from 2 to 4. The control circuit 30 refers to the second table 22 and identifies that the state change from 2 to 4 corresponds to the index 2.

After that, the control circuit 30 outputs control signals and operation parameters corresponding to the index 2 to the model circuit 10 with reference to the third table 23 or 23-1, such that previous control signals and operation parameters for the model circuit 10 are updated with the control signals and operation parameters corresponding to the index 2.

When the input signals a 1 and a 2 change from (0, 1) to (1, 1), the model circuit 10 may operate according to the updated control signals and operation parameters, and may provide a waveform of the output signal y 1 shown in FIG. 10 . Therefore, when the output signal y 1 changes from 1 to 0, and the modeling for a delay amount of the output signal y 1 is accurately performed based on the updated control signals and operation parameters.

FIG. 11 shows a graph illustrating an operation of a simulation device according to an embodiment of the present disclosure.

In FIG. 11 , (1) indicates a result of the pre-spice simulation, and (2) indicates a simulation result using the model circuit 10 and the LUT 20 according to the present embodiment.

When considering a time period from a 50% rising point of the input signal a 1 to a 50% falling point of the output signal y 1 , the time period in case of (1) is 19 ps and the time period in case of (2) is 20.2 ps.

In the present disclosure, when a digital circuit is very large, the entire digital circuit is divided into a plurality of sub-digital circuits, and a circuit module is generated for each of the sub-digital circuits. A simulation is sequentially or parallelly performed on all the circuit modules for the sub-digital circuits, so that the simulation for the entire digital circuit can be performed.

In the conventional case, it takes a long time to simulate the entire digital circuit.

However, a simulation time for the entire digital circuit can be greatly reduced by applying the simulation technology of the present disclosure to each sub-digital circuit and combining the simulation results of the sub-digital circuits.

For example, if the present disclosure is applied to a digital circuit including about 1000 inverters, a time reduction of about 1000 times can be expected as compared with the conventional technique of performing the spice simulation on the entire digital circuit.

Accordingly, when the present disclosure is applied, the simulation time may be greatly reduced while achieving a simulation result similar to that of the spice simulation.

FIG. 12 shows a digital circuit 2 having two output signals according to an embodiment of the present disclosure.

In order to apply the modelling technology according to the present disclosure, the digital circuit of FIG. 12 may include a first digital circuit 2 - 1 for generating a first output signal y 1 based on two input signals a 1 and a 2 and a second digital circuit 2 - 2 for generating a second output signal y 2 based on the input signals a 1 and a 2 , as shown in FIG. 13 .

The model circuit 10 and the LUT 20 can be generated for each of the first and second digital circuits 2 - 1 and 2 - 2 as described above with reference to FIG. 2-8 .

By performing simulations in parallel on the first and second digital circuits 2 - 1 and 2 - 2 , a simulation result for the digital circuit 2 in FIG. 12 can be obtained.

A model circuit for a digital circuit having M input signals and N output signals may be easily derived from the above disclosure, where M and N are natural numbers.

The above described model circuit 10 may be implemented as a software module and stored in a semiconductor chip or a storage medium readable by a computer.

The LUT 20 and the control circuit 30 may be implemented as a hardware chip, but may also be implemented as a software module.

If each of the LUT 20 and the control circuit 30 is implemented as a software module, the software modules for the LUT 20 and the control circuit 30 may be stored in a storage medium together with or separately from the software module for the model circuit 10 .

Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made to the described embodiments without departing from the spirit and scope of the disclosure as defined by the following claims.