Voltage regulation circuit suitable to provide output voltage to core circuit

The present invention relates to a regulation circuit, and in particular it relates to a voltage regulation circuit.

With the advancement of technology, there are more types of electronic devices available on the market, and these electronic devices have more and more functions. In general, many integrated circuits are mounted inside an electronic device. Each of the integrated circuits may receive many operation voltages, wherein the operation voltages are different.

However, when an integrated circuit uses an input voltage that exceeds its required operation voltage, the integrated circuit may be damaged or experience abnormal operation. Therefore, the design of the above structure still needs to be improved.

An embodiment of the present invention provides a voltage regulation circuit, thereby avoiding situations wherein an unsuitable output voltage is provided to a core circuit, which may result in abnormal operation or damage to the core circuit, and increasing the security and stability of the operation of the circuit.

An embodiment of the present invention provides a voltage regulation circuit suitable to provide an output voltage to a core circuit. The voltage regulation circuit includes a pad, a pull-down unit, a first control unit, a second control unit and a voltage regulation unit. The pad is configured to receive and provide an input voltage. The pull-down unit is coupled to the pad. The pull-down unit is configured to receive the input voltage and generate a pull-down voltage according to the input voltage. The first control unit is coupled to the pad and the pull-down unit. The first control unit is configured to receive the input voltage and the pull-down voltage and generate a first control signal according to the input voltage and the pull-down voltage. The second control unit is coupled to the pad and the first control unit. The second control unit is configured to receive the input voltage and the first control signal and generate a second control signal according to the input voltage and the first control signal. The voltage regulation unit is coupled to the pad, the first control unit and the second control unit. The voltage regulation unit is configured to receive the input voltage, the first control signal and the second control signal and regulate the input voltage according to the first control signal and the second control signal, so as to generate the output voltage.

According to the voltage regulation circuit disclosed by the embodiment of the present invention, the pull-down unit generates the pull-down voltage according to the input voltage. The first control unit generates the first control signal according to the input voltage and the pull-down voltage. The second control unit generates the second control signal according to the input voltage and the first control signal. The voltage regulation unit regulates the input voltage according to the first control signal and the second control signal, so as to generate the output voltage. Therefore, the embodiment of the present invention may effectively avoid situations wherein an unsuitable output voltage is provided to a core circuit, which may result in abnormal operation or damage to the core circuit, and increase the security and stability of the operation of the circuit.

The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 shows a schematic view of a voltage regulation circuit according to an embodiment of the present invention;

FIG. 2 shows a schematic view of a detailed circuit of a voltage regulation circuit according to an embodiment of the present invention;

FIG. 3 shows a schematic view of an operation of a voltage regulation circuit according to an embodiment of the present invention;

FIG. 4 shows a schematic view of an operation of a voltage regulation circuit according to another embodiment of the present invention; and

FIG. 5 shows a schematic view of an operation of a voltage regulation circuit according to another embodiment of the present invention.

In each of the following embodiments, the same reference number represents the same or similar element or component.

FIG. 1 shows a schematic view of a voltage regulation circuit according to an embodiment of the present invention. Please refer to FIG. 1 . In the embodiment, the voltage regulation circuit 100 is suitable to provide an output voltage VOUT to a core circuit 160 , so that the core circuit 160 may obtain a required working voltage to maintain a normal operation.

The voltage regulation circuit 100 includes a pad 110 , a pull-down unit 120 , a first control unit 130 , a second control unit 140 and a voltage regulation unit 150 . The pad 110 is configured to receive and provide an input voltage VIN. The pull-down unit 120 is coupled to the pad 110 . The pull-down unit 120 is configured to receive the input voltage VIN and generate a pull-down voltage VD according to the input voltage VIN.

The first control unit 130 is coupled to the pad 110 and the pull-down unit 120 . The first control unit 130 is configured to receive the input voltage VIN and the pull-down voltage VD and generate a first control signal CS 1 according to the input voltage VIN and the pull-down voltage VD. The second control unit 140 is coupled to the pad 110 and the first control unit 130 . The second control unit 140 is configured to receive the input voltage VIN and the first control signal CS 1 and generate a second control signal CS 2 according to the input voltage VIN and the first control signal CS 1 .

The voltage regulation unit 150 is coupled to the pad 110 , the first control unit 130 and the second control unit 140 . The voltage regulation unit 150 is configured to receive the input voltage VIN, the first control signal CS 1 and the second control signal CS 2 and regulate the input voltage VIN according to the first control signal CS 1 and the second control signal CS 2 , so as to generate the output voltage VOUT.

When the input voltage VIN is less than or equal to a predetermined value, the first control unit 130 regulates the voltage level of the first control signal CS 1 and the second control unit 140 regulates the voltage level of the second control signal CS 2 , so that the voltage regulation unit 150 maintains the voltage level of the input voltage VIN to generate the output voltage VOUT. In the embodiment, the predetermined value is, for example, the required working voltage of the core circuit 160 , and the predetermined value is, for example, 1.8V.

That is, when the input voltage VIN is less than or equal to the predetermined value (such as 1.8V), it indicates that the input voltage VIN may be supplied to the core circuit 160 . The first control unit 130 may regulate the voltage level of the first control signal CS 1 , and the second control unit 140 may regulate the voltage level of the second control signal CS 2 . Then, the voltage regulation unit 150 may maintain the voltage level of the input voltage VIN according to the voltage level of the first control signal CS 1 and the voltage level of the second control signal CS 2 , so as to generate the same output voltage VOUT as the voltage level of the input voltage VIN. Afterward, the output voltage VOUT is provided to the core circuit 160 .

In addition, when the input voltage VIN is greater than the predetermined value, the first control unit 130 regulates the voltage level of the first control signal CS 1 and the second control unit 140 regulates the voltage level of the second control signal CS 2 , so that the voltage regulation unit 150 decreases the voltage level provided by the input voltage VIN to generate the output voltage VOUT.

That is, when the input voltage VIN is greater than the predetermined value (such as 1.8V), it indicates that the input voltage VIN is greater than the required working voltage of the core circuit 160 . The first control unit 130 may regulate the voltage level of the first control signal CS 1 , and the second control unit 140 may regulate the voltage level of the second control signal CS 2 . Then, the voltage regulation unit 150 may decrease the voltage level provided by the input voltage VIN according to the voltage level of the first control signal CS 1 and the voltage level of the second control signal CS 2 . For example, the voltage regulation unit 150 decreases the voltage level provided by the input voltage VIN to the same voltage level as the predetermined value, so as to generate the output voltage VOUT that is the same as the predetermined value. Afterward, the output voltage VOUT is provided to the core circuit 160 .

It can be seen that when the input voltage VIN is less than or equal to the predetermined value, the voltage regulation circuit 100 directly uses the input voltage VIN as the output voltage VOUT and provides the output voltage VOUT to the core circuit 160 . When the input voltage VIN is greater than the predetermined value, the voltage regulation circuit 100 decreases the voltage level provided by the input voltage VIN, uses the decreased voltage level as the output voltage VOUT, and provides the output voltage VOUT to the core circuit 160 . Therefore, the voltage regulation circuit 100 may avoid situations wherein the unsuitable output voltage VOUT is provided to the core circuit 160 , which may result in abnormal operation or damage to the core circuit 160 , and increase the security and stability of the operation of the circuit.

FIG. 2 shows a schematic view of a detailed circuit of a voltage regulation circuit according to an embodiment of the present invention. Please refer to FIG. 2 . The pull-down unit 120 includes an inverter 210 and a transistor N 1 . The inverter 210 has an input terminal and an output terminal. The input terminal of the inverter 210 is coupled to the pad 110 and receives the input voltage VIN. The output terminal of the inverter 210 generates an inversion signal.

The transistor N 1 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor N 1 is coupled to the output terminal of the inverter 210 . The second terminal of the transistor N 1 generates the pull-down voltage VD. The third terminal and the fourth terminal of the transistor N 1 receive a first voltage V 1 . In the embodiment, the first voltage V 1 is, for example, a grounding voltage GND.

Furthermore, the inverter 210 includes a transistor P 1 and a transistor N 2 . The transistor P 1 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor P 1 serves as the input terminal of the inverter 210 and receives the input voltage VIN. The second terminal of the transistor P 1 serves as the output terminal of the inverter 210 and generates the inversion signal. The third terminal and the fourth terminal of the transistor P 1 receive a second voltage V 2 . In the embodiment, the second voltage V 2 may be a working voltage, such as 1.8V.

The transistor N 2 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor N 2 is coupled to the first terminal of the transistor P 1 . The second terminal of the transistor N 2 is coupled to the second terminal of the transistor P 1 . The third terminal and the fourth terminal of the transistor N 2 receive the first voltage V 1 (i.e., the grounding voltage GND).

In the embodiment, both the transistors N 1 and N 2 are, for example, N-type transistors. The first terminal of the transistors N 1 or N 2 is, for example, a gate terminal of the N-type transistor. The second terminal of the transistors N 1 or N 2 is, for example, a drain terminal of the N-type transistor. The third terminal of the transistors N 1 or N 2 is, for example, a source terminal of the N-type transistor. The fourth terminal of the transistors N 1 or N 2 is, for example, a base terminal of the N-type transistor.

In addition, the transistor P 1 is, for example, a P-type transistor. The first terminal of the transistor P 1 is, for example, a gate terminal of the P-type transistor. The second terminal of the transistor P 1 is, for example, a drain terminal of the P-type transistor. The third terminal of the transistor P 1 is, for example, a source terminal of the P-type transistor. The fourth terminal of the transistor P 1 is, for example, a base terminal of the P-type transistor.

The first control unit 130 includes a transistor N 3 , a transistor N 4 , a transistor N 5 and a transistor P 2 . The transistor N 3 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor N 3 receives the second voltage V 2 (i.e., the working voltage 1.8V). The second terminal of the transistor N 3 is coupled to the pad 110 . The fourth terminal of the transistor N 3 receives the first voltage V 1 (i.e., the grounding voltage).

The transistor N 4 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal and the second terminal of the transistor N 4 are coupled to the third terminal of the transistor N 3 . The third terminal of the transistor N 4 generates the first control signal CS 1 . The fourth terminal of the transistor N 4 receives the first voltage V 1 (i.e., the grounding voltage GND).

The transistor N 5 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor N 5 receives the second voltage V 2 (i.e., the working voltage 1.8V). The second terminal of the transistor N 5 is coupled to the third terminal of the transistor N 4 . The third terminal of the transistor N 5 is coupled to the pull-down unit 120 and receives the pull-down voltage VD. The fourth terminal of the transistor N 5 receives the first voltage V 1 (i.e., the grounding voltage GND).

The transistor P 2 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor P 2 receives the second voltage V 2 (i.e., the working voltage 1.8V). The second terminal of the transistor P 2 is coupled to the second terminal of the transistor N 5 . The third terminal of the transistor P 2 is coupled to the pad 110 . The fourth terminal of the transistor P 2 receives the second control signal CS 2 .

In the embodiment, the transistors N 3 , N 4 and N 5 are, for example, N-type transistors. The first terminal of the transistors N 3 , N 4 or N 5 is, for example, a gate terminal of the N-type transistor. The second terminal of the transistors N 3 , N 4 or N 5 is, for example, a drain terminal of the N-type transistor. The third terminal of the transistors N 3 , N 4 or N 5 is, for example, a source terminal of the N-type transistor. The fourth terminal of the transistors N 3 , N 4 or N 5 is, for example, a base terminal of the N-type transistor.

In addition, the transistor P 2 is, for example, a P-type transistor. The first terminal of the transistor P 2 is, for example, a gate terminal of the P-type transistor. The second terminal of the transistor P 2 is, for example, a drain terminal of the P-type transistor. The third terminal of the transistor P 2 is, for example, a source terminal of the P-type transistor. The fourth terminal of the transistor P 2 is, for example, a base terminal of the P-type transistor.

The second control unit 140 includes a transistor P 3 and a transistor P 4 . The transistor P 3 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor P 3 receives the first control signal CS 1 . The second terminal and the fourth terminal of the transistor P 3 are coupled to each other and generate the second control signal CS 2 . The third terminal of the transistor P 3 receives the second voltage V 2 (i.e., the working voltage 1.8V).

The transistor P 4 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor P 4 receives the second voltage V 2 (i.e., the working voltage 1.8V). The second terminal and the fourth terminal of the transistor P 4 are coupled to the second terminal of the transistor P 3 . The third terminal of the transistor P 4 is coupled to the pad 110 .

In addition, the transistors P 3 and P 4 are, for example, P-type transistors. The first terminal of the transistors P 3 or P 4 is, for example, a gate terminal of the P-type transistor. The second terminal of the transistors P 3 or P 4 is, for example, a drain terminal of the P-type transistor. The third terminal of the transistors P 3 or P 4 is, for example, a source terminal of the P-type transistor. The fourth terminal of the transistors P 3 or P 4 is, for example, a base terminal of the P-type transistor.

The voltage regulation unit 150 includes a transistor P 5 and a transistor N 6 . The transistor P 5 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor P 5 receives the first control signal CS 1 . The second terminal of the transistor P 5 generates the output voltage VOUT. The third terminal of the transistor P 5 is coupled to the pad 110 and receives the input voltage VIN. The fourth terminal of the transistor P 5 receives the second control signal CS 2 .

The transistor N 6 has a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the transistor N 6 receives the second control signal CS 2 . The second terminal of the transistor N 6 is coupled to the second terminal of the transistor P 5 . The third terminal of the transistor N 6 is coupled to the third terminal of the transistor P 5 . The fourth terminal of the transistor N 6 receives the first voltage V 1 (i.e., the grounding voltage GND).

In the embodiment, the transistor P 5 is, for example, a P-type transistor. The first terminal of the transistor P 5 is, for example, a gate terminal of the P-type transistor. The second terminal of the transistor P 5 is, for example, a drain terminal of the P-type transistor. The third terminal of the transistor P 5 is, for example, a source terminal of the P-type transistor. The fourth terminal of the transistor P 5 is, for example, a base terminal of the P-type transistor.

In addition, the transistor N 6 is, for example, an N-type transistor. The first terminal of the transistor N 6 is, for example, a gate terminal of the N-type transistor. The second terminal of the transistor N 6 is, for example, a drain terminal of the N-type transistor. The third terminal of the transistor N 6 is, for example, a source terminal of the N-type transistor. The fourth terminal of the transistor N 6 is, for example, a base terminal of the N-type transistor.

Furthermore, in the embodiment, the thicknesses of the process parameters used in the transistors N 1 to N 6 and P 1 to P 5 are larger than the thicknesses of the process parameters of the general transistors, and thus threshold voltages (Vth) of the transistors N 1 to N 6 and P 1 to P 5 are larger. In addition, the transistors N 1 to N 6 and P 1 to P 5 are, for example, transistors capable of operating at 5V.

The internal components and the arrangement relationship thereof of the voltage adjustment circuit 100 have been described above, and the operation of the voltage adjustment circuit 100 will be described below by way of some embodiments.

FIG. 3 shows a schematic view of an operation of a voltage regulation circuit according to an embodiment of the present invention. It is assumed that the input voltage VIN is 0V, i.e., the input voltage VIN is less than the predetermined value.

Firstly, since the input voltage VIN is 0V, the transistor P 1 of the inverter 210 is turned on and the transistor N 2 of the inverter 210 is turned off, and the inversion signal outputted by the output terminal of the inverter 210 is the second voltage V 2 (i.e., the working voltage 1.8V). Since the inversion signal is the second voltage V 2 (i.e., the working voltage 1.8V), the transistor N 1 is turned on, the pull-down voltage VD generated by the second terminal of the transistor N 1 is the first voltage V 1 (i.e., the grounding voltage GND). That is, the pull-down unit 120 generates the pull-down voltage VD with the first voltage V 1 .

In addition, since the input voltage VIN is 0V, the transistor N 3 is turned on, and the transistor N 4 and the transistor P 2 are turned off. Since the first terminal (such as the gate terminal) of the transistor N 5 receives the second voltage V 2 (i.e., the working voltage 1.8V) and the third terminal (such as the source terminal) of the transistor N 5 receives the pull-down voltage VD with the first voltage V 1 , the transistor N 5 is turned on, and the first control signal CS 1 generated by the second terminal of the transistor N 5 is the first voltage V 1 (i.e., the grounding voltage GND). That is, the first control unit 130 generates the first control signal CS 1 with the first voltage V 1 .

Since the first terminal (such as the gate terminal) of the transistor P 3 receives the first control signal CS 1 with the first voltage V 1 and the third terminal (such as the source terminal) of the transistor P 3 receives the second voltage V 2 (i.e., the working voltage 1.8V), the transistor P 3 is turned on, and the second control signal CS 2 generated by the second terminal (such as the drain terminal) of the transistor P 3 is the second voltage V 2 (i.e., the working voltage 1.8V). That is, the second control unit 140 generates the second control signal CS 2 with the second voltage V 2 (i.e., the working voltage 1.8V). Since the first terminal (such as the gate terminal) of the transistor P 4 receives the second voltage V 2 (i.e., the working voltage 1.8V) and the third terminal (such as the source terminal) of the transistor P 4 receives the input voltage VIN with 0V, the transistor P 4 is turned off.

Then, since the first control signal CS 1 is the first voltage V 1 (i.e., the grounding voltage GND) and the second control signal CS 2 is the second voltage V 2 (i.e., the working voltage 1.8V), the transistor P 5 and the transistor N 6 are turned on, and the voltage regulation unit 150 uses the input voltage VIN with 0V as the output voltage VOUT and provides the output voltage VOUT with 0V to the core circuit 160 .

FIG. 4 shows a schematic view of an operation of a voltage regulation circuit according to another embodiment of the present invention. It is assumed that the input voltage is 1.8V, i.e., the input voltage VIN equals to the predetermined value.

Firstly, since the input voltage VIN is 1.8V, the transistor P 1 of the inverter 210 is turned off and the transistor N 2 of the inverter 210 is turned on, and the inversion signal outputted by the output terminal of the inverter 210 is the first voltage V 1 (i.e., the grounding voltage GND). Since the inversion signal is the first voltage V 1 (i.e., the grounding voltage GND), the transistor N 1 is turned off, and the pull-down unit 120 does not generate the pull-down voltage VD.

In addition, since the input voltage VIN is 1.8V, the transistor N 3 and the transistor N 4 are turned on, and the transistor P 2 is turned off. Since transistor N 3 and the transistor N 4 are turned on, the first control signal CS 1 generated by the third terminal (such as the source terminal) of the transistor N 4 is 1.8-2Vth, wherein “2Vth” is the threshold voltages of the transistor N 3 and the transistor N 4 .

Since the first terminal (such as the gate terminal) of the transistor P 3 receives the first control signal CS 1 with (1.8-2Vth) and the third terminal (such as the source terminal) receives the second voltage V 2 (i.e., the working voltage 1.8V), the transistor P 3 is turned on, and the second control signal CS 2 generated by the second terminal (such as the drain terminal) of the transistor P 3 is the second voltage V 2 (i.e., the working voltage 1.8V). That is, the second control unit 140 generates the second control signal CS 2 with the second voltage V 2 (i.e., the working voltage 1.8V). Since the first terminal (such as the gate terminal) of the transistor P 4 receives the second working voltage V 2 (i.e., the working voltage 1.8V) and the third terminal (such as the source terminal) of the transistor P 4 receives the input voltage VIN with 1.8V, the transistor P 4 is turned off

Then, since the first control signal CS 1 is (1.8-2Vth) and the second control signal CS 2 is the second voltage V 2 (i.e., the working voltage 1.8V), the transistor P 5 and the transistor N 6 are turned on, and the voltage regulation unit 150 starts to generate the output voltage VOUT. When the transistor P 5 and the transistor N 6 are turned on, the output voltage VOUT are simultaneously provided by the transistor P 5 and the transistor N 6 .

Then, when the output voltage VOUT reaches 1.8-Vth, the transistor N 6 is turned off and the transistor P 5 is still turned on, so that the output voltage VOUT is still provided by the transistor P 5 until the output voltage VOUT reaches the same voltage level as the voltage level of the input voltage VIN with 1.8V. That is, the voltage regulation unit 150 may provide the same output voltage VOUT (i.e., 1.8V) as the voltage level of the input voltage VIN and provide the output voltage VOUT to the core circuit 160 .

FIG. 5 shows a schematic view of an operation of a voltage regulation circuit according to another embodiment of the present invention. It is assumed that the input voltage VIN is 3.3V, i.e., the input voltage VIN is greater than the predetermined value.

Firstly, since the input voltage VIN is 3.3V, the transistor P 1 of the inverter 210 is turned off and the transistor N 2 of the inverter 210 is turned on, and the inversion signal outputted by the output terminal of the inverter 210 is the first voltage V 1 (i.e., the grounding voltage GND). Since the inversion signal is the first voltage V 1 (i.e., the grounding voltage GND), the transistor N 1 is turned off, and the pull-down unit 120 does not generate the pull-down voltage VD.

In addition, since the input voltage VIN is 3.3V, the transistor P 2 is turned on, and the first control signal CS 1 generated by the transistor P 2 is 3.3V. Since the input voltage VIN is 3.3V and the first control signal CS 1 is 3.3V, the transistor N 3 and the transistor N 4 are turned off

Since the first terminal (such as the gate terminal) of the transistor P 3 receives the first control signal CS 1 with 3.3V and the third terminal (such as the source terminal) of the transistor P 3 receives the second voltage V 2 (i.e., the working voltage 1.8V), the transistor P 3 is turned off. Since the first terminal (such as the gate terminal) of the transistor P 4 receives the second voltage V 2 (i.e., the working voltage 1.8V) and the third terminal (such as the source terminal) of the transistor P 4 receives the input voltage VIN with 3.3V, the transistor P 4 is turned on, and the second control signal CS 2 generated by the second terminal (such as the drain terminal) of the transistor P 4 is the input voltage VIN with 3.3V. That is, the second control unit 140 generates the second control signal CS 2 with 3.3V.

Then, since the first control signal CS 1 is 3.3V and the second control signal CS 2 is 3.3V, the transistor P 5 is turned off and the transistor N 6 is turned on, the voltage regulation unit 150 may decrease the voltage level of the input voltage VIN with 3.3V through the threshold voltage of the transistor N 6 , such as 3.3V-Vth. Then, the voltage regulation unit 150 uses the regulated voltage level (i.e., 3.3V-Vth) as the output voltage VOUT. In the embodiment, Vth is the threshold voltage of the transistor N 6 .

The output voltage VOUT generated by the voltage regulation unit 150 is, for example, the same as the predetermined value, and the output voltage VOUT is provided to the core circuit 160 . Therefore, the voltage regulation circuit 100 may avoid situations wherein the unsuitable output voltage VOUT is provided to the core circuit 160 , which may result in abnormal operation or damage to the core circuit 160 , and increase the security and stability of the operation of the circuit.

In summary, according to the voltage regulation circuit disclosed by the embodiment of the present invention, the pull-down unit generates the pull-down voltage according to the input voltage. The first control unit generates the first control signal according to the input voltage and the pull-down voltage. The second control unit generates the second control signal according to the input voltage and the first control signal. The voltage regulation unit regulates the input voltage according to the first control signal and the second control signal, so as to generate the output voltage. Therefore, the embodiment of the present invention may effectively avoid situations wherein the unsuitable output voltage is provided to the core circuit, which may result in abnormal operation or damage to the core circuit, and increase the security and stability of the operation of the circuit.

While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.