Bridgeless power factor correction converter with zero current detection circuit

The present invention relates generally to electronic circuits, and, more particularly, to a bridgeless power factor correction converter.

A power factor of an electrical circuit is determined using a ratio of real power to apparent power, where the real power is associated with a load of the electrical circuit, and the apparent power is the power supplied to the electrical circuit. The power factor is indicative of the efficiency of the circuit. An efficient circuit will have a power factor in the range of 0.8-1, where 1 is ideal.

Today's power supplies often include a power factor correction (PFC) converter in order to improve the efficiency of the power supply. One example of a PFC circuit is a critical conduction mode (CRM) totem-pole bridgeless PFC circuit. This circuit includes a zero-current detection (ZCD) circuit and a bridgeless PFC converter. The bridgeless PFC converter includes transistors in a totem-pole arrangement and an inductor. A power factor close to unity is achieved by carefully controlling the switching of the transistors. The transistors are switched based on a detection of a zero-current state across the inductor by the ZCD circuit.

The ZCD circuit uses auxiliary windings to detect the zero-current state based on a voltage induced in the auxiliary windings. However, the induced voltage is bipolar, so a rectification circuit is needed to detect the induced bipolar voltage. A sampling circuit also is required to sample voltages used for detecting the zero-current state. The sampling circuit and the rectification circuit increase the area required by the ZCD circuit and thus by the bridgeless PFC system.

Other implementations of the ZCD circuit include current transformer (CT) sensors that detect the zero-current state. However, using multiple CT sensors increases area as well as power consumption. In addition, other bridgeless PFC systems may include additional hardware circuitry or use software-based methods for controlling the bridgeless PFC converter. However, accuracy issues are prevalent. Thus, there is still is room for improvement in CRM bridgeless PFC systems.

The following detailed description of the preferred embodiments of the present invention will be better understood when read in conjunction with the appended drawings. The present invention is illustrated by way of example, and not limited by the accompanying figures, in which like references indicate similar elements.

FIG. 1 is a schematic block diagram of a critical conduction mode (CRM) bridgeless power factor correction (PFC) system in accordance with an embodiment of the present invention;

FIG. 2 is a schematic circuit diagram of a bridgeless PFC converter of the CRM bridgeless PFC system of FIG. 1 in accordance with an embodiment of the present invention;

FIG. 3A is a schematic circuit diagram of a zero-current detection (ZCD) circuit of the CRM bridgeless PFC system of FIG. 1 in accordance with an embodiment of the present invention;

FIG. 3B is a timing diagram illustrating an operation of the ZCD circuit of FIG. 3A in positive and negative half-cycles of a supply voltage in accordance with an embodiment of the present invention;

FIG. 4 is a schematic circuit diagram of a zero-voltage switching (ZVS) detection circuit of the CRM bridgeless PFC system of FIG. 1 in accordance with an embodiment of the present invention;

FIG. 5 is a flow chart illustrating an operation of a processor of the CRM bridgeless PFC system of FIG. 1 in accordance with an embodiment of the present invention; and

FIG. 6 is a timing diagram illustrating an operation of the CRM bridgeless PFC system in the positive half-cycle in accordance with an embodiment of the present invention.

The detailed description of the appended drawings is intended as a description of the currently preferred embodiments of the present invention and is not intended to represent the only form in which the present invention may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the present invention.

For purposes of this description, the terms “couple,” “coupling,” “coupled,” “connect,” “connecting,” or “connected” refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. The terms “directly coupled,” “directly connected,” etc., imply that the connected elements are either contiguous or connected via a conductor for the transmission of electrical signals.

In an embodiment, the present invention provides a critical conduction mode (CRM) bridgeless power factor correction (PFC) system that includes a bridgeless PFC converter, a zero-current detection (ZCD) circuit, a zero-voltage switching (ZVS) detection circuit, and a processor. The bridgeless PFC converter receives a supply voltage and outputs first and second voltages. The ZCD circuit is connected to the bridgeless PFC converter and includes first and second voltage divider circuits, first and second comparators, and a selecting circuit. The first voltage divider circuit receives the supply voltage and outputs a third voltage. The second voltage divider circuit is connected to the bridgeless PFC converter for receiving the first voltage, and outputting a fourth voltage. The first and second comparators are connected to the first and second voltage divider circuits for receiving the third and fourth voltages, and outputting first and second comparison signals, respectively. The selecting circuit is connected to the first and second comparators for receiving the first and second comparison signals, respectively, and outputting a ZCD signal. The ZCD signal is indicative of a zero-current state of the bridgeless PFC converter. The ZVS detection circuit is connected to the bridgeless PFC converter for receiving the first and second voltages, and the ZCD circuit for receiving the ZCD signal. The ZVS detection circuit outputs a ZVS flag signal. The processor is connected to the ZCD circuit and the ZVS detection circuit for receiving the ZCD signal and the ZVS flag signal, respectively, and the bridgeless PFC converter for receiving the first and second voltages, and outputting a set of control signals for controlling the bridgeless PFC converter.

In another embodiment, the present invention provides a ZCD circuit for a PFC converter. The ZCD circuit includes first and second voltage divider circuits, first and second comparators, and a selecting circuit. The first voltage divider circuit receives a supply voltage and outputs a first voltage. The second voltage divider circuit is connected to a bridgeless PFC converter for receiving a second voltage, and outputting a third voltage. The first and second comparators are connected to the first and second voltage divider circuits for receiving the first and third voltages, and outputting first and second comparison signals, respectively. The selecting circuit is connected to the first and second comparators for receiving the first and second comparison signals and outputting a ZCD signal. The ZCD signal is indicative of a zero-current state of the bridgeless PFC converter.

Various embodiments of the present invention provide a CRM bridgeless PFC system. The CRM bridgeless PFC system includes a ZCD circuit for detecting a zero-current state of a bridgeless PFC converter of the CRM bridgeless PFC system. The PFC converter outputs first and second voltages. The ZCD circuit is connected to the bridgeless PFC converter and an AC source for receiving the first voltage and a supply voltage, respectively. The ZCD circuit outputs a ZCD signal based on the first voltage and the supply voltage. The ZCD signal also is used by a ZVS detection circuit for generating a ZVS flag signal FS. A processor receives the supply voltage, the first and second voltages, the ZCD signal, and the ZVS flag signal and generates a set of control signals that are used to control the PFC converter.

The CRM bridgeless PFC system eliminates the need for implementing additional hardware (such as rectification circuitry, sampling circuitry, and multiple CT sensors) to detect the zero-current state, thereby reducing the area required by the ZCD circuit. The space occupied by the PFC system, the cost of the PFC system, and the power consumed by the PFC system all are improved compared to conventional CRM bridgeless PFC systems. Further, the ZCD signal acts as a timing control signal for the generation of the ZVS flag signal in real-time. Thus, the accuracy and reliability of controlling the PFC system is improved as compared to conventional bridgeless PFC systems.

Referring now to FIG. 1 , a block diagram of a CRM bridgeless PFC system 100 in accordance with an embodiment of the present invention is shown. The PFC system 100 includes an AC (Alternating Current) source 102 , a bridgeless PFC converter 104 , a polarity detection circuit 106 , a zero-current detection (ZCD) circuit 108 , a zero-voltage switching (ZVS) detection circuit 110 , and a processor 112 . The AC source 102 outputs an AC voltage, i.e., a supply voltage VS.

The PFC converter 104 is connected to the AC source 102 for receiving the supply voltage VS. The PFC converter 104 also receives first through fourth control signals CL 1 -CL 4 (hereinafter referred to as a “set of control signals CL 1 -CL 4 ”) from the processor 112 . The PFC converter 104 converts the supply voltage VS to first and second DC (Direct Current) output voltages V 1 and V 2 .

The polarity detection circuit 106 is connected to the AC source 102 for receiving the supply voltage VS. The polarity detection circuit 106 outputs a polarity signal POL that indicates positive or negative half-cycles of the supply voltage VS. In one embodiment, during the positive and negative half-cycles, the polarity detection circuit 106 generates the polarity signal POL at logic high and logic low states, respectively. In another embodiment, during the positive and negative half-cycles, the polarity detection circuit 106 generates the polarity signal POL at logic low and logic high states, respectively.

The ZCD circuit 108 is connected to the AC source 102 , the bridgeless PFC converter 104 , and the polarity detection circuit 106 for receiving the supply voltage VS, the first voltage V 1 , and the polarity signal POL, respectively. The ZCD circuit 108 outputs a ZCD signal ZCDS that indicates a zero-current state of the PFC converter 104 . During the positive half-cycle, the ZCD signal ZCDS is activated when the first voltage V 1 is less than the supply voltage VS. During the negative half-cycle, the ZCD signal ZCDS is activated when the first voltage V 1 is greater than the supply voltage VS.

The ZVS detection circuit 110 is connected to the bridgeless PFC converter 104 , the polarity detection circuit 106 , and the ZCD circuit 108 for receiving the first and second voltages V 1 and V 2 , the polarity signal POL, and the ZCD signal ZCDS, respectively. The ZVS detection circuit 110 further receives a delay signal DS from the processor 112 . The ZVS detection circuit 110 outputs a ZVS flag signal FS. During the positive half-cycle, the ZVS flag signal FS is activated (i.e., the ZVS flag signal FS is at a logic high state) when the ZCD signal ZCDS is activated and the first voltage V 1 is less than a first threshold voltage Vth 1 (shown in FIG. 6 ). The processor 112 determines a value of the first threshold voltage Vth 1 , which is used for determining whether an ideal switching condition for valley switching of the first and second control signals CL 1 and CL 2 has been achieved. During the negative half-cycle, the ZVS flag signal FS is activated when the ZCD signal ZCDS is activated and the first voltage V 1 is greater than the second voltage V 2 .

The processor 112 is connected to the ZVS detection circuit 110 for receiving the ZVS flag signal FS. The processor 112 also is connected to the AC source 102 , the PFC converter 104 , the polarity detection circuit 106 , and the ZCD circuit 108 for receiving the supply voltage VS, the first and second voltages V 1 and V 2 , the polarity signal POL, and the ZCD signal ZCDS, respectively. The processor 112 generates the set of control signals CL 1 -CL 4 , which are used to control the PFC converter 104 . The processor 112 also generates the delay signal DS, which is used to control the ZVS detection circuit 110 .

Referring now to FIG. 2 , a circuit diagram of the PFC converter 104 in accordance with an embodiment of the present invention is shown. The bridgeless PFC converter 104 includes an inductor 202 , and first and second bridge arms 204 and 206 which are connected in parallel.

The inductor 202 has a first terminal connected to the AC source 102 for receiving the supply voltage VS and a second terminal that outputs the first voltage V 1 .

The first bridge arm 204 includes first and second switches 207 a and 207 b connected in series with a first node N 1 between the switches 207 a and 207 b . The first and second switches 207 a and 207 b include first and second series connected transistors 208 a and 208 b . The second terminal of the inductor 202 also is connected to the first node N 1 . The first switch 207 a further includes a first body diode 210 a and a first body capacitor 212 a . Similarly, the second switch 207 b includes a second body diode 210 b and a second body capacitor 212 b . The first body diode 210 a and the first body capacitor 212 a are coupled in parallel to the first transistor 208 a . Similarly, the second body diode 210 b and the second body capacitor 212 b are coupled in parallel to the second transistor 208 b.

The second bridge arm 206 includes third and fourth series connected switches 213 a and 213 b , and there is a second node N 2 located between the switches 213 a and 213 b . The first and second switches 213 a and 213 b include third and fourth transistors 214 a and 214 b , respectively, that are connected in series. The AC source 102 also is connected to the second node N 2 . The third and fourth transistors 214 a and 214 b are connected to the first and second transistors 208 a and 208 b at third and fourth nodes N 3 and N 4 , respectively. The third node N 3 also is connected to ground. The third and fourth switches 213 a and 213 b include third and fourth body diodes 216 a and 216 b , respectively. The third and fourth body diodes 216 a and 216 b are coupled in parallel to the third and fourth transistors 214 a and 214 b , respectively.

The PFC converter 104 further includes a first capacitor 218 and a load 220 that each are connected between the third and fourth nodes N 3 and N 4 such that they are connected in parallel with the first and second bridge arms 204 and 206 .

The first transistor 208 a has first and second terminals connected to the first and third nodes N 1 and N 3 , respectively. During the positive half-cycle, the first and second terminals of the first transistor 208 a are drain and source terminals, respectively, while during the negative half-cycle, the first and second terminals are source and drain terminals, respectively. The first transistor 208 a further has a gate terminal connected to the processor 112 for receiving the first control signal CL 1 . The second transistor 208 b has first and second terminals connected to the first and fourth nodes N 1 and N 4 , respectively. During the positive half-cycle, the first and second terminals of the second transistor 208 b are drain and source terminals, respectively, and during the negative half-cycle, the first and second terminals of the second transistor 208 b are source and drain terminals, respectively. The gate of the second transistor 208 b is connected to the processor 112 for receiving the second control signal CL 2 .

The third transistor 214 a has first and second terminals connected to the second and third nodes N 2 and N 3 , respectively. During the positive half-cycle, the first and second terminals are drain and source terminals, respectively, and during the negative half-cycle, the first and second terminals are source and drain terminals, respectively. The gate of the third transistor 214 a is connected to the processor 112 for receiving the third control signal CL 3 . The fourth transistor 214 b has first and second terminals connected to the second and fourth nodes N 2 and N 4 , respectively. During the positive half-cycle, the first and second terminals are drain and source terminals, respectively, and during the negative half-cycle, the first and second terminals are source and drain terminals, respectively. The gate of the fourth transistor 214 b is connected to the processor 112 for receiving the fourth control signal CL 4 .

The first through fourth transistors 208 a , 208 b , 214 a and 214 b are controlled by the set of control signals CL 1 -CL 4 . In one embodiment, the first through fourth transistors 208 a , 208 b , 214 a , and 214 b are activated when the set of control signals CL 1 -CL 4 are activated, respectively. In another embodiment, the first through fourth transistors 208 a , 208 b , 214 a , and 214 b are activated when the set of control signals CL 1 -CL 4 are deactivated, respectively.

The first transistor 208 a functions as an active switch and a free-wheeling switch in the positive and negative half-cycles, respectively, and the second transistor 208 b functions as a free-wheeling switch and an active switch in the positive and negative half-cycles, respectively. In one embodiment, the first and second transistors 208 a and 208 b are gallium nitride (GaN) high electron mobility transistors (HEMT) and the third and fourth transistors 214 a and 214 b are silicon transistors. During the positive half-cycle of VS, the first and third transistors 208 a and 214 a are activated and the second and fourth transistors 208 b and 214 b are deactivated when the inductor 202 is charging, and the second and third transistors 208 b and 214 a are activated and the first and fourth transistors 208 a and 214 b are deactivated when the inductor 202 is discharging. Further, during the negative half-cycle, the second and fourth transistors 208 b and 214 b are activated and the first and third transistors 208 a and 214 a are deactivated when the inductor 202 is charging, and the first and fourth transistors 208 a and 214 b are activated and the second and third transistors 208 b and 214 a are deactivated when the inductor 202 is discharging.

Referring now to FIG. 3A , a circuit diagram of the ZCD circuit 108 in accordance with an embodiment of the present invention is shown. The ZCD circuit 108 includes first and second voltage divider circuits 302 a and 302 b , first and second comparators 304 a and 304 b , and a first selecting circuit 306 .

The first voltage divider circuit 302 a includes first through third series connected resistors 308 a - 308 c . The first resistor 308 a has a first terminal connected to the AC source 102 for receiving the supply voltage VS. The second resistor 308 b is connected between the first and third resistors 308 a and 308 c , and the third resistor 308 c is connected between the second resistor 308 b and ground. There is a first voltage tap between the second and third resistors 308 b and 308 c . A second capacitor 310 is connected in parallel to the third resistor 308 c . The first voltage divider circuit 302 a outputs a third voltage V 3 at the first voltage tap.

The second voltage divider circuit 302 b includes fourth through sixth resistors 312 a - 312 c that are connected in series between the first node (where the first voltage V 1 is generated) and ground. More particularly, the fourth resistor 312 a has a first terminal connected to the second terminal of the inductor 202 for receiving the first voltage V 1 . The fifth resistor 312 b is connected between the fourth and sixth resistors 312 a and 312 c , and the sixth resistor 312 c is connected between the fifth resistor 312 b and ground. A fourth voltage V 4 is output from a second voltage tap located between the fifth and sixth resistors 312 b and 312 c . A third capacitor 314 is connected in parallel with the sixth resistor 312 c.

Noninverting and inverting (positive and negative) input terminals of the first comparator 304 a receive the third and fourth voltages V 3 and V 4 from the first and second taps of the first and second voltage dividers 302 a and 302 b . The first comparator 304 a outputs a first comparison signal Vc 1 . In one embodiment, the first comparator 304 a outputs the first comparison signal Vc 1 at logic low and high states when the fourth voltage V 4 is greater and less than the third voltage V 3 , respectively.

Noninverting and inverting (positive and negative) Noninverting and inverting (positive and negative) input terminals of the second comparator 304 b receive the fourth and third voltages V 4 and V 3 , respectively. The second comparator 304 b outputs a second comparison signal Vc 2 . In one embodiment, the second comparison signal Vc 2 is high when the fourth voltage V 4 is greater than the third voltage V 3 , and Vc 2 is low when the V 4 is less than V 3 .

The first selecting circuit 306 includes first and second switches 316 a and 316 b having first terminals that are connected to the output terminals of the first and second comparators 304 a and 304 b for receiving the first and second comparison signals Vc 1 and Vc 2 , respectively.

The ZCD circuit 108 further includes a first logic gate 318 that is connected to the polarity detection circuit 106 for receiving the polarity signal POL and generating/POL. In one embodiment, the first logic gate 318 is a NOT gate. The first logic gate 318 thus outputs an inverted version of the polarity signal IPOL (hereinafter referred to simply as “IPOL”). The first and second switches 316 a and 316 b have control terminals that are connected to the polarity detection circuit 106 and the first logic gate 318 for receiving POL and IPOL, respectively, for controlling a switching operation of the first and second switches 316 a and 316 b . Thus, the first and second switches 316 a and 316 b are activated in the positive and negative half-cycles, respectively. Second terminals of the first and second switches 316 a and 316 b are connected together and the ZCD signal is provided for outputting the ZCD signal at such connection. When the first and second switches 316 a and 316 b are activated during the positive and negative half-cycles, the first selecting circuit 306 outputs the ZCD signal ZCDS as the first and second comparison signals Vc 1 and Vc 2 , respectively.

Referring now to FIG. 3B , a timing diagram 300 illustrating the generation of the ZCD signal ZCDS in the positive and negative half-cycles in accordance with an embodiment of the present invention is shown.

During the positive half-cycle, the polarity detection circuit 106 outputs the polarity signal POL at a logic high state. Further, the processor 112 activates the third control signal CL 3 and deactivates the fourth control signal CL 4 . Thus, the third transistor 214 a is activated and the fourth transistor 214 b is deactivated. Further, the first transistor 208 a functions as an active switch and the second transistor 208 b functions as a free-wheeling switch. The inductor current IL passes through the first transistor 208 a , the third transistor 214 a and the inductor 202 when the inductor 202 is charging, and the second transistor 208 b , the first capacitor 218 , the load 220 , the third transistor 214 a , and the inductor 202 when the inductor 202 is discharging.

At time T 0 , the inductor current IL is at a zero-current value. The first control signal CL 1 is activated and the second control signal CL 2 is deactivated. Thus, the first transistor 208 a is activated and the second transistor 208 b is deactivated. Further, the first voltage V 1 is at a zero-voltage level and the supply voltage VS is greater than the first voltage V 1 . Hence, the ZCD circuit 108 asserts the ZCD signal ZCDS.

During time period T 0 -T 1 , the first and second control signals CL 1 and CL 2 remain unchanged. Thus, the inductor 202 charges and the inductor current IL rises from a zero-current value to a first peak value of the inductor current IL. Further, the first voltage V 1 remains unchanged at a zero-voltage level and hence the ZCD signal ZCDS remains unchanged at a logic high state.

At time T 1 , the inductor current IL is at the first peak value. The first control signal CL 1 transitions from an active state to an inactive state. Thus, the first transistor 208 a is deactivated. Further, the second control signal CL 2 remains unchanged. The first voltage V 1 rises rapidly from a zero-voltage level to a first voltage level, which is at a voltage level of the second voltage V 2 and is greater than the supply voltage VS. Hence, the ZCD signal ZCDS transitions from high to low.

During time period T 1 -T 2 , the first and second control signals CL 1 and CL 2 remain unchanged. Thus, the first and second transistors 208 a and 208 b remain deactivated. As a result, the inductor 202 starts discharging by way of the second body diode 210 b and the inductor current IL starts falling from the first peak value to a first inductor current IL value. Further, the first voltage V 1 remains unchanged, i.e., remains greater than the supply voltage VS. Thus, the ZCD signal ZCDS stays low.

At time T 2 , the inductor current IL is at the first inductor current IL value. The first control signal CL 1 remains unchanged. The second control signal CL 2 transitions from an inactive state to an active state. Thus, the second transistor 208 b is activated after a first dead time (i.e., time period T 1 -T 2 ) to avoid shorting of the fourth node N 4 and ground by having the first and second transistors 208 a and 208 b activated at the same time. Further, the first voltage V 1 remains unchanged, and hence the ZCD signal ZCDS stays low.

During time period T 2 -T 3 , the inductor current IL continues dropping until it reaches a zero-current value. The first and second control signals CL 1 and CL 2 remain unchanged. The first voltage V 1 remains unchanged, and hence the ZCD signal ZCDS stays low.

At time T 3 , the inductor current IL reaches the zero-current value. The first control signal CL 1 remains unchanged. The second control signal CL 2 transitions from an active state to an inactive state. Thus, the second transistor 208 b is deactivated. The inductor 202 and the first and second body capacitors 212 a and 212 b start resonating. The first voltage V 1 remains unchanged, i.e., remains greater than the supply voltage VS, and hence the ZCD signal ZCDS stays low.

During time period T 3 -T 4 , the first and second transistors 208 a and 208 b are deactivated as the first and second control signals CL 1 and CL 2 remain unchanged. Thus, a reverse current flows through the inductor 202 , i.e., the inductor current IL falls below the zero-current value to reach a second peak value of the inductor current IL, and then starts rising. As a result, the first voltage V 1 starts falling to a voltage level of the supply voltage VS. The ZCD signal ZCDS remains unchanged at a logic low state.

At time T 4 , the first and second control signals CL 1 and CL 2 remain unchanged. Thus, the inductor 202 , and the first and second body capacitors 212 a and 212 b remain in resonance. The inductor current IL is greater than the second peak value and the first voltage V 1 is less than the supply voltage VS. Thus, the ZCD signal ZCDS transitions from low to high.

During time period T 4 -T 5 , the first and second control signals CL 1 and CL 2 remain unchanged. Hence, the inductor 202 , and the first and second body capacitors 212 a and 212 b remain in resonance. The inductor current IL continues rising from the second peak value to the zero-current value. Further, the first voltage V 1 starts falling below the supply voltage VS to reach a second voltage level. The ZCD signal ZCDS stays high.

At time T 5 , the inductor current IL reaches the zero-current value and the first control signal CL 1 transitions from an inactive state to an active state. Thus, the first transistor 208 a is activated after a second dead time (i.e., time period T 3 -T 5 ) to allow the inductor current IL to reach the zero-current value. The second control signal CL 2 remains unchanged. Further, the first voltage V 1 reaches the zero-voltage level from the second voltage level. The ZCD signal ZCDS remains unchanged at a logic high state.

The time period T 0 -T 5 represents a first switch cycle. Further, the processor 112 determines an on-time (i.e. duration of time period T 2 -T 3 ), of the second transistor 208 b as explained in FIGS. 5 and 6 hereinafter. It will be apparent to a person skilled in the art that the positive half-cycle may have multiple switch cycles that are similar to the first switch cycle. For example, the time period T 5 -T 10 may represent a second switch cycle where the first and second control signals CL 1 and CL 2 , the ZCD signal ZCDS, the inductor current IL, and the first voltage V 1 transition in a manner similar to the transitions in the first switch cycle. Further, one switch cycle of the positive and negative half-cycles corresponds to the charging and the subsequent discharging of the inductor 202 .

During the negative half-cycle (i.e., time period T 11 -T 19 ), the polarity detection circuit 106 outputs the polarity signal POL at a logic low state. Further, the processor 112 outputs the third and fourth control signals CL 3 and CL 4 at logic low and high states, respectively. Thus, the third transistor 214 a is deactivated and the fourth transistor 214 b is activated. Further, the second transistor 208 b functions as the active switch and the first transistor 208 a functions as the free-wheeling switch. It will be apparent to a person skilled in the art that the processor 112 controls the transitions of the first and second control signals CL 1 and CL 2 in the negative half-cycle in a manner similar to the transitions of the second and first control signals CL 2 and CL 1 in the positive half-cycle, respectively.

During the negative half-cycle, the operation of the bridgeless PFC system 100 is similar to the operation of the bridgeless PFC system 100 in the positive half-cycle. Further, a polarity of the inductor current IL is reversed and the inductor current IL reaches a third peak value at time T 12 . Further, the inductor current IL passes through the fourth transistor 214 b , the second transistor 208 b and the inductor 202 when the inductor 202 is charging, and the fourth transistor 214 b , the first capacitor 218 , the load 220 , the first transistor 208 a , and the inductor 202 when the inductor 202 is discharging. The ZCD circuit 108 outputs the ZCD signal ZCDS at logic high and low states when the first voltage V 1 is greater and less than the supply voltage VS, respectively. Further, the rise of the first voltage V 1 from a zero-voltage level to the second voltage level from time instants T 14 -T 16 is in a manner similar to the fall of the first voltage V 1 from the first voltage level to the second voltage level. It will be understood by those of skill in the art that the first voltage V 1 remains greater than the supply voltage VS when the second control signal CL 2 remains activated, i.e., during time periods T 11 -T 12 and T 16 -T 17 . Further, the ZCD signal ZCDS transitions from high to low and from low to high at times T 11 -T 19 in a manner similar to the transition explained above for times T 0 -T 10 .

Referring now to FIG. 4 , a circuit diagram of the ZVS detection circuit 110 in accordance with an embodiment of the present invention is shown. The ZVS detection circuit 110 includes a delay element 402 , a latch 404 , second and third selecting circuits 406 a and 406 b , and third and fourth comparators 408 and 410 .

The delay element 402 is connected to the first selecting circuit 306 for receiving the ZCD signal ZCDS. Further, the delay element 402 is connected to the processor 112 for receiving the delay signal DS. The delay element 402 delays the ZCD signal ZCDS and outputs a delayed version of the ZCD signal ZCDS, hereinafter referred to as delayed ZCD signal DZCD. The delay element 402 thus delays the ZCD signal ZCDS by a first delay value, which is based on the delay signal DS. When the supply voltage VS is greater than one-half of the second voltage V 2 , the first delay value is a fixed delay value, for example, a constant value of the duration of the time period T 4 -T 5 as shown in FIG. 6 . Further, when the supply voltage VS is less than one-half of the second voltage V 2 , the first delay value is a variable delay value.

The latch 404 has first and second input terminals connected to the first selecting circuit 306 and the delay element 402 for receiving the ZCD signal ZCDS and the delayed ZCD signal DZCD, respectively. The latch 404 outputs a latch output signal VL at a logic high state when the ZCD signal ZCDS and the delayed ZCD signal DZCD are at logic high and low states, respectively. The latch 404 outputs the latch output signal VL at a logic low state when the ZCD signal ZCDS and the delayed ZCD signal DZCD are at logic low and high states, respectively. In one embodiment, the latch 404 is a Set/Reset (SR) latch.

The second selecting circuit 406 a includes third and fourth switches 412 a and 412 b having first terminals that are connected to the bridgeless PFC converter 104 for receiving the first and second voltages V 1 and V 2 , respectively. In one embodiment, the ZVS detection circuit 110 also includes a second logic gate 414 that is connected to the polarity detection circuit 106 for receiving the polarity signal POL and generating/POL. That is, in one embodiment the second logic gate 414 is a NOT gate that receives POL and generates the inverted polarity signal IPOL. In another embodiment, the fourth switch 412 b is connected to an output terminal of the first logic gate 318 for receiving the inverted polarity signal IPOL.

The third and fourth switches 412 a and 412 b have control terminals that are connected to the polarity detection circuit 106 and the second logic gate 414 for receiving POL and IPOL, which control a switching operation of the third and fourth switches 412 a and 412 b , respectively. Thus, the third and fourth switches 412 a and 412 b are activated in the positive and negative half-cycles, respectively. Second terminals of the third and fourth switches 412 a and 412 b are connected together for outputting one of the first and second voltages V 1 and V 2 . When the third and fourth switches 412 a and 412 b are activated, the second selecting circuit 406 a outputs the first and second voltages V 1 and V 2 , respectively.

The third selecting circuit 406 b includes fifth and sixth switches 416 a and 416 b having first terminals that are connected to a threshold generator (not shown) and the PFC converter 104 for receiving the first threshold voltage Vth 1 and the first voltage V 1 , respectively. The first threshold voltage Vth 1 is a pre-determined value. The fifth and sixth switches 416 a and 416 b have control terminals that are connected to the polarity detection circuit 106 and the second logic gate 414 for receiving POL and IPOL, respectively, which control the switching operation of the fifth and sixth switches 416 a and 416 b , respectively. Thus, the fifth and sixth switches 416 a and 416 b are activated in the positive and negative half-cycles, respectively. Second terminals of the fifth and sixth switches 416 a and 416 b are connected together for outputting one of the first threshold voltage Vth 1 and the first voltage V 1 . When the fifth and sixth switches 416 a and 416 b are activated, the third selecting circuit 406 b outputs the first threshold voltage Vth 1 and the first voltage V 1 , respectively.

First and second terminals of the third comparator 408 are non-inverting and inverting terminals, and are connected to the second and third selecting circuits 406 a and 406 b , respectively. The third comparator 408 also has a control terminal that is connected to the latch 404 for receiving the latch output signal VL. During the positive half-cycle, the third comparator 408 receives the first voltage V 1 and the first threshold voltage Vth 1 from the second and third selecting circuits 406 a and 406 b , respectively. During the negative half-cycle, the third comparator 408 receives the second and first voltages V 2 and V 1 from the second and third selecting circuits 406 a and 406 b , respectively.

The third comparator 408 outputs a third comparison signal Vc 3 . During the positive half-cycle, the third comparator 408 outputs the third comparison signal Vc 3 at a logic high state when the latch output signal VL is at a logic high state and the first threshold voltage Vth 1 is greater than the first voltage V 1 . The third comparator 408 outputs the third comparison signal Vc 3 at a logic low state when the latch output signal VL is high and the first threshold voltage Vth 1 is less than the first voltage V 1 .

During the negative half-cycle, the third comparator 408 outputs the third comparison signal Vc 3 at a logic high state when the latch output signal VL is high and the first voltage V 1 is greater than the second voltage V 2 . Further, the third comparator 408 outputs the third comparison signal Vc 3 at a logic low state when the latch output signal VL is high and the first voltage V 1 is less than the second voltage V 2 .

The fourth comparator 410 has inverting, non-inverting and control terminals that are connected to the threshold generator, the third comparator 408 , and a driver circuit (not shown) for receiving a second threshold voltage Vth 2 , the third comparison signal Vc 3 , and a trigger voltage Vtrig, respectively. The second threshold voltage Vth 2 is a predetermined value, and is used as a reference signal to determine whether the third comparison signal Vc 3 is high or low. During the positive half-cycle, the driver circuit outputs the trigger voltage Vtrig at a logic high state when the first control signal CL 1 transitions from an inactive state to an active state. The driver circuit outputs the trigger voltage Vtrig at a logic low state when the first control signal CL 1 transitions from an active state to an inactive state. During the negative half-cycle, the driver circuit outputs the trigger voltage Vtrig at a logic high state when the second control signal CL 2 transitions from an inactive state to an active state. The driver circuit outputs the trigger voltage Vtrig at a logic low state when the second control signal CL 2 transitions from an active state to an inactive state.

The fourth comparator 410 generates the ZVS flag signal FS. The ZVS flag signal FS is indicative of a voltage across the active switches of the PFC converter 104 when the active switches transition from inactive states to active states. Thus, during the positive half-cycle, the ZVS flag signal FS is indicative of the voltage across the first transistor 208 a . The ZVS flag signal FS is asserted, i.e., high, when the trigger voltage Vtrig is high, the first voltage V 1 is less than the first threshold voltage Vth 1 , and the ZCD signal ZCDS is activate. The ZVS flag signal FS is de-asserted (i.e., low) when the trigger voltage Vtrig is high and the first voltage V 1 is greater than the first threshold voltage Vth 1 .

During the negative half-cycle, the ZVS flag signal FS is indicative of the voltage across the second transistor 208 b . Thus, the ZVS flag signal FS is high when the trigger voltage Vtrig is high, the first voltage V 1 is greater than the second voltage V 2 , and the ZCD signal ZCDS is activate. Further, the ZVS flag signal FS is low when the trigger voltage Vtrig is high and the first voltage V 1 is less than the second voltage V 2 .

Referring now to FIG. 5 , a flow chart 500 illustrating an operation of the processor 112 in accordance with an embodiment of the present invention is shown.

At step 502 , the processor 112 determines the on-time of the active switch in the positive and negative half-cycles, i.e., the time period for which the first and second transistors 208 a and 208 b remain activated, respectively, based on the voltages output in a control loop.

At step 504 , the processor 112 determines a nominal on-time Tb of the transistor implementing the free-wheeling switch, i.e., the first and second transistors 208 a and 208 b in the negative and positive half-cycles, respectively, by way of a volt-second balance relationship of the inductor 202 . For example, the nominal on-time of the second transistor 208 b , which functions as the free-wheeling switch, is from time T 2 -T 3 (see FIG. 6 ).

At step 506 , the processor 112 checks the current status of the ZVS flag signal FS (i.e., the processor 112 reads the current logic state of the ZVS flag signal FS) by way of the ZVS detection circuit 110 . The current status is a value that indicates a current voltage level of the first voltage V 1 across the transistor functioning as the active switch when the active switch transitions from an inactive state to an active state in the current switch cycle.

At step 508 , the processor 112 determines whether the ZVS flag signal FS is at a logic high state. If no (ZVS flag signal FS is low), then step 510 is performed, and if yes (ZVS flag signal FS is high), then step 512 is performed.

At step 510 , the processor 112 determines an offset compensation time ΔTb_n+1 for offsetting the nominal on-time Tb of the free-wheeling switch in a next switch cycle (such as the second switch cycle in FIG. 6 ). The offset compensation time ΔTb_n+1 is determined based on the current compensation time, i.e., ΔTb_n, of the free-wheeling switch in the current switch cycle (such as the first switch cycle in FIG. 6 ) using equation (1):

Δ Tb _ n+ 1=Δ Tb _ n+Δt 1  (1)

where,

Δt 1 is a first offset value determined by the processor 112 . For example, a difference between time period T 2 -T 3 (as shown in FIG. 6 ) and time period T 7 -T 9 (see FIG. 6 ) is the first offset value Δt 1 . The first offset value is used to vary the offset compensation time. In the example, the time period T 8 -T 9 (see FIG. 6 ) is the current compensation time ΔTb_n, and time period T 14 -T 15 (see FIG. 6 ) is the offset compensation time ΔTb_n+1 that is determined using equation (1).

Alternatively, at step 512 , the processor 112 determines the offset compensation time for the next switch cycle based on the current compensation time using equation (2):

Δ Tb _ n+ 1=Δ Tb _ n−Δt 2  (2)

where,

Δt 2 is a second offset value determined by the processor 112 . For example, a difference between time period T 14 -T 15 ( FIG. 6 ) and time period T 21 -T 22 ( FIG. 6 ) is the second offset value Δt 2 . The second offset value is used to vary the offset compensation time. In the example, time period T 14 -T 15 ( FIG. 6 ) is the current compensation time ΔTb_n and time period T 21 -T 22 ( FIG. 6 ) is the offset compensation time ΔTb_n+1 determined using equation (2).

Both of steps 510 and 512 next perform step 514 . At step 514 , the processor 112 determines whether the supply voltage VS is greater than one-half of the second voltage V 2 . If at step 514 , the processor 112 determines that the supply voltage VS is greater than one-half of the second voltage V 2 , step 516 is performed, and if no, step 518 is performed.

At step 516 , the processor 112 sets an on-time Tb_n+1 of the free-wheeling switch for the next switch cycle, for example, the on-time of the second transistor 208 b in the positive half-cycle, using equation (3):

Tb _ n+ 1= Tb+ΔTb _ n+ 1  (3)

where,

Tb is the nominal on-time of the free-wheeling switch, and

ΔTb_n+1 is the offset compensation time determined by the processor 112 . For example, time period T 13 -T 15 ( FIG. 6 ) is the current on-time Tb_n of the free-wheeling switch, i.e., the second transistor 208 b , and time period T 20 -T 22 ( FIG. 6 ) is the on-time Tb_n+1 of the second transistor 208 b that is varied based on equation (3).

If at step 514 , the processor 112 determines that the supply voltage VS is less than one-half of the second voltage V 2 , step 518 is performed. At step 518 , the processor 112 sets the first delay value for the next switch cycle (designated as “Td_n+1”) using equation (4):

Td _ n+ 1= Td _ n+ΔTb _ n+ 1  (4)

where,

Td_n is the current first delay value, and ΔTb_n+1 is the offset compensation time determined by the processor 112 .

Time period T 4 -T 5 (see FIG. 6 ) is the current first delay value (i.e., Td_n), and time period T 10 -T 11 ( FIG. 6 ) is the first delay value for the next switch cycle (i.e., Td_n+1) and is varied based on equation (4).

When the supply voltage VS is less than one-half of the second voltage V 2 , the processor 112 varies the first delay value of the delay element 402 . Thus, when the second transistor 208 b is deactivated during the positive half-cycle, the first transistor 208 a is activated when the first time duration lapses after the ZCD signal ZCDS is activated. Similarly, when the first transistor 208 a is deactivated during the negative half-cycle, the second transistor 208 b is activated when a second time duration lapses after the ZCD signal ZCDS is deactivated. During the positive and negative half-cycles, the first and second time durations correspond to the first delay value.

Referring now to FIG. 6 , a timing diagram 600 illustrating an operation of the bridgeless PFC system 100 in the positive half-cycle, in accordance with an embodiment of the present invention, is shown. In the positive half-cycle, the polarity detection circuit 106 outputs the polarity signal POL at a logic high state. The processor 112 also outputs the third control signal CL 3 at a logic high state and the fourth control signal CL 4 at a logic low state. Thus, the third transistor 214 a is activated and the fourth transistor 214 b is deactivated. The first transistor 208 a functions as the active switch and the second transistor 208 b functions as the free-wheeling switch.

At time T 0 , the inductor current IL is at a zero-current value. Further, the first and second control signals CL 1 and CL 2 are activated and deactivated, respectively. Thus, the first and second transistors 208 a and 208 b are activated and deactivated, respectively. The first voltage V 1 is less than the first threshold voltage Vth 1 . Further, the ZCD signal ZCDS is at a logic high state, and the latch output signal VL is at a logic low state. The third comparison signal Vc 3 and the ZVS flag signal FS are at logic high states.

During time period T 0 -T 1 , the inductor current IL rises from the zero-current value to the first peak value, thereby charging the inductor 202 . The first and second control signals CL 1 and CL 2 and the ZCD signal ZCDS remain unchanged. The latch output signal VL also remains unchanged at a logic low state as the ZCD signal ZCDS and the delayed ZCD signal DZCD are both high. Thus, the third comparison signal Vc 3 remains unchanged at a logic high state, i.e., remains greater than the second threshold voltage Vth 2 . Hence, the ZVS flag signal FS remains unchanged at a logic high state.

At time T 1 , the inductor current IL is at the first peak value. The first control signal CL 1 transitions from an active state to an inactive state, thereby deactivating the first transistor 208 a . Hence, time period T 0 -T 1 corresponds to the on-time of the first transistor 208 a . The second control signal CL 2 remains unchanged, thus, the second transistor 208 b remains deactivated. When the first transistor 208 a is deactivated, the inductor 202 , and the first and second body capacitors 212 a and 212 b start resonating, and the first voltage V 1 rises rapidly from a zero-voltage level to the first voltage level, i.e., the voltage level of the second voltage V 2 . Further, the inductor 202 starts discharging by way of the second body diode 210 b when the first voltage V 1 is at the voltage level of the second voltage V 2 . The first voltage V 1 is greater than the supply voltage VS, and thus the ZCD signal ZCDS goes from high to low. Further, the latch output signal VL remains unchanged at a logic low state. Thus, the third comparison signal Vc 3 and the ZVS flag signal FS remain unchanged at logic high states.

During time period T 1 -T 2 , the first control signal CL 1 and the second control signal CL 2 remain unchanged, and thus the first and second transistors 208 a and 208 b remain deactivated. Thus, the inductor 202 starts discharging by way of the second body diode 210 b and the inductor current IL starts falling from the first peak value to reach the first inductor current IL value. The first voltage V 1 remains unchanged, i.e., remains greater than the supply voltage VS. Thus, the ZCD signal ZCDS and the latch output signal VL remain unchanged at logic low states, and the third comparison signal Vc 3 and the ZVS flag signal FS remain unchanged at logic high states.

At time T 2 , the second control signal CL 2 transitions from an inactive state to an active state. Thus, the second transistor 208 b is activated after the first dead time. The first control signal CL 1 remains unchanged. The inductor current IL is at the first inductor current IL value. The first voltage V 1 remains unchanged, i.e., remains greater than the supply voltage VS. Thus, the ZCD signal ZCDS and the latch output signal VL remain unchanged at logic low states, and the third comparison signal Vc 3 and the ZVS flag signal FS remain unchanged at logic high states.

During time period T 2 -T 3 , the inductor current IL continues dropping until it reaches the zero-current value, thereby discharging the inductor 202 . The first and second control signals CL 1 and CL 2 and the first voltage V 1 remain unchanged. As a result, and the ZCD signal ZCDS and the latch output signal VL remain unchanged at logic low states, and the third comparison signal Vc 3 and the ZVS flag signal FS remain unchanged at logic high states.

At time T 3 , the first control signal CL 1 remains unchanged and the second control signal CL 2 transitions from an active state to an inactive state. Thus, the second transistor 208 b is deactivated. Hence, time period T 2 -T 3 corresponds to the on-time of the second transistor 208 b . Further, the inductor 202 , and the first and second body capacitors 212 a and 212 b start resonating. The inductor current IL reaches the zero-current value and the first voltage V 1 remains greater than the supply voltage VS. As a result, the ZCD signal ZCDS and the latch output signal VL remain unchanged at logic low states, and the third comparison signal Vc 3 and the ZVS flag signal FS remain unchanged at logic high states.

During time period T 3 -T 4 , the first and second transistors 208 a and 208 b are deactivated as the first and second control signals CL 1 and CL 2 remain unchanged. Thus, the reverse current flows through the inductor 202 , i.e., the inductor current IL falls below the zero-current value to reach a second peak value, and then starts rising. Further, the first voltage V 1 starts falling to a voltage level of the supply voltage VS. The ZCD signal ZCDS and the latch output signal VL remain unchanged at logic low states. The third comparison signal Vc 3 and the ZVS flag signal FS remain unchanged at logic high states.

At time T 4 , the first and second control signals CL 1 and CL 2 remain unchanged. Thus, the inductor 202 , and the first and second body capacitors 212 a and 212 b remain in resonance. The inductor current IL is greater than the second peak value and the first voltage V 1 is less than the supply voltage VS. The ZCD signal ZCDS transitions from low to high. Thus, the latch output signal VL transitions from low to high. Further, the third comparison signal Vc 3 transitions from a high to low (i.e., a voltage level of the third comparison signal Vc 3 falls below the second threshold voltage Vth 2 ). The ZVS flag signal FS remains unchanged at a logic high state as the trigger voltage Vtrig is at a logic low state.

During time period T 4 -T 5 , the first and second control signals CL 1 and CL 2 remain unchanged. Thus, the inductor 202 , and the first and second body capacitors 212 a and 212 b remain in resonance. Hence, the inductor current IL continues to rise to the zero-current value, and the first voltage V 1 continues to fall and is less than the supply voltage VS. The ZCD signal ZCDS and the latch output signal VL remain unchanged at logic high states. The third comparison signal Vc 3 remains unchanged at a logic low state, and the ZVS flag signal FS remains unchanged at a logic high state.

At time T 5 , the inductor current IL reaches the zero-current value. Further, the first control signal CL 1 transitions from an inactive state to an active state, thus, activating the first transistor 208 a after the second dead time. The second control signal CL 2 remains unchanged. The first voltage V 1 falls to the zero-voltage level. The ZCD signal ZCDS remains unchanged at a logic high state. The latch output signal VL transitions from a logic high state to a logic low state (as the delayed ZCD signal DZCD transitions from a logic low state to a logic high state due to the delay value that equals the time period T 4 -T 5 ). The third comparison signal Vc 3 remains unchanged at a logic low state. As a voltage level of the third comparison signal Vc 3 is less than the second threshold voltage Vth 2 , the ZVS flag signal FS goes from high to low.

The time period T 0 -T 5 is a first switch cycle. Based on the ZVS flag signal FS at time T 5 and the first through third equations (1)-(3), the processor 112 sets the on-time of the second transistor 208 b for a next switch cycle T 5 -T 11 .

The inductor current IL, the first control signal CL 1 , the ZCD signal ZCDS, and the latch output signal VL vary periodically during time periods T 5 -T 11 , T 11 -T 18 , and T 18 -T 25 in a manner as explained in the first switch cycles T 0 -T 5 . The on-time of the second control signal CL 2 varies based on the ZVS flag signal FS. Thus, the second transistor 208 b is deactivated at times T 9 , T 15 , and T 22 based on the ZVS flag signal FS as explained above with reference to FIG. 5 .

The ZVS flag signal FS goes low at time T 5 in the first switch cycle T 0 -T 5 . Thus, the processor 112 increases the on-time of the second transistor 208 b based on the equations (1) and (3) in the second switch cycle T 5 -T 12 as explained above with reference to FIG. 5 . At time T 8 , the inductor current IL falls to the zero-current value, however, the second control signal CL 2 remains activated. Thus, the second transistor 208 b remains activated. During time period T 8 -T 9 , the inductor current IL falls below the zero-current value, and the first and second control signals CL 1 and CL 2 , the ZCD signal ZCDS, and the third comparison signal Vc 3 remain unchanged.

At time T 9 , the second control signal CL 2 transitions from an active state to an inactive state, thereby deactivating the second transistor 208 b . The inductor 202 , and the first and second body capacitors 212 a and 212 b start resonating. Thus, the reverse current flows through the inductor 202 , i.e., the inductor current IL falls below the zero-current value. Thus, the first voltage V 1 falls to a voltage level closer to the first threshold voltage Vth 1 .

The ZVS flag signal FS remains unchanged at a logic low state in the second switch cycle T 5 -T 11 . Thus, the processor 112 increase the on-time of the second transistor 208 b based on equations (1) and (3) in the third switch cycle T 11 -T 18 as discussed above. At time T 14 , the inductor current IL falls to the zero-current value, however, the second control signal CL 2 remains activated. Thus, the second transistor 208 b remains activated. During time period T 14 -T 15 , the inductor current IL falls below the zero-current value and the first and second control signals CL 1 and CL 2 , the ZCD signal ZCDS, and the third comparison signal Vc 3 remain unchanged.

At time T 15 , the second control signal CL 2 transitions from an active state to an inactive state, thus, deactivating the second transistor 208 b . The offset compensation time T 14 -T 15 in the third switch cycle T 11 -T 18 is larger than the offset compensation time T 8 -T 9 in the second switch cycle T 5 -T 11 . Thus, the first voltage V 1 is less than the first threshold voltage Vth 1 at the time instance T 17 . Further, the latch output signal VL is at a logic high state. Thus, the third comparison signal Vc 3 transitions from a logic low state to a logic high state.

At time T 18 , the first control signal CL 1 transitions from an inactive state to an active state, thus, activating the first transistor 208 a . Further, the third comparison signal Vc 3 is greater than the second threshold voltage Vth 2 , and thus the ZVS flag signal FS transitions from a logic low state to a logic high state.

The ZVS flag signal FS transitions to a logic high state at the time T 18 in third switch cycle T 11 -T 18 . Thus, the processor 112 decreases the on-time of the second transistor 208 b based on the equations (2) and (3) in the fourth switch cycle T 18 -T 25 as previously explained. At time T 21 , the inductor current IL falls to the zero-current value, however, the second control signal CL 2 remains activated. Thus, the second transistor 208 b remains activated. During time period T 21 -T 22 , the inductor current IL falls below the zero-current value and the first and second control signals CL 1 and CL 2 , the ZCD signal ZCDS, and the third comparison signal Vc 3 remain unchanged.

At time T 22 , the second control signal CL 2 transitions from an active state to an inactive state, thus, deactivating the second transistor 208 b . The offset compensation time T 21 -T 22 in the fourth switch cycle T 18 -T 25 is less than the offset compensation time T 14 -T 15 in the third switch cycle T 11 -T 18 . This enables the first voltage V 1 to drop to the zero-voltage level at a time that is closer to time T 25 when the first transistor 208 a is activated.

The ZCD circuit 108 uses configurable comparators (i.e., the first and second comparators 304 a and 304 b ) and sampling circuitry (not shown) of the ZVS detection circuit 110 . Thus, the need for separate sampling circuitry to sample the first and supply voltages V 1 and VS is eliminated. Further, the sampling of the first and supply voltages V 1 and VS by the ZVS detection circuit 110 ensures that the first voltage V 1 and the supply voltage VS remain at positive voltage levels in the positive and negative half-cycles. Hence, the need for a rectifier circuit in the bridgeless PFC system 100 is eliminated. Thus, absence of the separate sampling circuitry and the rectifier circuit reduces the area occupied by the ZCD circuit 108 . Additionally, the area and cost of the bridgeless PFC system 100 is less than that of conventional bridgeless PFC systems because the ZCD circuits requires less area.

The processor 112 outputs the first and second control signals CL 1 and CL 2 based on the detection of the zero-current state by the ZCD circuit 108 in real-time without additional circuitry (such as current transformer sensors to detect the zero-current state). Thus, the power consumed by the bridgeless PFC system 100 is less than for conventional bridgeless PFC systems that require additional circuitry for detecting the zero-current state. In addition, the ZCD signal ZCDS acts as a timing control signal for the generation of the ZVS flag signal FS in real-time, thereby leading to better accuracy and reliability.

It will be understood by those of skill in the art that the same functions may be performed by different arrangements of transistors that may operate using either high active or low active signals. Therefore, variations in the arrangement of some of the transistors described above should not be considered to depart from the scope of the present invention. In describing transistors, the terms gate, drain and source are used interchangeably with the respective terms “gate terminal”, “drain terminal” and “source terminal”.

While various embodiments of the present invention have been illustrated and described, it will be clear that the present invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the present invention, as described in the claims.