Transistor and method for forming the same

The disclosure relates to a semiconductor device, and particularly relates to a transistor and a method for forming the same.

As technology advances, the semiconductor device is minimized to meet the trend of lighter, thinner, shorter and smaller products. As the size of the semiconductor device is scaled down, the gate thickness becomes less and the spacer width becomes shorter, resulting in high gate-induced drain leakage (GIDL) and severe hot carrier effect.

In the conventional method, the implanting dosage of source/drain extension (SDE) regions is increased to resolve the said issues. However, the sheet resistance and gate-drain overlap capacitance are increased to affect the device performance. Therefore, how to effectively increase the spacer width to alleviate the GIDL and hot carrier effect has drawn high attention in the industry.

Accordingly, the present invention provides a transistor and a method of forming the same, in which a spacer width of the transistor can be increased, so the gate-induced drain leakage (GIDL) and hot carrier effect can be reduced.

According to an embodiment, a transistor is provided. The transistor comprises a semiconductor substrate, a gate dielectric layer, a gate electrode, a spacer, and a source/drain. The semiconductor substrate comprises a protrusive semiconductor portion protruded from a lower surface of the semiconductor substrate. The gate dielectric layer is on the semiconductor substrate. The gate electrode is on the gate dielectric layer. The spacer is on a sidewall of the gate electrode. An outer surface of the spacer has a concave portion. The source/drain is in the semiconductor substrate.

According to another embodiment, a method for forming a transistor is provided. The method comprises the following steps. A gate dielectric layer is formed on a semiconductor substrate comprising a protrusive semiconductor portion protruded from a lower surface of the semiconductor substrate. A gate electrode is formed on the gate dielectric layer. A spacer is formed. The spacer is on a sidewall of the gate electrode. An outer surface of the spacer has a concave portion. A source/drain is formed in the semiconductor substrate.

FIG. 1 to FIG. 5 are schematic cross-sectional views of a method of forming a semiconductor device according to an embodiment.

FIG. 6 is a schematic cross-sectional view of a step for a method of forming a semiconductor device according to another embodiment.

FIG. 7 to FIG. 9 are schematic cross-sectional views of a method of forming a semiconductor device according to yet another embodiment.

In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.

Embodiments are provided hereinafter with reference to the accompanying drawings for describing the related procedures and configurations. It is noted that not all embodiments of the invention are shown. Also, it is noted that there may be other embodiments of the present disclosure which are not specifically illustrated. Modifications and variations can be made without departing from the spirit of the disclosure to meet the requirements of the practical applications. It is also important to point out that the illustrations may not be necessarily drawn to scale. Thus, the specification and the drawings are to be regard as an illustrative sense rather than a restrictive sense. The identical and/or similar elements of the embodiments are designated with the same and/or similar reference numerals.

FIG. 1 to FIG. 5 are shown to illustrate a manufacturing method for forming a semiconductor device according to an embodiment.

Referring to FIG. 1 , a semiconductor substrate 102 is provided. The semiconductor substrate 102 may comprise a silicon-containing substrate. The semiconductor substrate 102 has a front surface comprising an upper surface 102 U. An etching step may be performed to the semiconductor substrate 102 from the upper surface 102 U to form a recess 104 exposing a sidewall surface 102 S′ and a lower surface 102 L below the sidewall surface 102 S′ of the semiconductor substrate 102 . In addition, a protrusive semiconductor portion 102 P′ may be defined through the etching step. In an embodiment, during the etching step, a patterned mask layer (not shown) formed the upper surface 102 U of the semiconductor substrate 102 may be used as an etching mask, and a pattern of the patterned mask layer may be transferred down into the semiconductor substrate 102 so as to form the recess 104 . In an embodiment, the patterned mask layer comprises a photoresist formed by a photolithography process, but is not limited thereto. After the etching step, the patterned mask layer (not shown) may be removed. The protrusive semiconductor portion 102 P′ has the sidewall surface 102 S′ and the upper surface 102 U and is protruded from the lower surface 102 L of the semiconductor substrate 102 . In this embodiment, the sidewall surface 102 S′ formed through the etching step for forming the recess 104 , the protrusive semiconductor portion 102 P′ may be a vertical surface perpendicular to the lower surface 102 L and the upper surface 102 U of the semiconductor substrate 102 .

A dielectric film 106 may be formed on the front surface of the semiconductor substrate 102 . The front surface comprises the upper surface 102 U, the lower surface 102 L and the sidewall surface 102 S′. The dielectric film 106 includes silicon oxide, and the forming method thereof includes performing an oxidation process or a suitable deposition process, such as a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process, and so on. An isolation structure 108 may be formed in the semiconductor substrate 102 . Active regions in a region 110 A and a region 110 B may be defined by the isolation structure 108 . In an embodiment, the isolation structure 108 comprises a shallow trench isolation (STI) as shown in figures, but is not limited thereto, and may use other suitable isolation elements.

Referring to FIG. 2 , a gate dielectric layer 112 is formed on the semiconductor substrate 102 . In an embodiment, the gate dielectric layer 112 may be formed by a method comprising a thermal oxidation method which may transform the protrusive semiconductor portion 102 P′ ( FIG. 1 ) into a protrusive semiconductor portion 102 P having a leaned sidewall surface 102 S between the upper surface 102 U and the lower surface 102 L of the semiconductor substrate 102 as shown in FIG. 2 . The gate dielectric layer 112 includes silicon oxide.

The leaned sidewall surface 102 S of the protrusive semiconductor portion 102 P is not perpendicular to the upper surface 102 U and the lower surface 102 L of the semiconductor substrate 102 . For example, an included angle θ between the leaned sidewall surface 102 S and the upper surface 102 U of the protrusive semiconductor portion 102 P may be an obtuse angle of 120 degrees to 150 degrees. In an embodiment, the protrusive semiconductor portion 102 P may have a trapezoid shape. For example, the protrusive semiconductor portion 102 P has a bottom size k 1 (e.g. width) in a first direction D 1 and a top size k 2 (e.g. width) in the first direction D 1 . The bottom size k 1 is larger than the top size k 2 . A difference between the bottom size k 1 and the top size k 2 may be 600 Å to 800 Å. A size k 3 (e.g. height) of the protrusive semiconductor portion 102 P in a second direction D 2 may be 300 Å to 400 Å. The first direction D 1 is different from the second direction D 2 . The first direction D 1 may be substantially perpendicular to the second direction D 2 . For example, the first direction D 1 may be parallel to a X axis or a Y axis, and the second direction D 2 may be parallel to a Z axis.

In an embodiment, gate dielectric layer 112 may be a conformal film on the front surface of the semiconductor substrate 102 . Therefore, the gate dielectric layer 112 in the region 110 A may have a surface profile similar to the front surface comprising the leaned sidewall surface 102 S, the upper surface 102 U and the lower surface 102 L of the semiconductor substrate 102 in the region 110 A. In other words, the gate dielectric layer 112 in the region 110 A may have an upper surface 112 U, a lower surface 112 L, and a leaned sidewall surface 112 S between the upper surface 112 U and the lower surface 112 L.

Referring to FIG. 3 , a gate electrode 114 A and a gate electrode 114 B are formed on the gate dielectric layer 112 . The gate electrode 114 A is formed on the gate dielectric layer 112 on the protrusive semiconductor portion 102 P of the semiconductor substrate 102 in the region 110 A. The gate electrode 114 A may be on the upper surface 102 U of the protrusive semiconductor portion 102 P. The gate electrode 114 B is formed on the gate dielectric layer 112 in the region 1108 . The gate electrode 114 A and the gate electrode 114 B may be formed by a method comprising forming a conductive material layer (not show), including polysilicon, amorphous silicon or a combination thereof, on the structure shown in FIG. 2 by a suitable deposition process, such as a CVD process or an ALD process, and then patterning the conductive material layer by a patterning step including performing photolithography and etching processes.

The gate electrode 114 A has a size M in the first direction D 1 . The bottom size k 1 of the protrusive semiconductor portion 102 P is larger than the size M of the gate electrode 114 A. The size M of the gate electrode 114 A may be larger than, equal to, or smaller than the top size k 2 of the protrusive semiconductor portion 102 P. In an example, a difference between the top size k 2 of the protrusive semiconductor portion 102 P and the size M of the gate electrode 114 A is within 10 nm.

An insulating film 116 may be formed on the gate electrode 114 A, the gate electrode 114 B, the gate dielectric layer 112 , and the isolation structure 108 . The insulating film 116 includes silicon nitride, and the forming method thereof includes performing a suitable deposition process, such as a CVD process or an ALD process. In an embodiment, the insulating film 116 may have a thickness T being 320 Å to 380 Å.

Referring to FIG. 4 , an etching step may be performed to remove a portion of the insulating film 116 ( FIG. 3 ), and the remained portion of the insulating film 116 forms a spacer 118 A and a spacer 118 B. In an embodiment, the etching step may be an anisotropic etching step for the insulating film 116 , and the spacer 118 A and the spacer 1188 are self-aligned spacers formed without using/forming a photo mask layer and/or an addition film stack. The spacer 118 A is on a sidewall of the gate electrode 114 A and is on the gate dielectric layer 112 A on the leaned sidewall surface 102 S of the protrusive semiconductor portion 102 P and the lower surface 102 L of the semiconductor substrate 102 . In embodiments, an outer surface of the spacer 118 A has a concave portion 118 A 1 . In an embodiment, the outer surface of the spacer 118 A may have a double C-shape, for example, comprising the concave portion 118 A 1 and further comprising a lower convex portion 118 A 2 and an upper convex portion 118 A 3 . The concave portion 118 A 1 is between the lower convex portion 118 A 2 and the upper convex portion 118 A 3 . A portion of the spacer 118 A having the lower convex portion 118 A 2 is on the gate dielectric layer 112 A on the leaned sidewall surface 102 S of the protrusive semiconductor portion 102 P. A portion of the spacer 118 A having the upper convex portion 118 A 3 is on the sidewall of the gate electrode 114 A. A gate structure GA in the region 110 A comprises the gate dielectric layer 112 A, the gate electrode 114 A and the spacer 118 A. The spacer 118 B is on a sidewall of the gate electrode 114 B and is on the gate dielectric layer 112 B on the upper surface 102 U of the semiconductor substrate 102 . A gate structure GB in the region 110 B comprises the gate dielectric layer 112 B, the gate electrode 114 B and the spacer 118 B.

Referring to FIG. 5 , a source/drain 120 A and a source/drain 120 B are formed in the semiconductor substrate 102 . The source/drain 120 A and the source/drain 120 B may be formed by a doping process with using the gate structure GA and the gate structure GB as a doping mask. A transistor 122 A comprises the gate structure GA and the source/drain 120 A in the region 110 A. A transistor 122 B comprises the gate structure GB and the source/drain 120 B in the region 110 B. In an embodiment, for example, the region 110 A may be a medium-V device region. The region 110 B may be a low-V device region. A thickness N of the gate dielectric layer 112 A of the transistor 122 A may be larger than a thickness of the gate dielectric layer 112 B of the transistor 122 B. For example, in an embodiment, the thickness N of the gate dielectric layer 112 A of the transistor 122 A may be 100 Å to 300 Å.

In the embodiment, the spacer 118 A of the transistor 122 A has an expanded portion (i.e. the portion having the concave portion 118 A 1 and the portion having the lower convex portion 118 A 2 ) on the leaned surface sidewall (i.e. the leaned sidewall surface 112 S of the gate dielectric layer 112 A and the leaned sidewall surface 102 S of the protrusive semiconductor portion 102 P) beyond the sidewall of the gate electrode 114 A. Therefore, the spacer 118 A has an increased spacer width with the expanded portion. In such manner, the GIDL and hot carrier effect of the transistor 122 A can be reduced.

The semiconductor device as shown in FIG. 5 is not limited to be manufactured through the above method.

For example, the manufacturing step shown in FIG. 1 may be replaced by a manufacturing step shown in FIG. 6 . Referring to FIG. 6 , in another embodiment, the leaned sidewall surface 102 S of the protrusive semiconductor portion 102 P may be formed through the etching step performed to the semiconductor substrate 102 for forming the recess 104 /protrusive semiconductor portion 102 P before forming a gate dielectric layer (for example the gate dielectric layer 112 illustrated referring to FIG. 2 ).

FIG. 7 to FIG. 9 are shown to illustrate a manufacturing method for forming a semiconductor device according to yet another embodiment.

Referring to FIG. 7 , a gate dielectric layer (for example similar to the gate dielectric layer 112 illustrated with referring to FIG. 2 ) may be formed on the upper surface 102 U of the semiconductor substrate 102 . The gate electrode 114 A and the gate electrode 114 B are formed on the gate dielectric layer. A patterned mask layer 350 may be formed to cover the structure in the region 110 B. An etching step may be performed to remove portions of the gate dielectric layer and the semiconductor substrate 102 not covered by the gate electrode 114 A and the patterned mask layer 350 functioning as an etching mask. In particular, the etching step removes the gate dielectric layer and then removes the semiconductor substrate 102 from the upper surface 102 U to form the recess 104 exposing the leaned sidewall surface 102 S and the lower surface 102 L of the semiconductor substrate 102 and form the protrusive semiconductor portion 102 P in the region 110 A. The remained portion of the gate dielectric layer in the region 110 A forms the gate dielectric layer 112 A.

Referring to FIG. 8 , the spacer 118 A is formed on the sidewall of the gate electrode 114 A, a sidewall of the gate dielectric layer 112 A, the leaned sidewall surface 102 S of the protrusive semiconductor portion 102 P and the lower surface 102 L of the semiconductor substrate 102 . In particular, since the gate dielectric layer 112 A not covered by the gate electrode 114 A in the region 110 A is removed, the spacer 118 A is formed to be in contact with the sidewall of the gate dielectric layer 112 A, the leaned sidewall surface 102 S of the protrusive semiconductor portion 102 P, and the lower surface 102 L of the semiconductor substrate 102 . The spacer 118 B is formed on the sidewall of the gate electrode 114 B and the gate dielectric layer 112 B on the upper surface 102 U of the semiconductor substrate 102 . The spacer 118 A and the spacer 1188 may be formed by a method comprising forming an insulating film by a deposition method and then performing an anisotropic etching step to the insulation film, similar to the illustration relative to the process performed to the insulating film 116 referring to FIG. 3 and FIG. 4 .

The semiconductor structure shown in FIG. 8 may be different from the semiconductor structure shown in FIG. 4 with the following illustration. Portions of the spacer 118 A having the concave portion 118 A 1 and the lower convex portion 118 A 2 is on the sidewall of the gate dielectric layer 112 A and the leaned sidewall surface 102 S of the protrusive semiconductor portion 102 P. In particular, the portion of the spacer 118 A having the concave portion 118 A 1 is in contact with the leaned sidewall surface 102 S of the protrusive semiconductor portion 102 P, and the lower surface 102 L of the semiconductor substrate 102 . The size M of the gate electrode 114 A may be substantially equal to top size k 2 of the protrusive semiconductor portion 102 P.

Referring to FIG. 9 , the source/drain 120 A and the source/drain 1208 are formed in the semiconductor substrate 102 .

In the embodiment, the spacer 118 A of the transistor 122 A has an expanded portion (i.e. the portion having the concave portion 118 A 1 and the portion having the lower convex portion 118 A 2 ) on the leaned sidewall surface 102 S of the protrusive semiconductor portion 102 P beyond the sidewalls of the gate electrode 114 A and the gate dielectric layer 112 A. Therefore, the spacer 118 A has an increased spacer width with the expanded portion. In such manner, the GIDL and hot carrier effect of the transistor 122 A can be alleviated.

In summary, in the present invention, the transistor 122 A has the spacer 118 A having an expanded portion (i.e. the portion with the outer surface having the concave portion 118 A 1 and/or the portion with the outer surface having the lower convex portion 118 A 2 ) on the leaned surface sidewall (i.e. the leaned sidewall surface 112 S of the gate dielectric layer 112 A and/or the leaned sidewall surface 102 S of the protrusive semiconductor portion 102 P) beyond the sidewall of the gate electrode 114 A. Therefore, the spacer 118 A has an increased spacer width with the expanded portion. In such manner, the GIDL and hot carrier effect of the transistor 122 A can be reduced. The spacer 118 A may be a self-aligned spacer formed without using/forming a photo mask layer and/or an addition film stack.

While the disclosure has been described by way of example and in terms of the exemplary embodiment(s), it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.