Transmitting apparatus and signal processing method thereof

This application is a Continuation of U.S. application Ser. No. 14/506,794 filed Oct. 6, 2014, which claims the benefit under 35 U.S.C. § 119 from U.S. Provisional Application No. 61/886,849 filed on Oct. 4, 2013, in the United States Patent and Trademark Office and Korean Patent Application No. 10-2014-0134441 filed on Oct. 6, 2014 in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety.

1. Technical Field

Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus and a signal processing method thereof, and more particularly, to a transmitting apparatus which processes data and transmits the data, and a signal processing method thereof.

2. Description of the Related Art

In a communication/broadcasting system, link performance may greatly deteriorate due to various noises of channels, a fading phenomenon, and an inter-symbol interference (ISI). Therefore, in order to implement high digital communication/broadcasting systems requiring high data throughput and reliability, such as next-generation mobile communication, digital broadcasting, and portable Internet, there is a demand for a method for overcoming the noise, fading, and inter-symbol interference. To overcome the noise, etc., research on an error-correction code has been actively conducted in recent years as a method for effectively restoring distorted information and enhancing reliability of communication.

The Low Density Parity Check (LDPC) code which was first introduced by Gallager in the 1960s has been forgotten for a long time due to its difficulty and complexity in realizing by the level of technology at that time. However, as the turbo code which was suggested by Berrou, Glavieux, Thitimajshima in 1993 showed performance equivalent to the channel capacity of Shannon, the performance and characteristics of the turbo code were actively interpreted and many researches on channel encoding based on iterative decoding and graph were conducted. This leaded the re-research on the LDPC code in the late 1990's and it turned out that decoding by applying iterative decoding based on a sum-product algorithm on a Tanner graph corresponding to the LDPC code resulted in the performance equivalent to the channel capacity of Shannon.

When the LDPC code is transmitted by using a high order modulation scheme, performance depends on how codeword bits are mapped onto high order modulation bits. Therefore, there is a need for a method for mapping LDPC codeword bits onto high order modulation bits to obtain an LDPC code of good performance.

One or more exemplary embodiments may overcome the above disadvantages and other disadvantages not described above. However, it is understood that one or more exemplary embodiment are not required to overcome the disadvantages described above, and may not overcome any of the problems described above.

One or more exemplary embodiments provide a transmitting apparatus which can map a bit included in a predetermined group from among a plurality of groups of a Low Density Parity Check (LDPC) codeword onto a predetermined bit of a modulation symbol, and transmit the bit, and a signal processing method thereof.

According to an aspect of an exemplary embodiment, there is provided a transmitting apparatus including: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol, the interleaver is formed of a plurality of columns each including a plurality of rows and includes a block interleaver configured to divide each of the plurality of columns into a first part and a second part and interleave the LDPC codeword, wherein the number of rows constituting each column divided into the first part is determined differently depending upon the modulation method, and wherein the number of rows constituting each column divided into the second part is determined depending upon the number of rows constituting each column divided into the first part.

The number of the plurality of columns may have the same value as a modulation degree according to the modulation method. In addition, each of the plurality of columns may be formed of rows corresponding to a value obtained by dividing the number of bits constituting an LDPC codeword by the number of the plurality of columns.

The first part may be formed of rows as many as the number of bits included in at least a part of bit groups which are writable in bit group units in each of the plurality of columns among a plurality of bit groups constituting the LDPC codeword, in each of the plurality of columns. In addition, the second part may be formed of rows excluding rows corresponding to the number of bits included in at least a part of bit groups which are writable in bit group units in each of the plurality of columns in rows constituting each of the plurality of columns, in each of the plurality of columns.

The number of rows of the second part may have the same value as a quotient obtained by dividing the number of bits included in all bits groups excluding a bit group corresponding to the first part by the number of columns constituting the block interleaver.

The block interleaver may sequentially write the bits included in the at least a part of bits groups which are writable in the bit group units in each of the plurality of columns constituting the first part, divide bits included in remaining bit groups excluding at least a part of bit groups from a plurality of bit groups based on the number of the plurality of columns, and sequentially write the divided bits in each of the plurality of columns constituting the second part.

The block interleaver may perform interleaving by dividing the bits included in the remaining bit groups by the number of the plurality of columns, writing each of the divided bits in each of the plurality of columns constituting the second part in a column direction, and reading the plurality of columns constituting the first part and the second part in a row direction.

In response to the modulation method being QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, the modulation degree may be 2, 4, 6, 8, 10, and 12.

According to an aspect of an exemplary embodiment, there is provided a method for processing a signal of a transmitting apparatus, the method including: generating a low density parity check (LDPC) codeword by performing LDPC encoding; interleaving the LDPC codeword; and generating a modulation symbol by modulating the interleaved LDPC codeword according to a modulation method, the interleaving comprises interleaving the LDPC codeword by dividing each of a plurality of columns each including a plurality of rows into a first part and a second part, wherein the number of rows constituting each column divided into the first part is determined differently depending upon the modulation method, and wherein the number of rows constituting each column divided into the second part is determined depending upon the number of rows constituting each column divided into the first part.

The number of the plurality of columns may have the same value as a modulation degree according to the modulation method. In addition, each of the plurality of columns may be formed of rows corresponding to a value obtained by dividing the number of bits constituting an LDPC codeword by the number of the plurality of columns.

The first part may be formed of rows as many as the number of bits included in at least a part of bit groups which are writable in bit group units in each of the plurality of columns among a plurality of bit groups constituting the LDPC codeword, in each of the plurality of columns. In addition, the second part may be formed of rows excluding rows corresponding to the number of bits included in at least a part of bit groups which are writable in bit group units in each of the plurality of columns in rows constituting each of the plurality of columns, in each of the plurality of columns.

The number of rows of the second part may have the same value as a quotient obtained by dividing the number of bits included in all bits groups excluding a bit group corresponding to the first part by the number of plurality of columns.

The interleaving may include sequentially writing the bits included in the at least a part of bits groups which are writable in the bit group units in each of the plurality of columns constituting the first part, dividing bits included in remaining bit groups excluding at least a part of bit groups from a plurality of bit groups based on the number of the plurality of columns, and sequentially writing the divided bits in each of the plurality of columns constituting the second part.

The interleaving may include performing interleaving by dividing the bits included in the remaining bit groups by the number of the plurality of columns, writing each of the divided bits in each of the plurality of columns constituting the second part in a column direction, and reading the plurality of columns constituting the first part and the second part in a row direction.

In response to the modulation method being QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, the modulation degree may be 2, 4, 6, 8, 10, and 12.

According to various exemplary embodiments, more excellent encoding performance and reception performance may be provided.

The above and/or other aspects will be more apparent by describing in detail exemplary embodiments, with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram to illustrate a configuration of a transmitting apparatus according to an exemplary embodiment;

FIGS. 2 and 3 are views to illustrate a configuration of a parity check matrix according to exemplary embodiments;

FIG. 4 is a block diagram to illustrate a configuration of an interleaver according to an exemplary embodiment;

FIGS. 5 to 7 are views illustrating a method for processing an LDPC codeword on a group basis according to exemplary embodiments;

FIGS. 8 to 11 are views to illustrate a configuration of a block interleaver and an interleaving method according to exemplary embodiments;

FIGS. 12 and 13 are views to illustrate an operation of a demultiplexer according to exemplary embodiments;

FIG. 14 is a view to illustrate an example of a uniform constellation modulation method according to an exemplary embodiment;

FIGS. 15 to 19 are views to illustrate an example of a non-uniform constellation modulation method according to exemplary embodiments;

FIG. 20 is a block diagram to illustrate a configuration of a receiving apparatus according to an exemplary embodiment;

FIG. 21 is a block diagram to illustrate a configuration of a deinterleaver according to exemplary embodiments;

FIG. 22 is a view to illustrate a block deinterleaver according to an exemplary embodiment; and

FIG. 23 is a flowchart to illustrate a signal processing method according to an exemplary embodiment.

Hereinafter, various exemplary embodiments will be described in greater detail with reference to the accompanying drawings.

In the following description, same reference numerals are used for the same elements when they are depicted in different drawings. The matters defined in the description, such as detailed construction and elements, are provided to assist in a comprehensive understanding of the exemplary embodiments. Thus, it is apparent that the exemplary embodiments can be carried out without those specifically defined matters. Also, functions or elements known in the related art are not described in detail since they would obscure the exemplary embodiments with unnecessary detail.

FIG. 1 is a block diagram to illustrate a configuration of a transmitting apparatus according to a first exemplary embodiment. Referring to FIG. 1 , the transmitting apparatus 100 includes an encoder 110 , an interleaver 120 , and a modulator 130 (or a constellation mapper).

The encoder 110 generates a Low Density Parity Check (LDPC) codeword by performing LDPC encoding. The encoder 110 may include an LDPC encoder (not shown) to perform the LDPC encoding.

Specifically, the encoder 110 LDPC-encodes input bits to information word bits to generate the LDPC codeword which is formed of the information word bits and parity bits (that is, LDPC parity bits). Here, since an LDPC code for the LDPC encoding is a systematic code, the information word bits may be included in the LDPC codeword as they are.

The LDPC codeword is formed of the information word bits and the parity bits. For example, the LDPC codeword is formed of N ldpc number of bits, and includes K ldpc number of information word bits and N parity =N ldpc −K ldpc number of parity bits.

In this case, the encoder 110 may generate the LDPC codeword by performing the LDPC encoding based on a parity check matrix. That is, since the LDPC encoding is a process for generating an LDPC codeword to satisfy H·C T =0, the encoder 110 may use the parity check matrix when performing the LDPC encoding. Herein, H is a parity check matrix and C is an LDPC codeword.

For the LDPC encoding, the transmitting apparatus 100 may include a separate memory and may pre-store parity check matrices of various formats.

For example, the transmitting apparatus 100 may pre-store parity check matrices which are defined in Digital Video Broadcasting-Cable version 2 (DVB-C2), Digital Video Broadcasting-Satellite-Second Generation (DVB-S2), Digital Video Broadcasting-Second Generation Terrestrial (DVB-T2), etc., or may pre-store parity check matrices which are defined in the North America digital broadcasting standard system Advanced Television System Committee (ATSC) 3.0 standards, which are currently being established. However, this is merely an example and the transmitting apparatus 100 may pre-store parity check matrices of other formats in addition to these parity check matrices.

Hereinafter, a configuration of a parity check matrix will be explained in detail with reference to FIGS. 2 and 3 .

First, referring to FIG. 2 , a parity check matrix 200 is formed of an information word submatrix 210 corresponding to information word bits, and a parity submatrix 220 corresponding to parity bits. In the parity check matrix 200 , elements other than elements with 1 have 0.

The information word submatrix 210 includes K ldpc number of columns and the parity submatrix 220 includes N parity =N ldpc −K ldpc number of columns. The number of rows of the parity check matrix 200 is identical to the number of columns of the parity submatrix 220 , N parity =N ldpc −K ldpc .

In addition, in the parity check matrix 200 , N ldpc is a length of an LDPC codeword, K ldpc is a length of information word bits, and N parity =N ldpc −K ldpc is a length of parity bits. The length of the LDPC codeword, the information word bits, and the parity bits mean the number of bits included in each of the LDPC codeword, the information bits, and the parity bits.

Hereinafter, the configuration of the information word submatrix 210 and the parity submatrix 220 will be explained in detail.

The information word submatrix 210 includes K ldpc number of columns (that is, 0 th column to (K ldpc −1) th column), and follows the following rules:

First, M number of columns from among K ldpc number of columns of the information word submatrix 210 belong to the same group, and K ldpc number of columns is divided into K ldpc /M number of column groups. In each column group, a column is cyclic-shifted from an immediately previous column by Q ldpc or Q ldpc number of bits.

Herein, M is an interval at which a pattern of a column group, which includes a plurality of columns, is repeated in the information word submatrix 210 (e.g., M=360), and Q ldpc is a size by which one column is cyclic-shifted from an immediately previous column in a same column group in the information word submatrix 210 . M and Q ldpc are integers and are determined to satisfy Q ldpc =(N ldpc −K ldpc )/M. In this case, K ldpc /M is also an integer. M and Q ldpc may have various values according to a length of the LDPC codeword and a code rate.

For example, when M=360 and the length of the LDPC codeword, N ldpc , is 64800, Q ldpc may be defined as in table 1 presented below, and, when M=360 and the length N ldpc of the LDPC codeword is 16200, Q ldpc may be defined as in table 2 presented below.

Second, when the degree of the 0 th column of the i th column group (i=0, 1, . . . , K ldpc /M−1) is D i (herein, the degree is the number of value 1 existing in each column and all columns belonging to the same column group have the same degree), and a position (or an index) of each row where 1 exists in the 0 th column of the i th column group is R i,0 (0) , R i,0 (1) , . . . , R i,0 (D i −1) an index R i,j (k) of a row where k th weight-1 is located in the j th column in the i th column group (that is, an index of a row where k th 1 is located in the j th column in the i th column group) is determined by following Equation 1:

R i,j (k) =R i,(j−1) (k) +Q ldpc mod( N ldpc −K ldpc )  (1)

where k=0, 1, 2, . . . D i −1; i=0, 1, . . . , K ldpc /M−1; and j=1, 2, . . . , M−1.

Equation 1 can be expressed as following Equation 2:

R i,j (k) ={R i,0 (k) +( j mod M )× Q ldpc }mod( N ldpc −K ldpc )  (2)

where k=0, 1, 2, . . . D i −1; i=0, 1, . . . , K ldpc /M−1; and j=1, 2, . . . , M−1.

In the above equations, R i,j (k) is an index of a row where k th weight-1 is located in the j th column in the i th column group, N ldpc is a length of an LDPC codeword, K ldpc is a length of information word bits, D i is a degree of columns belonging to the i th column group, M is the number of columns belonging to a single column group, and Q ldpc is a size by which each column in the column group is cyclic-shifted.

As a result, referring to these equations, when only R i,0 (k) is known, the index R i,j (k) of the row where the k th weight-1 is located in the j th column in the i th column group can be known. Therefore, when the index value of the row where the k th weight-1 is located in the first column of each column group is stored, a position of column and row where weight-1 is located in the parity check matrix 200 having the configuration of FIG. 2 (that is, in the information word submatrix 210 of the parity check matrix 200 ) can be known.

According to the above-described rules, all of the columns belonging to the i th column group have the same degree D i . Accordingly, the LDPC codeword which stores information on the parity check matrix according to the above-described rules may be briefly expressed as follows.

For example, when N ldpc is 30, K ldpc is 15, and Q ldpc is 3, position information of the row where weight-1 is located in the 0 th column of the three column groups may be expressed by a sequence of Equations 3 and may be referred to as “weight-1 position sequence”.

R 1,0 (1) =1, R 1,0 (2) =2, R 1,0 (3) =8, R 1,0 (4) =10,

R 2,0 (1) =0, R 2,0 (2) =9, R 2,0 (3) =13,

R 3,0 (1) =0, R 3,0 (2) =14.  (3)

where R i,j (k) is an index of a row where k th weight-1 is located in the j th column in the i th column group.

The weight-1 position sequence like Equation 3 which expresses an index of a row where 1 is located in the 0 th column of each column group may be briefly expressed as in Table 3 presented below:

Table 3 shows positions of elements having weight-1, that is, the value 1, in the parity check matrix, and the i th weight-1 position sequence is expressed by indexes of rows where weight-1 is located in the 0 th column belonging to the i th column group.

The information word submatrix 210 of the parity check matrix according to an exemplary embodiment may be defined as in Tables 4 to 11 presented below, based on the above descriptions.

Specifically, Tables 4 to 11 show indexes of rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 . That is, the information word submatrix 210 is formed of a plurality of column groups each including M number of columns, and positions of 1 in the 0 th column of each of the plurality of column groups may be defined by Tables 4 to 11.

Herein, the indexes of the rows where 1 is located in the 0 th column of the i th column group mean “addresses of parity bit accumulators”. The “addresses of parity bit accumulators” have the same meaning as defined in the DVB-C2/S2/T2 standards or the ATSC 3.0 standards which are currently being established, and thus, a detailed explanation thereof is omitted.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate R is 6/15, and M is 360, the indexes of the rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are as shown in Table 4 presented below:

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate R is 7/15, and M is 360, the indexes of the rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are as shown in Table 5 presented below:

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate R is 8/15, and M is 360, the indexes of the rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are as shown in Table 6 presented below:

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate R is 9/15, and M is 360, the indexes of the rows where 1 is located in the 0 th column of the i th column group of the information word submatrix 210 are as shown in Table 7 presented below:

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 10/15, and M is 360, the indexes of rows where 1 exists in the 0 th column of the i th column group of the information word submatrix 210 are defined as shown in Table 8 below.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 11/15, and M is 360, the indexes of rows where 1 exists in the 0 th column of the i th column group of the information word submatrix 210 are defined as shown in Table 9 below.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 12/15, and M is 360, the indexes of rows where 1 exists in the 0 th column of the i th column group of the information word submatrix 210 are defined as shown in Table 10 below.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 13/15, and M is 360, the indexes of rows where 1 exists in the 0 th column of the i th column group of the information word submatrix 210 are defined as shown in Table 11 below.

According to an exemplary embodiment, even when the order of numbers, i.e., indexes, in a sequence corresponding to the i th column group of the parity check matrix 200 as shown in the above-described Tables 4 to 11 is changed, the changed parity check matrix is a parity check matrix used for the same LDPC code. Therefore, a case in which the order of numbers in the sequence corresponding to the i th column group in Tables 4 to 11 is changed is covered by the inventive concept.

According to an exemplary embodiment, even when one sequence corresponding to one column group is changed and another sequence corresponding to another column group are changed to each other in Tables 4 to 11, cycle characteristics on a graph of the LDPC code and algebraic characteristics such as degree distribution are not changed. Therefore, a case in which the arrangement order of the sequences shown in Tables 4 to 11 is changed is also covered by the inventive concept.

In addition, even when a multiple of Q ldpc is equally added to all numbers, i.e., indexes, corresponding to a certain column group in Tables 4 to 11, the cycle characteristics on the graph of the LDPC code or the algebraic characteristics such as degree distribution are not changed. Therefore, a result of equally adding a multiple of Q ldpc to the sequences shown in Tables 4 to 11 is also covered by the inventive concept. However, it should be noted that, when the resulting value obtained by adding a multiple of Q ldpc to a given sequence is greater than or equal to (N ldpc −K ldpc ), a value obtained by applying a modulo operation for (N ldpc −K ldpc ) to the resulting value should be applied instead.

Once positions of the rows where 1 exists in the 0 th column of the i th column group of the information word submatrix 210 are defined as shown in Tables 4 to 11, positions of rows where 1 exists in another column of each column group may be defined since the positions of the rows where 1 exists in the 0 th column are cyclic-shifted by Q ldpc in the next column.

For example, in the case of Table 4, in the 0 th column of the 0 th column group of the information word submatrix 210 , 1 exists in the 1606 th row, 3402 th row, 4961 st row, . . . .

In this case, since Q ldpc =(N ldpc −K ldpc )/M=(64800−25920)/360=108, the indexes of the rows where 1 is located in the 1 st column of the 0 th column group may be 1714(=1606+108), 510(=3402+108), 5069(=4961+108), . . . , and the indexes of the rows where 1 is located in the 2 nd column of the 0 th column group may be 1822(=1714+108), 3618(=3510+108), 5177(=5069+108).

In the above-described method, the indexes of the rows where 1 is located in all rows of each column group may be defined.

The parity submatrix 220 of the parity check matrix 200 shown in FIG. 2 may be defined as follows:

The parity submatrix 220 includes N ldpc −K ldpc number of columns (that is, K ldpc th column to (N ldpc −1) th column), and has a dual diagonal or staircase configuration. Accordingly, the degree of columns except the last column (that is, (N ldpc −1) th column) from among the columns included in the parity submatrix 220 is 2, and the degree of the last column is 1.

As a result, the information word submatrix 210 of the parity check matrix 200 may be defined by Tables 4 to 11, and the parity submatrix 220 may have a dual diagonal configuration.

When the columns and rows of the parity check matrix 200 shown in FIG. 2 are permutated based on Equation 4 and Equation 5, the parity check matrix shown in FIG. 2 may be changed to a parity check matrix 300 shown in FIG. 3 .

Q ldpc ·i+j⇒M·j+i (0≤ i<M, 0≤ j<Q ldpc )  (4)

K ldpc +Q ldpc ·k+l⇒K ldpc +M·l+k (0≤ k<M, 0≤ l<Q ldpc )  (5)

The method for permutating based on Equation 4 and Equation 5 will be explained below. Since row permutation and column permutation apply the same principle, the row permutation will be explained by the way of an example.

In the case of the row permutation, regarding the X th row, i and j satisfying X=Q ldpc ×i+j are calculated and the X th row is permutated by assigning the calculated i and j to M×j+i. For example, regarding the 7 th row, i and j satisfying 7=2×i+j are 3 and 1, respectively. Therefore, the 7 th row is permutated to the 13 th row (10×1+3=13).

When the row permutation and the column permutation are performed in the above-described method, the parity check matrix of FIG. 2 may be converted into the parity check matrix of FIG. 3 .

Referring to FIG. 3 , the parity check matrix 300 is divided into a plurality of partial blocks, and a quasi-cyclic matrix of M×M corresponds to each partial block.

Accordingly, the parity check matrix 300 having the configuration of FIG. 3 is formed of matrix units of M×M. That is, the submatrices of M×M are arranged in the plurality of partial blocks, constituting the parity check matrix 300 .

Since the parity check matrix 300 is formed of the quasi-cyclic matrices of M×M, M number of columns may be referred to as a column block and M number of rows may be referred to as a row block. Accordingly, the parity check matrix 300 having the configuration of FIG. 3 is formed of N qc_column =N ldpc /M number of column blocks and N qc_row =N parity /M number of row blocks.

Hereinafter, the submatrix of M×M will be explained.

First, the (N qc_column −1) th column block of the 0 th row block has a form shown in Equation 6 presented below:

As described above, A 330 is an M×M matrix, values of the 0 th row and the (M−1) th column are all “0”, and, regarding 0≤i≤(M−2), the (i+1) th row of the i th column is “1” and the other values are “0”.

Second, regarding 0≤i≤(N ldpc −K ldpc )/M−1 in the parity submatrix 320 , the i th row block of the (K ldpc /M+i) th column block is configured by a unit matrix I M×M 340 . In addition, regarding 0≤i≤(N ldpc −K ldpc )/M−2, the (i+1) th row block of the (K ldpc /M+i) th column block is configured by a unit matrix I M×M 340 .

Third, a block 350 constituting the information word submatrix 310 may have a cyclic-shifted format of a cyclic matrix P, P a ij , or an added format of the cyclic-shifted matrix P a ij of the cyclic matrix P (or an overlapping format).

For example, a format in which the cyclic matrix P is cyclic-shifted to the right by 1 may be expressed by Equation 7 presented below:

The cyclic matrix P is a square matrix having an M×M size and is a matrix in which a weight of each of M number of rows is 1 and a weight of each of M number of columns is 1. When a ij is 0, the cyclic matrix P, that is, P 0 indicates a unit matrix I M×M , and when a ij is ∞, P ∞ is a zero matrix.

A submatrix existing where the i th row block and the j th column block intersect in the parity check matrix 300 of FIG. 3 may be P a ij . Accordingly, i and j indicate the number of row blocks and the number of column blocks in the partial blocks corresponding to the information word. Accordingly, in the parity check matrix 300 , the total number of columns is N ldpc =M×N qc_column , and the total number of rows is N parity =M×N qc_row . That is, the parity check matrix 300 is formed of N qc_column number of column blocks and N qc_row number of row blocks.

Referring back to FIG. 1 , the encoder 110 may perform the LDPC encoding by using various code rates such as 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, 13/15, etc. In addition, the encoder 110 may generate an LDPC codeword having various lengths such as 16200, 64800, etc., based on the length of the information word bits and the code rate.

In this case, the encoder 110 may perform the LDPC encoding by using the parity check matrix, and the parity check matrix is configured as shown in FIGS. 2 and 3 .

In addition, the encoder 110 may perform Bose, Chaudhuri, Hocquenghem (BCH) encoding as well as LDPC encoding. To achieve this, the encoder 110 may further include a BCH encoder (not shown) to perform BCH encoding.

In this case, the encoder 110 may perform encoding in an order of BCH encoding and LDPC encoding. Specifically, the encoder 110 may add BCH parity bits to input bits by performing BCH encoding and LDPC-encodes the bits to which the BCH parity bits are added into information word bits, thereby generating the LDPC codeword.

The interleaver 120 interleaves the LDPC codeword. That is, the interleaver 120 receives the LDPC codeword from the encoder 110 , and interleaves the LDPC codeword based on various interleaving rules.

In particular, the interleaver 120 may interleave the LDPC codeword such that a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword (that is, a plurality of bit groups or a plurality of blocks) is mapped onto a predetermined bit of a modulation symbol. Accordingly, the modulator 130 may map a bit included in a predetermined group from among the plurality of groups of the LDPC codeword onto a predetermined bit of the modulation symbol.

Hereinafter, the interleaver 120 will be explained in detail with reference to FIGS. 4 to 11 .

According to an exemplary embodiment, the interleaver 120 may interleave the LDPC codeword in a method described below such that a bit included in a predetermined group from among a plurality of groups constituting the interleaved LDPC codeword is mapped onto a predetermined bit in a modulation symbol. A detailed description thereof is provided with reference to FIG. 4 .

FIG. 4 is a block diagram to illustrate a configuration of an interleaver according to exemplary embodiment. Referring to FIG. 4 , the interleaver 120 includes a parity interleaver 121 , a group interleaver (or a group-wise interleaver 122 ), a group twist interleaver 123 and a block interleaver 124 .

The parity interleaver 121 interleaves parity bits constituting the LDPC codeword.

Specifically, when the LDPC codeword is generated based on the parity check matrix 200 having the configuration of FIG. 2 , the parity interleaver 121 may interleave only the parity bits of the LDPC codeword by using Equations 8 presented below:

u i =c i for 0≤ i<K ldpc , and

u K ldpc +M·t+s =c K ldpc +Q ldpc ·s+t for 0≤ s<M, 0≤ t<Q ldpc   (8),

where M is an interval at which a pattern of a column group, which includes a plurality of columns, is repeated in the information word submatrix 210 , that is, the number of columns included in a column group (for example, M=360), and Q ldpc is a size by which each column is cyclic-shifted in the information word submatrix 210 . That is, the parity interleaver 121 performs parity interleaving with respect to the LDPC codeword c=(c 0 , c 1 , . . . , c N ldpc −1 ), and outputs U=(u 0 , u 1 , . . . , u N ldpc −1 ).

When the LDPC codeword encoded based on the parity check matrix 200 of FIG. 2 is parity-interleaved based on Equations 8, the parity-interleaved LDPC codeword is the same as the LDPC codeword encoded by the parity check matrix 300 of FIG. 3 . Accordingly, when the LDPC codeword is generated based on the parity check matrix 300 of FIG. 3 , the parity interleaver 121 may be omitted.

The LDPC codeword parity-interleaved after having been encoded based on the parity check matrix 200 of FIG. 2 , or the LDPC codeword encoded based on the parity check matrix having the format of FIG. 3 may be characterized in that a predetermined number of continuous bits of the LDPC codeword have similar decoding characteristics (cycle distribution, a degree of a column, etc.).

For example, the LDPC codeword may have the same characteristics on the basis of M number of continuous bits. Herein, M is an interval at which a pattern of a column group is repeated in the information word submatrix and, for example, may be 360.

Specifically, a product of the LDPC codeword bits and the parity check matrix should be “0”. This means that a sum of products of the i th LDPC codeword bit, c i (i=0, 1, . . . , N ldpc −1) and the i th column of the parity check matrix should be a “0” vector. Accordingly, the i th LDPC codeword bit may be regarded as corresponding to the i th column of the parity check matrix.

In the case of the parity check matrix of FIG. 2 , M number of columns in the information word submatrix 210 belong to the same group and the information word submatrix 210 has the same characteristics on the basis of a column group (for example, the columns belonging to the same column group have the same degree distribution and the same cycle characteristic).

In this case, since M number of continuous bits in the information word bits correspond to the same column group of the information word submatrix 210 , the information word bits may be formed of M number of continuous bits having the same codeword characteristics. When the parity bits of the LDPC codeword are interleaved by the parity interleaver 121 , the parity bits of the LDPC codeword may be formed of M number of continuous bits having the same codeword characteristics.

In addition, in the case of the parity check matrix 300 of FIG. 3 , since the information word submatrix 310 and the parity submatrix 320 of the parity check matrix 300 have the same characteristics on the basis of a column group including M number of columns due to the row and column permutation, the information word bits and the parity bits of the LDPC codeword encoded based on the parity check matrix 300 are formed of M number of continuous bits of the same codeword characteristics.

Herein, the row permutation does not influence the cycle characteristic or algebraic characteristic of the LDPC codeword such as a degree distribution, a minimum distance, etc. since the row permutation is just to rearrange the order of rows in the parity check matrix. In addition, since the column permutation is performed for the parity submatrix 320 to correspond to parity interleaving performed in the parity interleaver 121 , the parity bits of the LDPC codeword encoded by the parity check matrix 300 of FIG. 3 are formed of M number of continuous bits like the parity bits of the LDPC codeword encoded by the parity check matrix 200 of FIG. 2 .

Accordingly, the bits constituting an LDPC codeword may have the same characteristics on the basis of M number of continuous bits, according to the present exemplary embodiment.

The group interleaver 122 may divide the LDPC codeword into a plurality of groups and rearrange the order of the plurality of groups or may divide the parity-interleaved LDPC codeword into a plurality of groups and rearrange the order of the plurality of groups. That is, the group interleaver 122 interleaves the plurality of groups in group units.

To achieve this, the group interleaver 122 divides the parity-interleaved LDPC codeword into a plurality of groups by using Equation 9 or Equation 10 presented below.

X j = { u k | j = ⌊ k 360 ⌋ , 0 ≤ k < N ldpc } ⁢ for ⁢ ⁢ 0 ≤ j < N group ( 9 ) X j = { u k | 360 × j ≤ k < 360 × ( j + 1 ) , 0 ≤ k < N ldpc } ⁢ ⁢ for ⁢

⁢ 0 ≤ j < N group ( 10 )

where N group is the total number of groups, X j is the j th group, and u k is the k th LDPC codeword bit input to the group interleaver 122 . In addition,

⌊ k 360 ⌋

is the largest integer below k/360.

Since 360 in these equations indicates an example of the interval M at which the pattern of a column group is repeated in the information word submatrix, 360 in these equations can be changed to M.

The LDPC codeword which is divided into the plurality of groups may be as shown in FIG. 5 .

Referring to FIG. 5 , the LDPC codeword is divided into the plurality of groups and each group is formed of M number of continuous bits. When M is 360, each of the plurality of groups may be formed of 360 bits. Accordingly, the groups may be formed of bits corresponding to the column groups of the parity check matrix.

Specifically, since the LDPC codeword is divided by M number of continuous bits, K ldpc number of information word bits are divided into (K ldpc /M) number of groups and N ldpc −K ldpc number of parity bits are divided into (N ldpc −K ldpc )/M number of groups. Accordingly, the LDPC codeword may be divided into (N ldpc /M) number of groups in total.

For example, when M=360 and the length N ldpc of the LDPC codeword is 64800, the number of groups N groups is 180, and, when the length N ldpc of the LDPC codeword is 16200, the number of groups N group is 45.

As described above, the group interleaver 122 divides the LDPC codeword such that M number of continuous bits are included in a same group since the LDPC codeword has the same codeword characteristics on the basis of M number of continuous bits. Accordingly, when the LDPC codeword is grouped by M number of continuous bits, the bits having the same codeword characteristics belong to the same group.

In the above-described example, the number of bits constituting each group is M. However, this is merely an example and the number of bits constituting each group is variable.

For example, the number of bits constituting each group may be an aliquot part of M. That is, the number of bits constituting each group may be an aliquot part of the number of columns constituting a column group of the information word submatrix of the parity check matrix. In this case, each group may be formed of aliquot part of M number of bits. For example, when the number of columns constituting a column group of the information word submatrix is 360, that is, M=360, the group interleaver 122 may divide the LDPC codeword into a plurality of groups such that the number of bits constituting each group is one of the aliquot parts of 360.

Hereinafter, the case in which the number of bits constituting a group is M will be explained for convenience of explanation.

Thereafter, the group interleaver 122 interleaves the LDPC codeword in group units. That is, the group interleaver 122 changes positions of the plurality of groups constituting the LDPC codeword and rearranges the order of the plurality of groups constituting the LDPC codeword.

In this case, the group interleaver 122 may rearrange the order of the plurality of groups by using Equation 11 presented below:

Y j =X π(j) (0= j<N group )  (11),

where X j is the j th group before group interleaving, and Y j is the j th group after group interleaving. In addition, π(j) is a parameter indicating an interleaving order and is determined by at least one of a length of an LDPC codeword, a code rate and a modulation method.

Accordingly, X π(j) is a π(j) th group before group interleaving, and Equation 11 means that the pre-interleaving π(j) th group is interleaved into the j th group.

According to an exemplary embodiment, an example of π(j) may be defined as in Tables 12 to 14 presented below.

In this case, π(j) is defined according to a length of an LPDC codeword and a code rate, and a parity check matrix is also defined according to a length of an LDPC codeword and a code rate. Accordingly, when LDPC encoding is performed based on a specific parity check matrix according to a length of an LDPC codeword and a code rate, the LDPC codeword may be interleaved in group units based on π(j) satisfying the corresponding length of the LDPC codeword and code rate.

For example, when the encoder 110 performs LDPC encoding at a code rate of 10/15 to generate an LDPC codeword of a length of 16200, the group interleaver 122 may perform interleaving by using π(j) which is defined according to the length of the LDPC codeword of 16200 and the code rate of 10/15 in tables 12 to 14 presented below.

For example, when the length of the LDPC codeword is 16200, the code rate is 10/15, and the modulation method is 16-Quadrature Amplitude Modulation (QAM), the group interleaver 122 may perform interleaving by using π(j) defined as in table 12.

An example of π(j) is as follows:

For example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 6/15, 7/15, 8/15 and 9/15, and the modulation method is 16-QAM, π(j) may be defined as in Table 12 presented below:

In the case of Table 12, Equation 11 may be expressed as Y 0 =X π(0) =X 3 , Y 1 =X π(1) =X 45 , Y 2 =X π(2) =X 175 , . . . , Y 178 =X π(178) =X 11 , and Y 179 =X π(179) =X 104 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of groups by changing the 3 th group to the 0 th group, the 45 th group to the 1 st group, the 175 th group to the 2 nd group, . . . , the 11 th group to the 178 th group, and the 104 th group to the 179 th group.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 10/15, 11/15, 12/15 and 13/15, and the modulation method is 16-QAM, π(j) may be defined as in Table 13 presented below:

In the case of Table 13, Equation 11 may be expressed as Y 0 =X π(0) =X 91 , Y 1 =X π(1) =X 161 , Y 2 =X π(2) =X 112 , . . . , Y 178 =X π(178) =X 10 , and Y 179 =X π(179) =X 8 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of groups by changing the 91 th group to the 0 th group, the 161 th group to the 1 st group, the 112 nd group to the 2 nd group, . . . , the 10 th group to the 178 th group, and the 8 th group to the 179 th group.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 6/15, 7/15, 8/15 and 9/15, and the modulation method is 256-QAM, π(j) may be defined as in Table 14 presented below.

In the case of Table 14, Equation 11 may be expressed as Y 0 =X π(0) =X 9 , Y 1 =X π(1) =X 6 , Y 2 =X π(2) =X 160 , . . . , Y 178 =X π(178) =X 177 , Y 179 =X π(179) =X 176 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of groups by changing the 9 th group to the 0 th group, the 6 th group to the 1 st group, the 160 st group to the 2 nd group, . . . , the 177 th group to the 178 th group, and the 176 th group to the 179 th group.

In another example, when the length N ldpc of the LDPC codeword is 64800, the code rate is 10/15, 11/15, 12/15 and 13/15, and the modulation method is 1024-QAM, π(j) may be defined as in Table 15 presented below:

In the case of Table 15, Equation 11 may be expressed as Y 0 =X π(0) =X 90 , Y 1 =X π(1) =X 28 , Y 2 =X π(2) =X 61 , . . . , Y 178 =X π(178) =X 19 , Y 179 =X π(179) =X 135 . Accordingly, the group interleaver 122 may rearrange the order of the plurality of groups by changing the 90 th group to the 0 th group, the 28 th group to the 1 st group, the 61 th group to the 2 nd group, . . . , the 19 th group to the 135 th group, and the 135 th group to the 179 th group.

As described above, the group interleaver 122 may rearrange the order of the plurality of groups by using Equation 11 and Tables 12 to 15.

On the other hand, since the order of the groups constituting the LDPC codeword is rearranged by the group interleaver 122 , and then the groups are block-interleaved by the block interleaver 124 , which will be described below, “Order of bits groups to be block interleaved” is set forth in Tables 12 to 15 in relation to π(j).

The LDPC codeword which is group-interleaved in the above-described method is illustrated in FIG. 6 . Comparing the LDPC codeword of FIG. 6 and the LDPC codeword of FIG. 5 before group interleaving, it can be seen that the order of the plurality of groups constituting the LDPC codeword is rearranged.

That is, as shown in FIGS. 5 and 6 , the groups of the LDPC codeword are arranged in order of group X 0 , group X 1 , . . . , group X Ngroup-1 before being group-interleaved, and are arranged in an order of group Y 0 , group Y 1 , . . . , group Y Ngroup-1 after being group-interleaved. In this case, the order of arranging the groups by the group interleaving may be determined based on Tables 12 to 15.

The group twist interleaver 123 interleaves bits in a same group. That is, the group twist interleaver 123 may rearrange the order of the bits in the same group by changing the order of the bits in the same group.

In this case, the group twist interleaver 123 may rearrange the order of the bits in the same group by cyclic-shifting a predetermined number of bits from among the bits in the same group.

For example, as shown in FIG. 7 , the group twist interleaver 123 may cyclic-shift bits included in the group Y 1 to the right by 1 bit. In this case, the bits located in the 0 th position, the 1 st position, the 2 nd position, . . . , the 358 th position, and the 359 th position in the group Y 1 as shown in FIG. 7 are cyclic-shifted to the right by 1 bit. As a result, the bit located in the 359 th position before being cyclic-shifted is located in the front of the group Y 1 and the bits located in the 0 th position, the 1 st position, the 2 nd position, . . . , the 358 th position before being cyclic-shifted are shifted to the right serially by 1 bit and located.

In addition, the group twist interleaver 123 may rearrange the order of bits in each group by cyclic-shifting a different number of bits in each group.

For example, the group twist interleaver 123 may cyclic-shift the bits included in the group Y 1 to the right by 1 bit, and may cyclic-shift the bits included in the group Y 2 to the right by 3 bits.

However, the above-described group twist interleaver 123 may be omitted according to circumstances.

In addition, the group twist interleaver 123 is placed after the group interleaver 122 in the above-described example. However, this is merely an example. That is, the group twist interleaver 123 changes only the order of bits in a certain group and does not change the order of the groups. Therefore, the group twist interleaver 123 may be placed before the group interleaver 122 .

The block interleaver 124 interleaves the plurality of groups the order of which has been rearranged.

Specifically, the block interleaver 124 is formed of a plurality of columns including a plurality of rows, respectively, and may divide each of the plurality of columns into a first part and a second part and perform a plurality of groups constituting the LDPC codeword.

In this case, the block interleaver 124 may interleave the plurality of groups the order of which has been rearranged by the group interleaver 122 .

Herein, the number of groups which are interleaved in group units may be determined by at least one of the number of rows and columns constituting the block interleaver 124 , the number of groups and the number of bits included in each group. In other words, the block interleaver 124 may determine the groups which are to be interleaved in group units considering at least one of the number of rows and columns constituting the block interleaver 124 , the number of groups and the number of bits included in each group, interleave the corresponding groups in group units, and divide and interleave the remaining groups. For example, the block interleaver 124 may interleave at least part of the plurality of groups in group units using the first part, and divide and interleave the remaining groups using the second part.

Meanwhile, interleaving groups in group units means that the bits included in the same group are written in the same column. In other words, the block interleaver 124 , in case of groups which are interleaved in group units, may not divide the bits included in the same groups and write the bits in the same column, and in case of groups which are not interleaved in group units, may divide the bits in the groups and write the bits in different columns.

Accordingly, in all groups interleaved by the first part, the bits included in the same group are written and interleaved in the same column of the first part, and in at least one group interleaved by the second part, the bits are divided and written in at least two columns.

Meanwhile, the number of rows constituting each column divided into the first part may be determined differently depending upon a modulation method, and the number of rows constituting each column divided into the second part may be determined depending upon the number of rows constituting each column divided into the first part. That is, each column divided into the first part may be formed of different number of rows depending upon a modulation method used by the modulator 130 , and each column divided into the second part may be formed of rows corresponding to the number of rows excluding the number of rows of each column divided in the first part from the number of the entire columns.

The specific interleaving method and structure will be described later.

Meanwhile, the group twist interleaver 123 changes only the order of bits in the same group and does not change the order of groups by interleaving. Accordingly, the order of the groups to be block-interleaved by the block interleaver 124 , that is, the order of the groups to be input to the block interleaver 124 , may be determined by the group interleaver 122 . Specifically, the order of the groups to be block-interleaved by the block interleaver 124 may be determined by π(j) defined in Tables 12 to 15.

As described above, the block interleaver 124 may be formed of a plurality of columns each including a plurality of rows, and may divide the plurality of columns into at least two parts and interleave an LDPC codeword.

For example, the block interleaver 124 may divide each of the plurality of columns into the first part and the second part, and may interleave a plurality of groups constituting the LDPC codeword.

In this case, the block interleaver 124 may divide each of the plurality of columns into N number of parts (N is an integer greater than or equal to 2) according to whether the number of groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124 , and may perform interleaving.

When the number of groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the block interleaver 124 , the block interleaver 124 may interleave the plurality of groups constituting the LDPC codeword in group units without dividing each of the plurality of columns into parts.

Specifically, the block interleaver 124 may interleave by writing the plurality of groups of the LDPC codeword on each of the columns in group units in a column direction, and reading each row of the plurality of columns in which the plurality of groups are written in group units in a row direction.

In this case, the block interleaver 124 may interleave by writing bits included in a predetermined number of groups which corresponds to a quotient obtained by dividing the number of groups of the LDPC codeword by the number of columns of the block interleaver 124 on each of the plurality of columns serially in a column direction, and reading each row of the plurality of columns in which the bits are written in a row direction.

Hereinafter, the group located in the j th position after being interleaved by the group interleaver 122 will be referred to as group Y j .

For example, it is assumed that the block interleaver 124 is formed of C number of columns each including R 1 number of rows. In addition, it is assumed that the LDPC codeword is formed of Y group number of groups and the number of groups Y group is a multiple of C.

In this case, the quotient obtained by dividing Y group number of groups constituting the LDPC codeword by C number of columns constituting the block interleaver 124 and thus, the block interleaver 124 may interleave by writing Y group /C number of groups on each column serially in a column direction and reading bits written on each column in a row direction.

For example, as shown in FIG. 8 , the block interleaver 124 writes bits included in group Y 0 , group Y 1 , . . . , group Y p−1 in the 1 st column from the 1 st row to the R 1 th row, writes bits included in group Y p , group Y p+1 , . . . , group Y q−1 in the 2 nd column from the 1 st row to the R 1 th row, . . . , and writes bits included in group Y z , Y z+1 , . . . , group Y Ngroup-1 in the column C from the 1 st row to the R 1 th row. The block interleaver 124 may read the bits written in each row of the plurality of columns in a row direction.

Accordingly, the block interleaver 124 interleaves all groups constituting the LDPC codeword in group units.

However, when the number of groups of the LDPC codeword is not an integer multiple of the number of columns of the block interleaver 124 , the block interleaver 124 may interleave a part of the plurality of groups of the LDPC codeword in group units by dividing each column into 2 parts, and divide and interleave the remaining groups. In this case, the bits included in the remaining groups, that is, the bits included in the number of groups which correspond to the remainder when the number of groups constituting the LDPC codeword is divided by the number of columns are not interleaved in group units, but interleaved by being divided according to the number of columns.

Specifically, the block interleaver 124 may interleave the LDPC codeword by dividing each of the plurality of columns into two parts.

In this case, the block interleaver 124 may divide the plurality of columns into a first part (part 1 ) and a second part (part 2 ) based on the number of columns of the block interleaver 124 , the number of groups of the LDPC codeword, and the number of bits of each of the plurality of groups.

Here, each of the plurality of groups may be formed of 360 bits. In addition, the number of groups of the LDPC codeword is determined based on the length of the LDPC codeword and the bits included in each group. For example, when an LDPC codeword in the length of 16200 is divided such that each group has 360 bits, the LDPC codeword is divided into 45 groups. Alternatively, when an LDPC codeword in the length of 64800 is divided such that each group has 360 bits, the LDPC codeword may be divided into 180 groups. Further, the number of columns constituting the block interleaver 124 may be determined according to a modulation method. This will be explained in detail below.

Accordingly, the number of rows constituting each of the first part and the second part may be determined based on the number of columns constituting the block interleaver 124 , the number of groups constituting the LDPC codeword, and the number of bits constituting each of the plurality of groups.

Specifically, in each of the plurality of columns, the first part may be formed of as many rows as the number of of bits included in at least one group which can be written in each column in group units from among the plurality of groups of the LDPC codeword, according to the number of columns constituting the block interleaver 124 , the number of groups constituting the LDPC codeword, and the number of bits constituting each group.

In each of the plurality of columns, the second part may be formed of rows excluding as many rows as the number of bits included in at least some groups which can be written in each of the plurality of columns in group units. Specifically, the number rows of the second part may be the same value as a quotient when the number of bits included in all bit groups excluding groups corresponding to the first part is divided by the number of columns constituting the block interleaver 124 . In other words, the number of rows of the second part may be the same value as a quotient when the number of bits included in the remaining groups which are not written in the first part from among groups constituting the LDPC codeword is divided by the number of columns.

That is, the block interleaver 124 may divide each of the plurality of columns into the first part including as many rows as the number of bits included in groups which can be written in each column in group units, and the second part including the other rows.

Accordingly, the first part may be formed of as many rows as the number of bits included in groups, that is, as many rows as an integer multiple of M. However, since the number of codeword bits constituting each group may be an aliquot part of M as described above, the first part may be formed of as many rows as an integer multiple of the number of bits constituting each group.

In this case, the block interleaver 124 may interleave by writing and reading the LDPC codeword in the first part and the second part in the same method.

Specifically, the block interleaver 124 may interleave by writing the LDPC codeword in the plurality of columns constituting each of the first part and the second part in a column direction, and reading the plurality of columns consisting the first part and the second part in which the LDPC codeword is written in a row direction.

That is, the block interleaver 124 may interleave by writing the bits included in at least some groups which can be written in each of the plurality of columns in group units in each of the plurality of columns of the first serially, dividing the bits included in the other groups except the at least some groups and writing in each of the plurality of columns of the second part in a column direction, and reading the plurality of columns constituting each of the first part and the second part in a row direction.

That is, the block interleaver 124 may perform interleaving by reading bits written in each of the plurality of columns constituting each of the first part and the second part in a column direction.

In this case, the block interleaver 124 may interleave by dividing the other groups except the at least some groups from among the plurality of groups based on the number of columns constituting the block interleaver 124 .

Specifically, the block interleaver 124 may interleave by dividing the bits included in the other groups by the number of a plurality of columns, writing each of the divided bits in each of a plurality of columns constituting the second part in a column direction, and reading the plurality of columns constituting the second part, where the divided bits are written, in a row direction.

That is, the block interleaver 124 may divide the bits included in the other groups except the groups written in the first part from among the plurality of groups of the LDPC codeword, that is, the bits in the number of groups which correspond to the remainder when the number of groups constituting the LDPC codeword is divided by the number of columns, by the number of columns, and may write the divided bits in each column of the second part serially in a column direction.

For example, it is assumed that the block interleaver 124 is formed of C number of columns each including R 1 number of rows. In addition, it is assumed that the LDPC codeword is formed of Y group number of groups, the number of groups Y group is not a multiple of C, and A×C+1=Y group (A is an integer greater than 0). In other words, it is assumed that when the number of groups constituting the LDPC codeword is divided by the number of columns, the quotient is A and the remainder is 1.

In this case, as shown in FIGS. 9 and 10 , the block interleaver 124 may divide each column into a first part including R 1 number of rows and a second part including R 2 number of rows. In this case, R 1 may correspond to the number of bits included in groups which can be written in each column in group units, and R 2 may be R 1 subtracted from the number of rows of each column.

That is, in the above-described example, the number of groups which can be written in each column in group units is A, and the first part of each column may be formed of as many rows as the number of bits included in A number of groups, that is, may be formed of as many rows as A×M number.

In this case, the block interleaver 124 writes the bits included in the groups which can be written in each column in group units, that is, A number of groups, in the first part of each column in the column direction.

That is, as shown in FIGS. 9 and 10 , the block interleaver 124 writes the bits included in each of group Y 0 , group Y 1 , . . . , group Y n−1 in the 1 st to R 1 th rows of the first part of the 1 st column, writes bits included in each of group Y n , group Y n+1 , . . . , group Y m−1 in the 1 st to R 1 th rows of the first part of the 2 nd column, . . . , writes bits included in each of group Y e , group Y e+1 , . . . , group Y Ngroup-2 in the 1 st to R 1 th rows of the first part of the column C.

As described above, the block interleaver 124 writes the bits included in the groups which can be written in each column in group units in the first part of each column in in group units.

In other words, in the above exemplary embodiment, the bits included in each of group (Y0), group (Y1), . . . , group (Yn−1) may not be divided and all of the bits may be written in the first column, the bits included in each of group (Yn), group (Yn+1), . . . , group (Ym-1) may not be divided and all of the bits may be written in the second column, and the bits included in each of group (Ye), group (Ye+1), . . . , group (YNgroup-2) may not be divided and all of the bits may be written in the C column. As such, all groups interleaved by the first part are written in the same column of the first part.

Thereafter, the block interleaver 124 divides bits included in the other groups except the groups written in the first part of each column from among the plurality of groups, and writes the bits in the second part of each column in the column direction. In this case, the block interleaver 124 divides the bits included in the other groups except the groups written in the first part of each column by the number of columns, so that the same number of bits are written in the second part of each column, and writes the divided bits in the second part of each column in the column direction.

Herein, each of the bits divided based on the number of columns may be referred to as a sub bit group and in this case, each sub bit group is written in each column of the second part.

In the above-described example, since A×C+1−Y group , when the groups constituting the LDPC codeword are written in the first part serially, the last group Y Ngroup-1 of the LDPC codeword is not written in the first part and remains. Accordingly, the block interleaver 124 divides the bits included in the group Y Ngroup-1 by C as shown in FIG. 9 , and writes the divided bits (that is, the bits corresponding to the quotient when the bits included in the last group (Y Ngroup-1 ) are divided by C) in the second part of each column serially.

That is, the block interleaver 124 writes the bits in the 1 st to R 2 th rows of the second part of the 1 st column, writes the bits in the 1 st to R 2 th rows of the second part of the 2 nd column, . . . , etc., and writes the bits in the 1 st to R 2 th rows of the second part of the column C. In this case, the block interleaver 124 may write the bits in the second part of each column in the column direction as shown in FIG. 9 .

That is, in the second part, the bits constituting the bit group may not be written in the same column and may be written in the plurality of columns. In other words, in the above example, the last group (Y Ngroup-1 ) is formed of M bits and thus, the bits included in the last group (Y Ngroup-1 ) may be divided by M/C and written in each column. In other words, the bits included in the last group (Y Ngroup-1 ) may be divided by M/C, the bits divided by M/C may form a sub bit group, and each sub bit group may be written in each column of the second part.

Accordingly, in at least some groups which are interleaved by the second part, the bits included in at least some groups are divided and written in at least two columns constituting the second part.

In the above-described example, the block interleaver 124 writes the bits in the second part in the column direction. However, this is merely an example. That is, the block interleaver 124 may write the bits in the plurality of columns of the second parts in a row direction. In this case, the block interleaver 124 may write the bits in the first part in the same method as described above.

Specifically, referring to FIG. 10 , the block interleaver 124 writes the bits from the 1 st row of the second part in the 1 st column to the 1 st row of the second part in the column C, writes the bits from the 2 nd row of the second part in the 1 st column to the 2 nd row of the second part in the column C, . . . , etc., and writes the bits from the R 2 th row of the second part in the 1 st column to the R 2 th row of the second part in the column C.

On the other hand, the block interleaver 124 reads the bits written in each row of each part serially in the row direction. That is, as shown in FIGS. 9 and 10 , the block interleaver 124 reads the bits written in each row of the first part of the plurality of columns serially in the row direction, and reads the bits written in each row of the second part of the plurality of columns serially in the row direction.

Accordingly, the block interleaver 124 may interleave a part of a plurality of groups constituting the LDPC codeword in group units, and divide and interleave the remaining groups.

As described above, the block interleaver 124 may interleave the plurality of groups in the methods described above with reference to FIGS. 8 to 10 .

In particular, in the case of FIG. 9 , the bits included in the group which does not belong to the first part are written in the second part in the column direction and read in the row direction. In view of this, the order of the bits included in the group which does not belong to the first part is rearranged. Since the bits included in the group which does not belong to the first part are interleaved as described above, Bit Error Rate (BER)/Frame Error Rate (FER) performance can be improved in comparison with a case in which such bits are not interleaved.

However, the group which does not belong to the first part may not be interleaved as shown in FIG. 10 . That is, since the block interleaver 124 writes and read the bits included in the group which does not belong to the first part on and from the second part in the row direction, the order of the bits included in the group which does not belong to the first part is not changed and the bits are output to the modulator 130 serially. In this case, the bits included in the group which does not belong to the first part may be output serially and mapped onto a modulation symbol.

In FIGS. 9 and 10 , the last single group of the plurality of groups is written in the second part. However, this is merely an example. The number of groups written in the second part may vary according to the total number of groups of the LDPC codeword, the number of columns and rows, the number of transmission antennas, etc.

The block interleaver 124 may have a different configuration according to whether bits included in a same group are mapped onto a single bit of each modulation symbol or bits included in a same group are mapped onto two bits of each modulation symbol.

On the other hand, in the case of a transceiving system using a plurality of antennas, the number of columns constituting the block interleaver 124 may be determined by considering the number of bits constituting a modulation symbol and the number of used antennas simultaneously. For example, when bits included in a same group are mapped onto a single bit in a modulation symbol and two antennas are used, the block interleaver 124 may determine the number of columns to be two times the number of bits constituting the modulation symbol.

First, when bits included in the same group are mapped onto a single bit of each modulation symbol, the block interleaver 124 may have configurations as shown in Tables 16 and 17:

Herein, C (or N C ) is the number of columns of the block interleaver 124 , R 1 is the number of rows constituting the first part in each column, and R 2 is the number of rows constituting the second part in each column.

Referring to Tables 16 and 17, the block interleaver 124 is formed of different number of rows depending upon a modulation method, the number of a plurality of columns has the same value as a modulation degree according to a modulation method, and each of a plurality of columns is formed of rows corresponding to the number of bits constituting the LDPC codeword divided by the number of a plurality of columns.

In addition, the first part is formed of rows as many as the number of bits included in a group which is writable in group units in each of a plurality of columns among a plurality of groups constituting an LDPC codeword, and thus, the number of columns varies depending upon a modulation degree. Accordingly, the number of rows constituting each column divided into the first part may be determined differently depending upon a modulation method.

In addition, the second part is formed of rows excluding the rows constituting the first part from the entire rows of each column, and thus, the number of rows constituting each column divided into the second part may be determined depending upon the number of rows constituting each column divided into the first part.

For example, when the length N ldpc of the LDPC codeword is 64800 and the modulation method is 16-QAM, the block interleaver 124 is formed of 4 columns as the modulation degree is 4 in the case of 16-QAM, and each column is formed of rows as many as R 1 +R 2 =16200(=64800/4) and may be the number of rows of the first part R 1 =16200(=360×45) and the number of rows of the second part R 2 =0.

Meanwhile, referring to Tables 16 and 17, when the number of groups constituting an LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 interleaves without dividing each column. Therefore, R 1 corresponds to the number of rows constituting each column, and R 2 is 0. In addition, when the number of groups constituting an LDPC codeword is not an integer multiple of the number of columns, the block interleaver 124 interleaves the groups by dividing each column into the first part formed of R 1 number of rows, and the second part formed of R 2 number of rows.

When the number of columns of the block interleaver 124 is equal to the number of bits constituting a modulation symbol, bits included in a same group are mapped onto a single bit of each modulation symbol as shown in Tables 16 and 17.

For example, when N ldpc =64800 and the modulation method is 16-QAM, the block interleaver 124 may use four (4) columns each including 16200 rows. In this case, a plurality of groups of an LDPC codeword are written in the four (4) columns in group units and bits written in the same row in each column are output serially. In this case, since four (4) bits constitute a single modulation symbol in the modulation method of 16-QAM, bits included in the same group, that is, bits output from a single column, may be mapped onto a single bit of each modulation symbol. For example, bits included in a group written in the 1 st column may be mapped onto the first bit of each modulation symbol.

On the other hand, when bits included in a same group are mapped onto two bits of each modulation symbol, the block interleaver 124 may have configurations as shown in Tables 18 and 19:

Herein, C (or N C ) is the number of columns of the block interleaver 124 , R 1 is the number of rows constituting the first part in each column, and R 2 is the number of rows constituting the second part in each column.

Referring to Tables 18 and 19, when the number of groups constituting an LDPC codeword is an integer multiple of the number of columns, the block interleaver 124 interleaves without dividing each column. Therefore, R 1 corresponds to the number of rows constituting each column, and R 2 is 0. In addition, when the number of groups constituting an LDPC codeword is not an integer multiple of the number of columns, the block interleaver 124 interleaves the groups by dividing each column into the first part formed of R 1 number of rows, and the second part formed of R 2 number of rows.

When the number of columns of the block interleaver 124 is half of the number of bits constituting a modulation symbol as shown in Tables 18 and 19, bits included in a same group are mapped onto two bits of each modulation symbol.

For example, when N ldpc =64800 and the modulation method is 16-QAM, the block interleaver 124 may use two (2) columns each including 32400 rows. In this case, a plurality of groups of an LDPC codeword are written in the two (2) columns in group units and bits written in the same row in each column are output serially. Since four (4) bits constitute a single modulation symbol in the modulation method of 16-QAM, bits output from two rows constitute a single modulation symbol. Accordingly, bits included in the same group, that is, bits output from a single column, may be mapped onto two bits of each modulation symbol. For example, bits included in a group written in the 1 st column may be mapped onto bits existing in any two positions of each modulation symbol.

Referring to Tables 16 to 19, the total number of rows of the block interleaver 124 , that is, R 1 +R 2 , is N ldpc /C.

In addition, the number of rows of the first part, R 1 , is an integer multiple of the number of bits included in each group, M (e.g., M=360), and maybe expressed as └N group /C┘×M, and the number of rows of the second part, R 2 , may be N ldpc /C−R 1 . Herein, └N group /C ┘ is the largest integer below N group /C. Since R 1 is an integer multiple of the number of bits included in each group, M, bits may be written in R 1 in group units.

In addition, when the number of groups of an LDPC codeword is not a multiple of the number of columns, it can be seen from Tables 16 to 19 that the block interleaver 124 interleaves a plurality of groups of the LDPC codeword by dividing each column into two parts.

Specifically, the length of an LDPC codeword divided by the number of columns is the total number of rows included in the each column. In this case, when the number of groups of the LDPC codeword is a multiple of the number of columns, each column is not divided into two parts. However, when the number of groups of the LDPC codeword is not a multiple of the number of columns, each column is divided into two parts.

For example, it is assumed that the number of columns of the block interleaver 124 is identical to the number of bits constituting a modulation symbol, and an LDPC codeword is formed of 64800 bits as shown in Table 16. In this case, each group of the LDPC codeword is formed of 360 bits, and the LDPC codeword is formed of 64800/360(=180) groups.

When the modulation method is 16-QAM, the block interleaver 124 may use four (4) columns and each column may have 64800/4(=16200) rows.

In this case, since the number of groups of an LDPC codeword divided by the number of columns is 180/4(=45), bits can be written in each column in group units without dividing each column into two parts. That is, bits included in 45 groups which is the quotient when the number of groups constituting the LDPC codeword is divided by the number of columns, that is, 45×360(=16200) bits can be written in each column.

However, when the modulation method is 256-QAM, the block interleaver 124 may use eight (8) columns and each column may have 64800/8(=8100) rows.

In this case, since the number of groups of an LDPC codeword divided by the number of columns is 180/8=22.5, the number of groups constituting the LDPC codeword is not an integer multiple of the number of columns. Accordingly, the block interleaver 124 divides each of the eight (8) columns into two parts to perform interleaving in group units.

In this case, since the bits should be written in the first part of each column in group units, the number of groups which can be written in the first part of each column in group units is 22 which is the quotient when the number of groups constituting the LDPC codeword is divided by the number of columns, and accordingly, the first part of each column has 22×360(=7920) rows. Accordingly, 7920 bits included in 22 groups may be written in the first part of each column.

The second part of each column has rows which are the rows of the first part subtracted from the total rows of each column. Accordingly, the second part of each column includes 8100−7920(=180) rows.

In this case, the bits included in the other group which has not been written in the first part are divided and written in the second part of each column.

Specifically, since 22×8(=176) groups are written in the first part, the number of groups to be written in the second part is 180-176 (=4) (for example, group Y 176 , group Y 177 , group Y 178 , and group Y 179 from among group Y 0 , group Y 1 , group Y 2 , . . . , group Y 178 , and group Y 179 constituting an LDPC codeword).

Accordingly, the block interleaver 124 may write the four (4) groups which have not been written in the first part and remains from among the groups constituting the LDPC codeword in the second part of each column serially.

That is, the block interleaver 124 may write 180 bits of the 360 bits included in the group Y 176 in the 1 st row to the 180 th row of the second part of the 1 st column in the column direction, and may write the other 180 bits in the 1 st row to the 180 th row of the second part of the 2 nd column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the group Y 177 in the 1 st row to the 180 th row of the second part of the 3 rd column in the column direction, and may write the other 180 bits in the 1 st row to the 180 th row of the second part of the 4 th column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the group Y 178 in the 1 st row to the 180 th row of the second part of the 5 th column in the column direction, and may write the other 180 bits in the 1 st row to the 180 th row of the second part of the 6 th column in the column direction. In addition, the block interleaver 124 may write 180 bits of the 360 bits included in the group Y 179 in the 1 st row to the 180 th row of the second part of the 7 th column in the column direction, and may write the other 180 bits in the 1 st row to the 180 th row of the second part of the 8 th column in the column direction.

Accordingly, the bits included in the group which has not been written in the first part and remains are not written in the same column in the second part and may be divided and written in the plurality of columns.

Hereinafter, the block interleaver of FIG. 4 according to an exemplary embodiment will be explained in detail with reference to FIG. 11 .

In a group-interleaved LDPC codeword (v 0 , v 1 , v N ldpc −1 ), Y j is continuously arranged like V={Y 0 , Y 1 , . . . Y N group −1 }.

The LDPC codeword after group interleaving may be interleaved by the block interleaver 124 as shown in FIG. 11 . In this case, the block interleaver 124 divide a plurality of columns into the first part(Part 1) and the second part(Part 2) based on the number of columns of the block interleaver 124 and the number of bits of groups. In this case, in the first part, the bits constituting groups may be written in the same column, and in the second part, the bits constituting groups may be written in a plurality of columns.

In the block interleaver 124 , the data bits vi from the group-wise interleaver 122 are written serially into the block interleaver column-wise starting in the first part and continuing column-wise finishing in the second part, and then read out serially row-wise from the first part and then row-wise from the second part. Accordingly, the bits included in the same group in the first part may be mapped onto single bit of each modulation symbol.

In this case, the number of columns and the number of rows of the first part and the second part of the block interleaver 124 vary according to a modulation method as in Table 20 presented below. The first part and the second part block interleaving configurations for each modulation format and code length are specified in Table 20. Herein, the number of columns of the block interleaver 124 may be equal to the number of bits constituting a modulation symbol. In addition, a sum of the number of rows of the first part, N r1 and the number of rows of the second part, N r2 , is equal to N ldpc /N C (herein, N C is the number of columns). In addition, since N r1 (=└N group /N c ┘×360) is a multiple of 360, so that multiple of bit groups are written into the first part of block interleaver.

Hereinafter, an operation of the block interleaver 124 will be explained in detail.

Specifically, as shown in FIG. 11 , the input bit v i (0≤i<N C ×N r1 ) is written in r i row of c i column of the first part of the block interleaver 124 . Herein, c i and r i are

c i = ⌊ i N r ⁢ ⁢ 1 ⌋

and r i =(i mod N r1 ), respectively.

In addition, the input bit v i (N C ×N r1 ≤i<N ldpc ) is written in an r i row of c i column of the second part of the block interleaver 124 . Herein, c i and r i are

c i = ⌊ ( i - N C × N r ⁢ ⁢ 1 ) N r ⁢ ⁢ 2 ⌋

and r i =N r1 +{(i−N C ×N r1 ) mod N r2 }, respectively.

An output bit q i (0≤j<N ldpc ) is read from c j column of r j row. Herein, r j and c j are

r j = ⌊ j N c ⌋

and c j =(j mod N C ), respectively.

For example, when the length N ldpc of an LDPC codeword is 64800 and the modulation method is 256-QAM, an order of bits output from the block interleaver 124 may be (q 0 , q 1 , q 2 , . . . , q 63357 , q 63358 , q 63359 , q 63360 , q 63361 , . . . , q 64799 )=(v 0 , v 7920 , v 15840 , . . . , v 47519 , v 55439 , v 63359 , v 63360 , v 63540 , . . . , v 64799 ). Herein, the indexes of the right side of the foregoing equation may be specifically expressed for the eight (8) columns as 0, 7920, 15840, 23760, 31680, 39600, 47520, 55440, 1, 7921, 15841, 23761, 31681, 39601, 47521, 55441, . . . , 7919, 15839, 23759, 31679, 39599, 47519, 55439, 63359, 63360, 63540, 63720, 63900, 64080, 64260, 64440, 64620, . . . , 63539, 63719, 63899, 64079, 64259, 64439, 64619, 64799.

Meanwhile, in the above example, the number of columns constituting the block interleaver 124 may be the same value as a modulation degree or half the modulation degree, but this is only an example. The number of columns constituting the block interleaver 124 may be a multiple value of the modulation degree. In this case, the number of rows constituting each column may be the length of the LDPC codeword divided by the number of columns.

For example, in case that the modulation method is QPSK (that is, the modulation degree is 2), the number of columns may be 4 instead of 2. In this case, if the length N ldpc of the LDPC codeword is 16200, the number of rows constituting each column may be 4050(=16200/4).

Meanwhile, even when the number of columns is the multiple value of the modulation degree, the block interleaver 124 may perform interleaving using the same method as when the number of columns is the same value as the modulation degree of half the modulation degree, so detailed description thereof will not be provided.

In this case, the number of columns constituting the block interleaver 124 may have the same value as the modulation degree or the integer multiple of the modulation degree and thus, the number of the second part may be the same value as a quotient when the number of bits included in all bit groups excluding groups corresponding to the first part is divided by the modulation degree or the multiple of the modulation degree.

Referring back to FIG. 1 , the modulator 130 modulates an interleaved LDPC codeword according to a modulation method to generate a modulation symbol. Specifically, the modulator 130 may demultiplex the interleaved LDPC codeword and modulate the demultiplexed LDPC codeword and map it onto a constellation, thereby generating a modulation symbol.

In this case, the modulator 130 may generate a modulation symbol using bits included in each of a plurality of groups.

In other words, as described above, the bits included in different groups are written in each column of the block interleaver 124 , and the block interleaver 124 reads the bits written in each column in a row direction. In this case, the modulator 130 generates a modulation symbol by mapping the bits read in each column onto each bit of the modulation symbol. Accordingly, each bit of the modulation symbol belongs to a different group.

For example, it is assumed that the modulation symbol consists of C bits (C refers to the number of bits). In this case, the bits which are read from each row of C columns of the block interleaver 124 may be mapped onto each bit of the modulation symbol and thus, each bit of the modulation symbol consisting of C bits belong to C different groups.

Hereinbelow, the above feature will be described in greater detail.

First, the modulator 130 demultiplexes the interleaved LDPC codeword. To achieve this, the modulator 130 may include a demultiplexer (not shown) to demultiplex the interleaved LDPC codeword.

The demultiplexer (not shown) demultiplexes the interleaved LDPC codeword. Specifically, the demultiplexer (not shown) performs serial-to-parallel conversion with respect to the interleaved LDPC codeword, and demultiplexes the interleaved LDPC codeword into a cell having a predetermined number of bits (or a data cell).

For example, as shown in FIG. 12 , the demultiplexer (not shown) receives the LDPC codeword Q=(q 0 , q 1 , q 2 , . . . ) output from the interleaver 120 , outputs the received LDPC codeword bits to one of a plurality of substreams serially, converts the input LDPC codeword bits into cells, and outputs the cells.

Herein, the number of substreams, N substreams , may be equal to the number of bits constituting a modulation symbol, η mod , and the number of bits constituting the cell may be equal to N ldpc /η mod . η mod varying according to a modulation method and the number of cells generated according to the length N ldpc of the LDPC codeword are as in Table 21 presented below:

Bits having the same index in each of the plurality of sub-streams may constitute a same cell. That is, in FIG. 12 , each cell may be expressed as (y 0,0 , y 1,0 , . . . , y ηMOD−1,0 ), (y 0,1 , y 1,1 , . . . , y ηMOD−1,1 ).

The demultiplexer (not shown) may demultiplex input LDPC codeword bits in various methods. That is, the demultiplexer (not shown) may change an order of the LDPC codeword bits and output the bits to each of the plurality of substreams, or may output the bits to each of the plurality of streams serially without changing the order of the LDPC codeword bits. These operations may be determined according to the number of columns used for interleaving in the block interleaver 124 .

Specifically, when the block interleaver 124 includes as many columns as half of the number of bits constituting a modulation symbol, the demultiplexer (not shown) may change the order of the input LDPC codeword bits and output the bits to each of the plurality of sub-streams. An example of a method for changing the order is illustrated in Table 22 presented below:

According to Table 22, when the modulation method is 16-QAM for example, the number of substreams is four (4) since the number of bits constituting the modulation symbol is four (4) in the case of 16-QAM. In this case, the demultiplexer (not shown) may output, from among the serially input bits, bits with an index i satisfying i mod 4=0 to the 0 th substream, bits with an index i satisfying i mod 4=1 to the 2 nd substream, bits with an index i satisfying i mode 4=2 to the 1 st substream, and bits with an index i satisfying i mode 4=3 to the 3 rd substream.

Accordingly, the LDPC codeword bits input to the demultiplexer (not shown), (q 0 , q 1 , q 2 , . . . ), may be output as cells like (y 0,0 , y 1,0 , y 2,0 , y 3,0 )=(q 0 , q 2 , q 1 , q 3 ), (y 0,1 , y 1,1 , y 2,1 , y 3,1 )=(q 4 , q 6 , q 5 , q 7 ), . . . .

When the block interleaver 124 includes the same number of columns as the number of bits constituting a modulation symbol, the demultiplexer (not shown) may output the input LDPC codeword bits to each of the plurality of streams serially without changing the order of the bits. That is, as shown in FIG. 13 , the demultiplexer (not shown) may output the input LDPC codeword bits (q 0 , q 1 , q 2 , . . . ) to each of the substreams serially, and accordingly, each cell may be configured as (y 0,0 , y 1,0 , . . . , y ηMOD−1,0 )=(q 0 , q 1 , . . . , q ηMOD−1 ), (y 0,1 , y 1,1 , . . . , y ηMOD−1,1 )=(q ηMOD , q ηMOD+1 , . . . , q 2×xηMOD−1 ), . . . .

In the above-described example, the demultiplexer (not shown) outputs the input LDPC codeword bits to each of the plurality of streams serially without changing the order of the bits. However, this is merely an example. That is, according to an exemplary embodiment, when the block interleaver 124 includes the same number of columns as the number of bits constituting a modulation symbol, the demultiplexer (not shown) may be omitted.

The modulator 130 may map the demultiplexed LDPC codeword onto modulation symbols. However, when the demultiplexer (not shown) is omitted as described above, the modulator 130 may map LDPC codeword bits output from the interleaver 120 , that is, block-interleaved LDPC codeword bits, onto modulation symbols.

The modulator 130 may modulate bits (that is, cells) output from the demultiplexer (not shown) in various modulation methods such as QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, 4096-QAM, etc. When the modulation method is QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM and 4096-QAM, the number of bits constituting a modulation symbol, η MOD (that is, a modulation degree), may be 2, 4, 6, 8, 10 and 12, respectively.

In this case, since each cell output from the demultiplexer (not shown) is formed of as many bits as the number of bits constituting a modulation symbol, the modulator 130 may generate a modulation symbol by mapping each cell output from the demultiplexer (not shown) onto a constellation point serially. Herein, a modulation symbol corresponds to a constellation point on the constellation.

However, when the demultiplexer (not shown) is omitted, the modulator 130 may generate modulation symbols by grouping a predetermined number of bits from interleaved bits serially and mapping the predetermined number of bits onto constellation points. In this case, the modulator 130 may generate the modulation symbols by using η MOD number of bits serially according to a modulation method.

The modulator 130 may modulate by mapping cells output from the demultiplexer (not shown) onto constellation points in a uniform constellation (UC) method.

The uniform constellation method refers to a method for mapping a modulation symbol onto a constellation point so that a real number component Re(z q ) and an imaginary number component Im(z q ) of a constellation point have symmetry and the modulation symbol is placed at equal intervals. Accordingly, at least two of modulation symbols mapped onto constellation points in the uniform constellation method may have the same demodulation performance.

Examples of the method for generating a modulation symbol in the uniform constellation method according to an exemplary embodiment are illustrated in Tables 23 to 30 presented below, and an example of a case of a uniform constellation 64-QAM is illustrated in FIG. 14 .

Tables 23 and 24 are used for determining a real number component Re(z q ) and an imaginary number component Im(z q ) when the modulation is performed in a QPSK method, Tables 25 and 26 are used for determining a real number component Re(z q ) and an imaginary number component Im(z q ) when the modulation is performed in a 16-QAM method, Tables 27 and 28 are used for determining a real number component Re(z q ) and an imaginary number component Im(z q ) when the modulation is performed in a 64-QAM method, and Tables 29 and 30 are used for determining a real number component Re(z q ) and an imaginary number component Im(z q ) when the modulation is performed in a 256-QAM method.

Referring to Tables 23 to 30, performance (e.g., reliability) varies according to whether a plurality of bits constituting a modulation symbol correspond to most significant bits (MSBs) or least significant bits (LSBs).

For example, in the case of 16-QAM, from among four (4) bits constituting a modulation symbol, each of the first and second bits determines a sign of each of the real number component Re(z q ) and the imaginary number component Im(z q ) of a constellation point onto which a modulation symbol is mapped, and the third and fourth bits determine a size of the constellation point onto which the modulation symbol is mapped.

In this case, the first and second bits for determining the sign from among the four (4) bits constituting the modulation symbol have a higher reliability than the third and fourth bits for determining the size.

In another example, in the case of 64-QAM, from among six (6) bits constituting a modulation symbol, each of the first and second bits determines a sign of each of the real number component Re(z q ) and the imaginary number component Im(z q ) of a constellation point onto which the modulation symbol is mapped. In addition, the third to sixth bits determine a size of the constellation point onto which the modulation symbol is mapped. From among these bits, the third and fourth bits determine a relatively large size, and the fifth and sixth bits determine a relatively small size (for example, the third bit determines which of sizes (−7, −5) and (−3, −1) corresponds to the constellation point onto which the modulation symbol is mapped, and, when (−7, −5) is determined by the third bit, the fourth bit determines which of −7 and −5 corresponds to the size of the constellation point.).

In this case, the first and second bits for determining the sign from among the six bits constituting the modulation symbol have the highest reliability, and the third and fourth bits for determining the relatively large size has the higher reliability than the fifth and sixth bits for determining the relatively small size.

As described above, in the case of the uniform constellation method, the bits constituting a modulation symbol have different reliability according to mapping locations in the modulation symbol.

The modulator 130 may modulate by mapping cells output from the demultiplexer (not shown) onto constellation points in a non-uniform constellation (NUC) method.

Specifically, the modulator 130 may modulate bits output from the demultiplexer (not shown) in various modulation methods such as non-uniform QPSK, non-uniform 16-QAM, non-uniform 64-QAM, non-uniform 256-QAM, non-uniform 1024-QAM, non-uniform 4096-QAM, etc.

Hereinafter, a method for generating a modulation symbol by using the non-uniform constellation method according to an exemplary embodiment will be explained.

First, the non-uniform constellation method has the following characteristics:

In the non-uniform constellation method, the constellation points may not regularly be arranged unlike in the uniform constellation method. Accordingly, when the non-uniform constellation method is used, performance for a signal-to-noise ratio (SNR) less than a specific value can be improved and a high SNR gain can be obtained in comparison to the uniform constellation method.

In addition, the characteristics of the constellation may be determined by one or more parameters such as a distance between constellation points. Since the constellation points are regularly distributed in the uniform constellation, the number of parameters for specifying the uniform constellation method may be one (1). However, the number of parameters necessary for specifying the non-uniform constellation method is relatively larger and the number of parameters increases as the constellation (e.g., the number of constellation points) increases.

In the case of the non-uniform constellation method, an x-axis and a y-axis may be designed to be symmetric to each other or may be designed to be asymmetric to each other. When the x-axis and the y-axis are designed to be asymmetric to each other, improved performance can be guaranteed, but decoding complexity may increase.

Hereinafter, an example of a case in which the x-axis and the y-axis are designed to be asymmetric to each other will be explained. In this case, once a constellation point of the first quadrant is defined, locations of constellation points in the other three quadrants may be determined as follows. For example, when a set of constellation points defined for the first quadrant is X, the set becomes −conj(X) in the case of the second quadrant, becomes conj(X) in the case of the third quadrant, and becomes −(X) in the case of the fourth quadrant.

That is, once the first quadrant is defined, the other quadrants may be expressed as follows:

1 Quarter (first quadrant)=X 2 Quarter (second quadrant)=−conj(X) 3 Quarter (third quadrant)=conj(X) 4 Quarter (fourth quadrant)=−X

Specifically, when the non-uniform M-QAM is used, M number of constellation points may be defined as z={z 0 , z 1 , . . . , z M-1 }. In this case, when the constellation points existing in the first quadrant are defined as {x 0 , x 1 , x 2 , . . . , x M/4-1 }, z may be defined as follows:

from z 0 to z M/4-1 =from x 0 to x M/4 from z M/4 to z 2×M/4-1 =−conj(from x 0 to x M/4 ) from z 2×M/4 to z 3×M/4-1 =conj(from x 0 to x M/4 ) from z 3×M/4 to z 4×M/4-1 =−(from x 0 to x M/4 )

Accordingly, the modulator 130 may map the bits [y 0 , . . . , y m−1 ] output from the demultiplexer (not shown) onto constellation points in the non-uniform constellation method by mapping the output bits onto Z L having an index of

L = ∑ i = 0 m - 1 ⁢ ( y 1 × 2 m - 1 ) .

An example of the constellation of the non-uniform constellation method is illustrated in FIGS. 15 to 19 .

An example of the method for modulating asymmetrically in the non-uniform constellation method in the modulator 130 is illustrated as in Tables 31 to 35 presented below. That is, according to an exemplary embodiment, modulation is performed in the non-uniform constellation method by defining constellation points existing in the first quadrant and defining constellations points existing in the other quadrants based on Tables 31 to 35.

In Tables 31 to 35, Table 31 indicates non-uniform QPSK, table 32 indicates non-uniform 16-QAM, Table 33 and Table 34 indicate non-uniform 64-QAM, and Table 35 indicates non-uniform 256-QAM, and in Tables 32 to 35, different mapping methods may be applied according to a code rate.

On the other hand, when the non-uniform constellation is designed to have the x-axis and the y-axis symmetric to each other, constellation points may be expressed similarly to those of uniform QAM and an example is illustrated as in Tables 36 to 38 presented below:

In Tables 36 to 38, Tables 36 and 37 are tables for determining the real number component Re(z q ) and the imaginary number component Im(z q ) when modulation is performed in the non-uniform 1024-QAM method. That is, Table 36 indicates the real number part of the 1024-QAM, and Table 37 indicates the imaginary number part of the 1024-QAM. In addition, Table 38 illustrate an example of a case in which modulation is performed in the non-uniform 1024-QAM method, and show x i values of Tables 36 and 37.

Since the non-uniform constellation method asymmetrically map the modulation symbol onto the constellation point as shown in Tables 36 to 38, modulation symbols mapped onto constellation points may have different decoding performance. That is, bits constituting a modulation symbol may have different performance.

For example, referring to FIG. 15 illustrating an example of a case in which modulation is performed in the non-uniform 64-QAM method, a modulation symbol 10 may be configured as (y 0 , y 1 , y 2 , y 3 , y 4 , y 5 )=(0, 0, 1, 0, 1, 0), and performance (e.g., capacity) of bits constituting the modulation symbol 10 may have a relationship of C(y 0 )>C(y 1 )>C(y 2 )>C(y 3 )>C(y 4 )>C(y 5 ).

In addition, it is obvious that the constellation in the uniform constellation method and the non-uniform constellation method may be rotated and/or scaled (herein, the same or different scaling factor may be applied to a real number axis and an imaginary number axis), and other variations can be applied. In addition, the illustrated constellation indicates relevant locations of the constellation points and another constellation can be derived by rotation, scaling and/or other appropriate conversion.

As described above, the modulator 130 may map modulation symbols onto constellation points by using uniform constellation methods and non-uniform constellation methods. In this case, bits constituting a modulation symbol may have different performance as described above.

LDPC codeword bits may have different codeword characteristics according to a configuration of a parity check matrix. That is, the LDPC codeword bits may have different codeword characteristics according to the number of 1 existing in the columns of the parity check matrix, that is, a column degree.

Accordingly, the interleaver 120 may interleave to map the LDPC codeword bits onto modulation symbols by considering both the codeword characteristic of the LDPC codeword bits and the reliability of the bits constituting a modulation symbol.

In particular, since bits constituting a modulation symbol have different performance when a non-uniform QAM is used, the block interleaver 124 configures the number of columns to be identical to the number of bits constituting a modulation symbol such that one of a plurality of groups of an LDPC codeword can be mapped onto bits each of which exists on a same location of each modulation symbol.

That is, when LDPC codeword bits of high decoding performance are mapped onto high reliability bits from among bits of each modulation symbol, a receiver side may show high decoding performance, but there is a problem that the LDPC codeword bits of the high decoding performance are not received. In addition, when the LDPC codeword bits of high decoding performance are mapped onto low reliability bits from among the bits of the modulation symbol, initial reception performance is excellent, and thus, overall performance is also excellent. However, when many bits showing poor decoding performance are received, error propagation may occur.

Accordingly, when LDPC codeword bits are mapped onto modulation symbols, an LDPC codeword bit having a specific codeword characteristic is mapped onto a specific bit of a modulation symbol by considering both codeword characteristics of the LDPC codeword bits and reliability of the bits of the modulation symbol, and is transmitted to a receiver side. Accordingly, the receiver side can achieve both the high reception performance and the high decoding performance.

In this case, since the LDPC codeword is divided into groups each formed of M (=360) number of bits having the same codeword characteristic and the bits are mapped respectively onto a bit of a specific location of each modulation symbol in group units, bits having a specific codeword characteristic can be mapped onto the specific location of each modulation symbol more effectively. In addition, the number of bits constituting the group may be an aliquot part of M as described above. However, the number of codeword bits constituting the group is limited to M for convenience of explanation.

That is, the modulator 130 can map at least one bit included in a predetermined group from among the plurality of groups constituting the LDPC codeword onto a predetermined bit of each modulation symbol. Herein, each of the plurality of groups may be formed of M (=360) number of bits.

For example, in the case of 16-QAM, at least one bit included in a predetermined group from among the plurality of groups may be mapped onto a first bit of each modulation symbol, or may be mapped onto a first bit and a second bit.

The modulator 130 can map at least one bit included in a predetermined group from among the plurality of groups onto a predetermined bit of each modulation symbol for the following reasons.

As described above, the block interleaver 124 interleaves a plurality of groups of an LDPC codeword in group units, the demultiplexer (not shown) demultiplexes bits output from the block interleaver 124 , and the modulator 130 maps demultiplexed bits (that is, cells) onto modulation symbols serially.

Accordingly, the group interleaver 122 , which is placed before the block interleaver 124 , interleaves the LDPC codeword in group units such that groups including bits to be mapped onto bits of specific locations of a modulation symbol can be written in the same column of the block interleaver 124 , considering a demultiplexing operation of the demultiplexer (not shown).

Specifically, the group interleaver 122 may rearrange the order of a plurality of groups of an LDPC codeword in group units such that at least one group including bits to be mapped onto the same location of different modulation symbols are serially arranged adjacent to one another, thereby allowing the block interleaver 122 to write a predetermined group on a predetermined column. That is, the group interleaver 122 interleaves the plurality of groups of the LDPC codeword in group units based on the above-described Tables 12 to 15, so that at least one group including bits to be mapped onto the same location of each modulation symbol are arranged to be adjacent to one another, and the block interleaver 124 interleaves by writing the adjacent at least one group on the same column.

Accordingly, the modulator 130 may generate a modulation symbol by mapping a bit output from a predetermined column of the block interleaver 124 onto a predetermined bit of the modulation symbol. In this case, bits included in one group may be mapped onto one bit of each modulation symbol or may be mapped onto two bits of each modulation symbol.

To explain detail, a case in which an LDPC codeword having a length of 64800 is modulated in the non-uniform 256-QAM method will be explained.

The group interleaver 122 divides the LDPC codeword into 64800/360(=180) groups, and interleaves the plurality of groups in group units.

In this case, the group interleaver 122 determines the number of groups to be written in each column of the block interleaver 124 based on the number of columns of the block interleaver 124 , and interleaves the plurality of groups in group units based on the determined number of groups.

Herein, groups written in a same column of the block interleaver 124 may be mapped onto a single specific bit or two specific bits from among bits constituting each modulation symbol according to the number of columns of the block interleaver 124 . Thus, the group interleaver 122 interleaves the plurality of groups in group units such that groups including bits required to be mapped onto a predetermined bit of each modulation symbol are adjacent to one another and serially arranged, considering bit characteristic of the modulation symbol. In this case, the group interleaver 122 may use the above-described Table 14 to perform interleaving.

Accordingly, the groups which are adjacent to one another in the LDPC codeword interleaved in group units may be written in the same column of the block interleaver 124 , and the bits written in the same column may be mapped onto a single specific bit or two specific bits of each modulation symbol by the modulator 130 .

For example, it is assumed that the block interleaver 124 includes as many columns as the number of bits constituting a modulation symbol, that is, eight (8) columns. In this case, each column of the block interleaver 124 may be divided into a first part including 7920 rows and a second part including 180 rows, as shown in Table 16 or Table 20.

Accordingly, the group interleaver 122 performs group interleaving such that 7920/360(=22) groups to be written in the first part of each column of the block interleaver 124 from among the plurality of groups are serially arranged to be adjacent to one another. Accordingly, the block interleaver 124 writes 22 groups on the first part of each column and divides the bits included in the other 4 groups and writes these bits on the second part of each column.

Thereafter, the block interleaver 124 reads the bits written in each row of the first part of the plurality of columns in the row direction, and reads the bits written in each row of the second part of the plurality of columns in the row direction.

That is, the block interleaver 124 may output the bits written in each row of the plurality of columns, from the bit written in the first row of the first column to the bit written in the first row of the sixth column, serially like (q 0 , q 1 , q 2 , q 3 , q 4 , q 5 , q 6 , q 7 , q 8 , q 9 , q 10 , q 11 , . . . ).

In this case, when the demultiplexer (not shown) is not used or the demultiplexer (not shown) outputs serially bits input to the demultiplexer (not shown) without changing the order of the bits, the LDPC codeword bits output from the block interleaver 124 , (q 0 , q 1 , q 2 , q 3 , q 4 , q 5 , q 6 , q 7 ), (q 8 , q 9 , q 10 , q 11 , q 12 , q 13 , q 14 , q 15 ), . . . , etc. are modulated by the modulator 130 . That is, the LDPC codeword bits output from the block interleaver 124 , (q 0 , q 1 , q 2 , q 3 , q 4 , q 5 , q 6 , q 7 ), (q 8 , q 9 , q 10 , q 11 , q 12 , q 13 , q 14 , q 15 ), . . . , etc. configure cells (y 0,0 , y 1,0 , . . . , y 7,0 ), (y 0,1 , y 1,1 , . . . , y 7,1 ), . . . , etc. and the modulator 130 generates a modulation symbol by mapping the cells onto constellation points.

Accordingly, the modulator 130 may map bits output from a same column of the block interleaver 124 onto a single specific bit of bits constituting each modulation symbol. For example, the modulator 130 may map bits included in a group written in the first column of the block interleaver 124 , that is, (q 0 , q 8 , . . . ), onto the first bit of each modulation symbol, and also, bits written in the first column may be bits which are determined to be mapped onto the first bit of each modulation symbol according to a codeword characteristic of the LDPC codeword bits and the reliability of the bits constituting the modulation symbol.

As described above, the group interleaver 122 may interleave a plurality of groups of an LDPC codeword in group units such that the groups including bits to be mapped onto a single bit of a specific location of each modulation symbol are written in a specific column of the block interleaver 124 .

Hereinafter, exemplary embodiments will be explained in detail.

First, according to an exemplary embodiment, it is assumed that the encoder 110 performs LDPC encoding at a code rate of 6/15, 7/15, 8/15 and 9/15 and generates an LDPC codeword formed of 64800 bits (N ldpc =64800), and the modulator 130 uses the non-uniform 256-QAM modulation method corresponding to the code rate based on Table 34.

In this case, the group interleaver 122 may perform group interleaving by using Equation 11 and Table 14. The block interleaver 124 in which the number of columns is eight (8), the number of rows of the first part is 7920(=360×22), and the number of rows of the second part is 180 according to Table 16 or 20 may be used.

Accordingly, 2 groups (X 9 , X 6 , X 160 , X 78 , X 1 , X 35 , X 102 , X 104 , X 86 , X 145 , X 111 , X 58 , X 166 , X 161 , X 92 , X 2 , X 124 , X 74 , X 117 , X 19 , X 168 , X 73 ) constituting an LDPC codeword are input to the first part of the first column of the block interleaver 124 , 22 groups (X 122 , X 32 , X 139 , X 42 , X 40 , X 105 , X 100 , X 144 , X 115 , X 154 , X 136 , X 97 , X 155 , X 24 , X 41 , X 138 , X 128 , X 89 , X 50 , X 80 , X 49 , X 26 ) are input to the first part of the second column of the block interleaver 124 , 22 groups (X 64 , X 75 , X 169 , X 146 , X 0 , X 33 , X 98 , X 72 , X 59 , X 120 , X 173 , X 96 , X 43 , X 129 , X 48 , X 10 , X 147 , X 8 , X 25 , X 56 , X 83 , X 16 ) are input to the first part of the third column of the block interleaver 124 , and 22 groups (X 67 , X 114 , X 112 , X 90 , X 152 , X 11 , X 174 , X 29 , X 110 , X 143 , X 5 , X 38 , X 85 , X 70 , X 47 , X 133 , X 94 , X 53 , X 99 , X 162 , X 27 , X 170 ) are input to the first part of the fourth column of the block interleaver 124 . In addition, 22 groups X 163 , X 57 , X 131 , X 34 , X 107 , X 66 , X 171 , X 130 , X 65 , X 3 , X 17 , X 37 , X 121 , X 18 , X 113 , X 51 , X 153 , X 101 , X 81 , X 123 , X 4 , X 21 ) are input to the first part of the fifth column of the block interleaver, 22 groups (X 46 , X 55 , X 20 , X 88 , X 15 , X 108 , X 165 , X 158 , X 87 , X 137 , X 12 , X 127 , X 68 , X 69 , X 82 , X 159 , X 76 , X 54 , X 157 , X 119 , X 140 , X 93 ) are input to the first part of the sixth column of the block interleaver 124 , 22 groups (X 106 , X 62 , X 95 , X 164 , X 141 , X 150 , X 23 , X 172 , X 91 , X 71 , X 61 , X 126 , X 60 , X 103 , X 149 , X 84 , X 118 , X 39 , X 77 , X 116 , X 22 , X 28 ) are input to the first part of the seventh column of the block interleaver 124 , and 22 groups (X 63 , X 45 , X 44 , X 151 , X 134 , X 52 , X 175 , X 142 , X 148 , X 167 , X 109 , X 31 , X 156 , X 14 , X 79 , X 36 , X 125 , X 135 , X 132 , X 30 , X 7 , X 13 ) are input to the first part of the eighth column of the block interleaver 124 .

In addition, groups X 179 , X 178 , X 177 , and X 176 are input to the second part of the block interleaver 124 . Specifically, bits constituting the group X 179 are input to the rows of the first column of the second part serially and input to the rows of the second column serially, bits constituting X 178 are input to the rows of the third column of the second part and input to the rows of the fourth column serially, bits constituting X 177 are input to the rows of the fifth column of the second part serially and input to the rows of the sixth column serially, and bits constituting X 176 are input to the rows of the seventh column of the second part serially and input to the rows of the eighth column serially. In this case, each of the groups X 179 , X 178 , X 177 , and X 176 is formed of 360 bits and 90 bits are input to the second part of each column.

In addition, the block interleaver 124 may output the bits input to the first row to the last row of each column serially, and the bits output from the block interleaver 124 may be input to the modulator 130 serially. In this case, the demultiplexer (not shown) may be omitted or the demultiplexer (not shown) may output the input bits serially without changing the order of the bits.

Accordingly, one bit included in each of groups X 9 , X 122 , X 64 , X 67 , X 163 , X 46 , X 106 , and X 63 constitute a single modulation symbol.

According to an exemplary embodiment, one bit included in each of the groups X 9 , X 122 , X 64 , X 67 , X 163 , X 46 , X 106 , and X 63 constitute constitute a single modulation symbol based on group interleaving and block interleaving. In addition to the above-described method, other methods for constituting a single modulation symbol with one bit included in each of the groups X 9 , X 122 , X 64 , X 67 , X 163 , X 46 , X 106 , and X 63 may be included in the inventive concept.

The transmitting apparatus 100 may modulate a signal mapped onto a constellation and may transmit the signal to a receiving apparatus (for example, a receiving apparatus 2700 of FIG. 20 ). For example, the transmitting apparatus 100 may map a signal mapped onto a constellation onto an Orthogonal Frequency Division Multiplexing (OFDM) frame by using the OFDM method, and may transmit the signal to the receiving apparatus 2700 via an allocated channel.

To achieve this, the transmitting apparatus 100 may further include a frame mapper (not shown) to map the signal mapped onto the constellation onto the OFDM frame, and a transmitter (not shown) to transmit the signal of the OFDM frame format to the receiving apparatus 2700 .

The bit interleaving method suggested in the exemplary embodiments is performed by the parity interleaver 121 , the group interleaver 122 , the group twist interleaver 123 , and the block interleaver 124 as shown in FIG. 4 (the parity interleaver 121 or group twist interleaver 123 may be omitted according to circumstances). However, this is merely an example and the bit interleaving method is not limited to three modules or four modules described above.

For example, when the block interleaver is used and the group interleaving method expressed as in Equation 11 is used, regarding the bit groups X j (0≤<N group ) defined as in Equation 9 and Equation 10, bits belonging to m number of bit groups, for example, {X π(i) , X π(a+i) , . . . , X π((m−1)×a+i) } (0≤i<a), may constitute a single modulation symbol.

Herein, a is the number of bit groups constituting the first part of the block interleaver, and a=└N group /m┘. In addition, m is the number of columns of the block interleaver and may be equal to the number of bits constituting the modulation symbol or half of the number of bits constituting the modulation symbol.

Therefore, for example, regarding parity-interleaved bits u i , {u π(i)+j , u π(a+i)+j , . . . , u π((m−1)×a+i)+j } (0<i≤m, 0<j≤M) may constitute a single modulation symbol. As described above, there are various methods for constituting a single modulation symbol.

FIG. 20 is a block diagram to illustrate a configuration of a receiving apparatus according to an exemplary embodiment. Referring to FIG. 20 , the receiving apparatus 2700 includes a demodulator 2710 , a multiplexer 2720 , a deinterleaver 2730 and a decoder 2740 .

The demodulator 2710 receives and demodulates a signal transmitted from the transmitting apparatus 100 . Specifically, the demodulator 2710 generates a value corresponding to an LDPC codeword by demodulating the received signal, and outputs the value to the multiplexer 2720 . In this case, the demodulator 2710 may use a demodulation method corresponding to a modulation method used in the transmitting apparatus 100 .

To do so, the transmitting apparatus 100 may transmit information regarding the modulation method to the receiving apparatus 2700 , or the transmitting apparatus 100 may perform demodulation using a pre-defined modulation method between the transmitting apparatus 100 and the receiving apparatus 2700 .

The value corresponding to the LDPC codeword may be expressed as a channel value for the received signal. There are various methods for determining the channel value, and for example, a method for determining a Log Likelihood Ratio (LLR) value may be the method for determining the channel value.

The LLR value is a log value for a ratio of the probability that a bit transmitted from the transmitting apparatus 100 is 0 and the probability that the bit is 1. In addition, the LLR value may be a bit value which is determined by a hard decision, or may be a representative value which is determined according to a section to which the probability that the bit transmitted from the transmitting apparatus 100 is 0 or 1 belongs.

The multiplexer 2720 multiplexes the output value of the demodulator 2710 and outputs the value to the deinterleaver 2730 .

Specifically, the multiplexer 2720 is an element corresponding to a demultiplexer (not shown) provided in the transmitting apparatus 100 , and performs an operation corresponding to the demultiplexer (not shown). Accordingly, when the demultiplexer (not shown) is omitted from the transmitting apparatus 100 , the multiplexer 2720 may be omitted from the receiving apparatus 2700 .

That is, the multiplexer 2720 converts the output value of the demodulator 2710 into cell-to-bit and outputs an LLR value on a bit basis.

In this case, when the demultiplexer (not shown) does not change the order of the LDPC codeword bits as shown in FIG. 13 , the multiplexer 2720 may output the LLR values serially on the bit basis without changing the order of the LLR values corresponding to the bits of the cell. Alternatively, the multiplexer 2720 may rearrange the order of the LLR values corresponding to the bits of the cell to perform an inverse operation to the demultiplexing operation of the demultiplexer (not shown) based on Table 22. Meanwhile, the information regarding whether the demultiplexing operation is performed may be provided by the transmitting apparatus 100 , or may be pre-defined between the transmitting apparatus 100 and the receiving apparatus 2700 .

The deinterleaver 2730 deinterleaves the output value of the multiplexer 2720 and outputs the values to the decoder 2740 .

Specifically, the deinterleaver 2730 is an element corresponding to the interleaver 120 of the transmitting apparatus 100 and performs an operation corresponding to the interleaver 120 . That is, the deinterleaver 2730 deinterleaves the LLR value by performing the interleaving operation of the interleaver 120 inversely.

To do so, the deinterleaver 2730 may include a block deinterleaver 2731 , a group twist deinterleaver 2732 , a group deinterleaver 2733 , and a parity deinterleaver 2734 as shown in FIG. 21 .

The block deinterleaver 2731 deinterleaves the output of the multiplexer 2720 and outputs a value to the group twist deinterleaver 2732 .

Specifically, the block deinterleaver 2731 is an element corresponding to the block interleaver 124 provided in the transmitting apparatus 100 and performs the interleaving operation of the block interleaver 124 inversely.

That is, the block deinterleaver 2731 deinterleaves by using at least one row formed of a plurality of columns, that is, by writing the LLR value output from the multiplexer 2720 in each row in the row direction and reading each column of the plurality of rows in which the LLR value is written in the column direction.

In this case, when the block interleaver 124 interleaves by dividing a column into two parts, the block deinterleaver 2731 may deinterleave by dividing a row into two parts.

Hereinafter, the block deinterleaver 2731 will be explained with reference to FIG. 22 . However, this is merely an example and the block deinterleaver 2731 may be implemented in other methods.

An input LLR v i (0≤i<N ldpc ) is written in a r i row and a c i column of the block deinterleaver 2431 . Herein, c i =(i mod N c ) and

On the other hand, an output LLR q i (0≤i<N c ×N r1 ) is read from a c i column and a r i row of the first part of the block deinterleaver 2431 . Herein,

c i = ⌊ i N r ⁢ ⁢ 1 ⌋ ,

r i =(i mod N r1 )

In addition, an output LLR q i (N c ×N r1 ≤i<N ldpc ) is read from a c i column and a r i row of the second part. Herein,

c i = ⌊ ( i - N c × N r ⁢ ⁢ 1 ) N r ⁢ ⁢ 2 ⌋ ,

r i =N r1 +{(i−N c ×N r1 ) mode N r2 }.

The group twist deinterleaver 2732 deinterleaves the output value of the block deinterleaver 2731 and outputs the value to the group deinterleaver 2733 .

Specifically, the group twist deinterleaver 2732 is an element corresponding to the group twist interleaver 123 provided in the transmitting apparatus 100 , and may perform the interleaving operation of the group twist interleaver 123 inversely.

That is, the group twist deinterleaver 2732 may rearrange the LLR values of the same group by changing the order of the LLR values existing in the same group. When the group twist operation is not performed in the transmitting apparatus 100 , the group twist deinterleaver 2732 may be omitted.

The group deinterleaver 2733 (or the group-wise deinterleaver) deinterleaves an output value of the group twist deinterleaver 2732 and outputs a value to the parity deinterleaver 2734 .

Specifically, the group deinterleaver 2733 is an element corresponding to the group interleaver 122 provided in the transmitting apparatus 100 and may perform the interleaving operation of the group interleaver 122 inversely.

That is, the group deinterleaver 2733 may rearrange the order of the plurality of groups in group units. In this case, the group deinterleaver 2733 may rearrange the order of the plurality of groups in group units by applying the interleaving method of Tables 12 to 15 inversely according to a length of the LDPC codeword, a modulation method and a code rate.

As described above, in the parity check matrix having the format shown in FIGS. 2 and 3 , the order of column groups is changeable and the column group corresponds to a bit group. Accordingly, when the order of column groups of the parity check matrix is changed, the order of bit groups is changed accordingly and the group deinterleaver 2733 may rearrange the order of the plurality of groups in group units with reference to this.

The parity deinterleaver 2734 performs parity deinterleaving with respect to an output value of the group deinterleaver 2733 and outputs a value to the decoder 2740 .

Specifically, the parity deinterleaver 2734 is an element corresponding to the parity interleaver 121 provided in the transmitting apparatus 100 and may perform the interleaving operation of the parity interleaver 121 inversely. That is, the parity deinterleaver 2734 may deinterleave the LLR values corresponding to the parity bits from among the LLR values output from the group deinterleaver 2733 . In this case, the parity deinterleaver 2734 may be omitted depending on the decoding method and embodiment of the decoder 2740 .

To do so, the transmitting apparatus 100 may transmit various pieces of information which are used for interleaving in the interleaver 120 to the receiving apparatus 2700 , or may perform interleaving using a pre-defined method between the transmitting apparatus 100 and the receiving apparatus 2700 .

Although the deinterleaver 2730 of FIG. 20 includes three (3) or four (4) elements as shown in FIG. 21 , operations of the elements may be performed by a single element. For example, when bits each of which belongs to each of bit groups X a , X b , X c , and X d constitute a single modulation symbol, the deinterleaver 2730 may deinterleave these bits to locations corresponding to their bit groups based on the received single modulation symbol.

For example, when a code rate is 7/15 and a modulation method is 256-QAM, the group deinterleaver 2733 may perform deinterleaving based on table 14.

In this case, bits each of which belongs to each of bit groups X 9 , X 122 , X 64 , X 67 , X 163 , X 46 , X 106 , and X 63 constitute a single modulation symbol. Since one bit in each of the bit groups X 9 , X 122 , X 64 , X 67 , X 163 , X 46 , X 106 , and X 63 constitutes a single modulation symbol, the deinterleaver 2730 may map bits onto decoding initial values corresponding to the bit groups X 9 , X 122 , X 64 , X 67 , X 163 , X 46 , X 106 , and X 63 based on the received single modulation symbol.

The decoder 2740 may perform LDPC decoding by using the output value of the deinterleaver 2730 . To achieve this, the decoder 2740 may include a separate LDPC decoder (not shown) to perform the LDPC decoding.

Specifically, the decoder 2740 is an element corresponding to the encoder 110 of the transmitting apparatus 200 and may correct an error by performing the LDPC decoding by using the LLR value output from the deinterleaver 2730 .

For example, the decoder 2740 may perform the LDPC decoding in an iterative decoding method based on a sum-product algorithm. The sum-product algorithm is one example of a message passing algorithm, and the message passing algorithm refers to an algorithm which exchanges messages (e.g., LLR value) through an edge on a bipartite graph, calculates an output message from messages input to variable nodes or check nodes, and updates.

The decoder 2740 may use a parity check matrix when performing the LDPC decoding. In this case, an information word submatrix in the parity check matrix is defined as in Tables 4 to 11 according to a code rate and a length of the LDPC codeword, and a parity submatrix may have a dual diagonal configuration.

In addition, information on the parity check matrix and information on the code rate, etc. which are used in the LDPC decoding may be pre-stored in the receiving apparatus 2700 or may be provided by the transmitting apparatus 100 .

FIG. 23 is a flowchart to illustrate a signal processing method according to an exemplary embodiment.

First of all, an LDPC codeword is generated by performing LDPC encoding (S3010).

Subsequently, the LDPC codeword is interleaved (S3020), and a modulation symbol is generated by modulating the interleaved LDPC codeword according to a modulation method (S3030).

Herein, in S 3020 , the interleaving may include interleaving an LDPC codeword by dividing each of a plurality of columns each including a plurality of rows into a first part and a second part. In this case, the number of rows constituting each column divided into the first part may be determined differently depending upon a modulation method, and the number of rows constituting each column divided into the second part may be determined depending upon the number of rows constituting each column divided into the first part.

To be specific, the number of the plurality of columns may have the same value as a modulation degree according to a modulation method, and each of the plurality of columns may be formed of rows corresponding to a value obtained by dividing the number of bits constituting an LDPC codeword by the number of the plurality of columns.

In addition, the first part may be formed of rows as many as the number of bits included in at least a part of bit groups which are writable in bit group units in each of the plurality of columns among a plurality of bit groups constituting the LDPC codeword, in each of the plurality of columns. In addition, the second part may be formed of rows excluding rows as many as the number of bits included in at least a part of bit groups which are writable in bit group units in each of the plurality of columns in rows constituting each of the plurality of columns, in each of the plurality of columns.

In this case, the number of rows of the second part may have the same value as a quotient obtained by dividing the number of bits included in all bits groups excluding a bit group corresponding to the first part by the number of the plurality of columns constituting the block interleaver.

Meanwhile, in S 3020 , the bits included in the at least a part of bits groups which are writable in the bit group units may be sequentially written in each of the plurality of columns constituting the first part, bits included in remaining bit groups excluding at least a part of bit groups from a plurality of bit groups may be divided based on the number of the plurality of columns, and the divided bits may be sequentially written in each of the plurality of columns constituting the second part.

In this case, in S 3020 , the interleaving may be performed by dividing the bits included in the remaining bit groups by the number of the plurality of columns, writing each of the divided bits in each of the plurality of columns constituting the second part in a column direction, and reading the plurality of columns constituting the first part and the second part in a row direction.

Meanwhile, in response to the modulation method being QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM, the modulation degree may be 2, 4, 6, 8, 10, and 12.

A non-transitory computer readable medium, which stores a program for performing the above signal processing methods according to various exemplary embodiments in sequence, may be provided.

The non-transitory computer readable medium refers to a medium that stores data semi-permanently rather than storing data for a very short time, such as a register, a cache, and a memory, and is readable by an apparatus. Specifically, the above-described various applications or programs may be stored in a non-transitory computer readable medium such as a compact disc (CD), a digital versatile disk (DVD), a hard disk, a Blu-ray disk, a universal serial bus (USB), a memory card, and a read only memory (ROM), and may be provided.

Components, elements or units represented by a block as illustrated in FIGS. 1, 4, 12, 13, and 23 may be embodied as the various numbers of hardware, software and/or firmware structures that execute respective functions described above, according to exemplary embodiments. For example, these components, elements or units may use a direct circuit structure, such as a memory, processing, logic, a look-up table, etc. that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. These components, elements or units may be specifically embodied by a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions. Also, at least one of the above components, elements or units may further include a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like.

Although a bus is not illustrated in the block diagrams of the transmitting apparatus and the receiving apparatus, communication may be performed between each element of each apparatus via the bus. In addition, each apparatus may further include a processor such as a Central Processing Unit (CPU) or a microprocessor to perform the above-described various operations.

The foregoing exemplary embodiments and advantages are merely exemplary and are not to be construed as limiting the present inventive concept. The exemplary embodiments can be readily applied to other types of apparatuses. Also, the description of the exemplary embodiments is intended to be illustrative, and not to limit the scope of the inventive concept, and many alternatives, modifications, and variations will be apparent to those skilled in the art.