LED drive circuit and method thereof

This application claims the benefit of Chinese Patent Application No. 201810534398.5, filed on May 29, 2018, which is incorporated herein by reference in its entirety.

The present invention generally relates to the field of power electronics, and more particularly to LED drivers and associated control methods.

A switched-mode power supply (SMPS), or a “switching” power supply, can include a power stage circuit and a control circuit. When there is an input voltage, the control circuit can consider internal parameters and external load changes, and may regulate the on/off times of the switch system in the power stage circuit. Switching power supplies have a wide variety of applications in modern electronics. For example, switching power supplies can be used to drive light-emitting diode (LED) loads.

FIG. 1 is a schematic block diagram of an example LED drive circuit.

FIG. 2 is a waveform diagram of example operation of the LED drive circuit shown in FIG. 1 .

FIG. 3 is a schematic block diagram of a first example LED drive circuit, in accordance with embodiments of the present invention.

FIG. 4 is a schematic block diagram of an example control circuit of the first example LED drive circuit shown in FIG. 3 , in accordance with embodiments of the present invention.

FIG. 5 is a schematic block diagram of an example clock generator of the example control circuit shown in FIG. 4 , in accordance with embodiments of the present invention.

FIG. 6 is a schematic block diagram of an example current feedback circuit of the example control circuit shown in FIG. 4 , in accordance with embodiments of the present invention.

FIG. 7 is a schematic block diagram of an example driver of the example control circuit shown in FIG. 4 , in accordance with embodiments of the present invention.

FIG. 8 is a waveform diagram of a first example operation mode of the first example LED drive circuit, in accordance with embodiments of the present invention.

FIG. 9 is a waveform diagram of a second example operation mode of the first example LED drive circuit, in accordance with embodiments of the present invention.

FIG. 10 is a schematic block diagram of a second example LED drive circuit, in accordance with embodiments of the present invention.

FIG. 11 is a schematic block diagram of an example control circuit of an example LED drive circuit, in accordance with embodiments of the present invention.

FIG. 12 is a schematic circuit diagram of a third example LED drive circuit, in accordance with embodiments of the present invention.

FIG. 13 is a waveform diagram of example operation of the third example LED drive circuit shown in FIG. 12 , in accordance with embodiments of the present invention.

Reference may now be made in detail to particular embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention may be described in conjunction with the preferred embodiments, it may be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it may be readily apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, processes, components, structures, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

Light-emitting diodes (LEDs) are widely used as light sources due to advantages of having high luminous efficiency, long life, and low power consumption. The LED load, as a constant current load, may be driven by a driver that can output a constant current. In FIG. 1 , shown is a schematic block diagram of an example LED drive circuit, and FIG. 2 shows a waveform diagram of example operation of the LED drive circuit of FIG. 1 . This example LED drive circuit can include sampling resistor Rcs and transistor Q 1 connected in series with an LED load. When the LED drive circuit is powered by an LED power source, the LED drive circuit can connect to an output end of rectification bridge BD, in order to obtain direct current bus voltage Vbus. Capacitor C 1 can connect to the output ends of the rectification bridge BD. During operation, transistor Q 1 in the LED drive circuit may operate in a linear mode/region. The operation state of transistor Q 1 can be controlled based on a feedback signal for an input current flowing through the transistor, in order to obtain a substantially constant input current.

In the linear drive manner, a relatively small number of devices are required, and the control is relatively simple. However, the voltage output by the rectification bridge may periodically fluctuate due to being a sinusoidal half-wave signal of a half power frequency period, which may result in periodical fluctuation of direct current bus voltage Vbus. In FIG. 2 , when direct current bus voltage Vbus is higher than load voltage Vled, the LED drive circuit can output a set/predetermined current. When direct current bus voltage Vbus approximates load voltage Vled, the current may be decreased as shown.

However, when the average of direct current bus voltage Vbus is much higher than load voltage Vled, the capacitance of capacitor C 1 may need to be increased in order to obtain constant current. This can result in increased loss of transistor Q 1 , and decreased overall system efficiency. Further, the power factor (PF) may be decreased due to the relatively large capacitance of capacitor C 1 . When the instantaneous value of direct current bus voltage Vbus approximates that of load voltage Vled, the input current may be decreased and the adjustment rate degraded. In this case, the current can approximately be in an open-loop state. If there is signal interference or grid jitter, the operation state of transistor Q 1 may not be controlled in time to adjust the input current, which can result in light flickering.

Referring now to FIG. 3 , shown is a schematic block diagram of a first example LED drive circuit, in accordance with embodiments of the present invention. In this particular example, LED drive circuit 100 can include a main circuit and control circuit 120 . The main circuit can include rectification bridge 110 , an LED load, transistor Q 1 , capacitor C 1 , and sampling resistor Rcs. The LED load, transistor Q 1 , and sampling resistor Rcs can connect in series between two output ends of rectification bridge 110 . Rectification bridge 110 can rectify alternating current input voltage Vac to acquire direct current bus voltage Vbus, and supply input current Iin to capacitor C 1 and the LED load. Capacitor C 1 can connect in parallel to the LED load, in order to smooth voltage Vled of the load. Input current Iin flowing through capacitor C 1 and the LED load may flow to a ground end via transistor Q 1 . Sampling resistor Rcs can obtain current sampling signal Vs of a current flowing through transistor Q 1 .

For example, transistor Q 1 may be implemented by a metal-oxide-semiconductor field-effect transistor (MOSFET). Those skilled in the art will recognize that transistor Q 1 may additionally or alternatively be implemented by other electronically controlled switches (e.g., a bipolar junction transistor [BJT], an insulated gate bipolar transistor [IGBT], a single MOSFET, a combination of multiple BJTs or MOSFETs, etc.). During operation, control circuit 120 in the LED drive circuit may generate drive signal Vg based on current sampling signal Vs, to control an operation state of transistor Q 1 , in order to control a load current flowing through the LED load. Since a value of the current flowing through transistor Q 1 may be equal to a value of input current Iin, the amount of accumulated charge of input current Iin during a half power frequency period can be controlled by controlling the operation state of transistor Q 1 , such that a distribution range of input current Iin can be controlled. This can improve a power factor and system efficiency of the LED drive circuit, and substantially avoid light flickering due to signal interference and/or grid jitter.

For example, control circuit 120 can control the amount of accumulated charge of input current Iin during the half power frequency period to be constant according to application environments of LED drive circuit 100 . Transistor Q 1 can be controlled so that a value of input current Iin in a first time period/duration (e.g., T 1 ) of the half power frequency period is greater than a value of input current Iin in a second time period/duration (e.g., T 1 ) of the half power frequency period. For example, in time period T 1 , transistor Q 1 can operate in a switching mode, and in time period T 2 , transistor Q 1 may operate in a linear mode. Time period T 1 may be before or after time period T 2 . For example, time period T 1 can be in a rising phase of direct current bus voltage Vbus, and time period T 2 after time period T 1 . Alternatively, time period T 1 can be in a falling phase of direct current bus voltage Vbus, and time period T 2 before time period T 1 . Control circuit 120 may perform the function of current integration control based on current sampling signal Vs of input current Iin in time period T 1 , to keep the amount of accumulated charge of input current Iin during time period T 1 constant. Control circuit 120 may perform the function of timing control in time period T 2 , in order to keep the amount of accumulated charge of input current Iin during time period T 2 constant.

Referring now to FIG. 4 , shown is a schematic block diagram of an example control circuit of the first example LED drive circuit shown in FIG. 3 , in accordance with embodiments of the present invention. In this particular example, control circuit 120 can include clock generator 121 , current feedback circuit 122 , logic circuit 123 , and driver 124 . For example, clock generator 121 may acquire alternating current input voltage Vac from alternating current input ends of rectification bridge 110 , and may generate clock signal CLK at a start time instant of the half power frequency period based on a sampling signal of alternating current input voltage Vac. Current feedback circuit 122 may acquire current sampling signal Vs from sampling resistor Rcs, and generate charge control signal CHG based on current sampling signal Vs and a current integration signal of current sampling signal Vs.

For example, logic circuit 123 may be an RS flip-flop. A set terminal and a reset terminal of the RS trigger can respectively connect to an output end of clock generator 121 and an output end of current feedback circuit 122 . Logic circuit 123 may generate, based on clock signal CLK and charge control signal CHG, control signals Vctr 1 and Vctr 2 , which are complementary to each other. Driver 124 can connect to output ends of logic circuit 123 , and may generate drive signal Vg based on at least one of control signals Vctr 1 and Vctr 2 . Further, current feedback circuit 122 can connect to the output end of logic circuit 123 , and current feedback circuit 122 may reset the current integration signal based on control signal Vctr 2 .

Referring now to FIG. 5 , shown is a schematic block diagram of an example clock generator of the example control circuit shown in FIG. 4 , in accordance with embodiments of the present invention. In this particular example, clock generator 121 can include a resistor divider network, comparator CMP 1 , and one-shot (pulse generator) circuit 1211 . For example, the resistor divider network can include resistors R 2 and R 4 connected in series, and resistor R 3 connected to a node between resistors R 2 and R 4 . Resistor R 4 may be grounded. Resistors R 2 and R 3 can respectively connect to two ends of alternating current input voltage Vac. Sampling signal Vbs of alternating current input voltage Vac may be obtained at the node between resistors R 2 and R 4 . A non-inverting input terminal of comparator CMP 1 can receive sampling signal Vbs of the alternating current input voltage, and an inverting input terminal of comparator CMP 1 can receive reference voltage Vst. Comparator CMP 1 can compare sampling signal Vbs of the alternating current input voltage against reference voltage Vst to generate a trigger signal. One-shot circuit 1211 can generate clock signal CLK in response to the trigger signal. For example, a pulse width of the trigger signal may be about 500 μs.

A period of clock signal CLK can be equal to the half power frequency period of direct current bus voltage Vbus. Clock signal CLK can trigger a single-pulse current in the rising phase of direct current bus voltage Vbus, such that time period T 1 begins. For example, a trigger time instant of clock signal CLK in the half power frequency period can be controlled by setting a value of reference voltage Vst, and the pulse width of clock signal CLK may be controlled by setting a delay time period of one-shot circuit 1211 . In this example, clock signal CLK may be generated based on voltage sampling signal Vbs indicating alternating current input voltage Vac. In other examples, voltage sampling signal Vbs may be obtained by sampling direct current bus voltage Vbus or voltage Vdrain across transistor Q 1 . For example, a diode can connect in series between the output end of rectification bridge 110 and an anode of the LED load, in order to prevent reverse flowing of the current.

Referring now to FIG. 6 , shown is a schematic block diagram of an example current feedback circuit of the example control circuit shown in FIG. 4 , in accordance with embodiments of the present invention. In this particular example, current feedback circuit 122 can include current integration circuit 1221 , closed-loop feedback circuit 1222 , and comparator CMP 2 . Current integration circuit 1221 can include error amplifier U 1 , capacitor C 2 , and transistor Q 2 . A non-inverting input terminal of error amplifier U 1 can receive current sampling signal Vs of the current flowing through transistor Q 1 , and an inverting input terminal of error amplifier U 1 may be grounded. Capacitor C 2 and transistor Q 2 can connect in parallel between an output terminal of error amplifier U 1 and ground. Current integration signal VA may be generated between two terminals of capacitor C 2 .

Closed-loop feedback circuit 1222 can include error amplifier U 2 , and capacitor C 3 . A non-inverting input terminal of error amplifier U 2 may be supplied with reference voltage VREF, and an inverting input terminal of error amplifier U 2 can receive current sampling signal Vs of the current flowing through transistor Q 1 . Capacitor C 3 can connect between an output terminal of error amplifier U 2 and ground. Compensation signal VC may be generated between two terminals of capacitor C 3 . Reference voltage VREF can indicate desired current value IREF. The compensation signal generated by error amplifier U 2 may indicate an error between an average of load current Iled and desired current value IREF. In this example, capacitor C 3 can average an error signal output by error amplifier U 2 . Those skilled in the art will recognize that resistor(s), inductor(s) and/or other capacitor(s) may be added in the compensation circuit according to the parameter/type of the signal output by the error amplifier.

An inverting input terminal of comparator CMP 2 can receive compensation signal VC, and a non-inverting input terminal of comparator CMP 2 can receive current integration signal VA. Comparator CMP 2 can compare compensation signal VC against current integration signal VA to generate charge control signal CHG. In time period T 1 , transistor Q 1 in the main circuit may be turned on and operate in the switching mode. In this case, a single-pulse current may be generated. Current integration circuit 1221 can integrate the single-pulse current. When current integration signal VA is increased to be a value greater than or equal to that of compensation signal VC, charge control signal CHG generated by comparator CMP 2 may transition from an inactive state to an active state.

Further, a control terminal of transistor Q 2 in the control circuit can connect to logic circuit 123 (see, e.g., FIG. 4 ), such that the operation state of transistor Q 2 may be related to control signal Vctr 2 generated by logic circuit 123 . In time period T 1 , transistor Q 2 can be turned off. Also, an output of current integration circuit 1221 can connect to an input end of comparator CMP 2 . Current integration circuit 1221 may integrate the single-pulse current. When current integration signal VA is increased to be a value greater than or equal to that of compensation signal VC, the state of charge control signal CHG may change, such that states of the control signals of logic circuit 123 are reversed. In this case, time period T 1 can end, and time period T 2 begin. Transistor Q 2 may be turned on due to control signal Vctr 2 of logic circuit 123 , such that the output of current integration circuit 1221 in current feedback circuit 122 is pulled down to ground. Capacitor C 2 can be discharged to ground, such that current integration signal VA is reset. Therefore, the amount of accumulated charge of input current Iin during time period T 1 (a time period/duration from time instant t 1 to time instant t 2 ) may be expressed as below in formula (1):

∫ t1 t2 g m I in R cs dt=C 2 VC   (1)

That is, as shown below in formula (2):

Here, gm represents a gain of current integration circuit 1221 , Rcs represents a sampling resistor, and VC represents a compensation signal. The amount of accumulated charge of input current Iin during time period T 1 may be kept constant.

Referring now to FIG. 7 , shown is a schematic block diagram of an example driver of the example control circuit shown in FIG. 4 , in accordance with embodiments of the present invention. In this particular example, driver 124 can include single-pulse circuit 1241 , timer 1242 , and current limiting circuit 1243 . Single-pulse circuit 1241 can include inverter U 3 , transistor Q 3 , current source A 1 , voltage sources Us 1 and Us 3 , capacitor C 4 , and diode D 1 . An input of inverter U 3 can receive control signal Vctr 1 , and an output of inverter U 3 can connect to a control terminal of transistor Q 3 . Current source A 1 and capacitor C 4 can connect in parallel between two power terminals of transistor Q 3 . Intermediate signal Vg 1 may be generated between two terminals of capacitor C 4 . Further, diode D 1 and voltage source Us 1 may form a high clamping circuit connected between the two terminals of capacitor C 4 . When intermediate signal Vg 1 is higher than high clamping signal Vhcmp provided by voltage source Us 1 , intermediate signal Vg 1 can be clamped at a value equal to Vhcmp+Vdiode, where Vdiode represents a forward voltage drop of diode D 1 . Voltage source Us 3 can be a voltage-controlled voltage source. One control terminal of voltage source Us 3 can receive intermediate signal Vg 1 , and the other control terminal of voltage source Us 3 may be grounded. Drive signal V 1 can be provided between two output terminals of voltage source Us 3 .

For example, timer 1242 may be a one-shot circuit. An input of timer 1242 can receive control signal Vctr 2 , and an output of timer 1242 may provide a timing signal. For example, the one-shot circuit may set a pulse width of the timing signal to be equal to Δt (e.g., about 3 ms), such that a predetermined delay time period can be obtained. Current limiting circuit 1243 can include inverter U 4 , transistor Q 4 , current source A 2 , voltage sources Us 2 and Us 4 , capacitor C 5 , and diode D 2 . An input of inverter U 4 can receive the timing signal, and an output of inverter U 4 can connect to a control terminal of transistor Q 4 . Current source A 2 and capacitor C 5 can connect in parallel between two power terminals of transistor Q 4 . Intermediate signal Vg 2 may be generated between two terminals of capacitor C 5 . Further, diode D 2 and voltage source Us 2 may form a low clamping circuit connected between the two terminals of capacitor C 5 .

When intermediate signal Vg 2 is higher than low clamping signal Vlcmp provided by voltage source Us 2 , intermediate signal Vg 2 can be clamped at a value equal to Vlcmp+Vdiode, where Vdiode represents a forward voltage drop of diode D 2 . Voltage source Us 4 can be a voltage-controlled voltage source. One control terminal of voltage source Us 4 may receive intermediate signal Vg 2 , and the other control terminal of voltage source Us 4 may be grounded. Drive signal V 2 having a preset pulse width Δt can be provided between two output terminals of voltage source Us 4 . Transistor Q 1 can generate a low clamp current Ilc under control of control signal V 2 , such that input current Iin may remain at low clamp current Ilc for a fixed duration Δt. Therefore, the amount of accumulated charge of input current Iin during time period T 2 (a time period/duration from time instant t 2 to a time instant t 3 ) may be expressed as below in formula (3):

∫ t2 t3 I in dt=I lc Δt   (3)

Here, Δt=t 3 −t 2 . The amount of accumulated charge of input current Iin during time period T 2 may remain constant. From the formulas (1)-(3), the amount Q of accumulated charge of input current Iin during the half power frequency period may be expressed as below in formula (4):

Q=∫I in=∫ t1 t2 I in dt|∫ t2 t3 I in dt= g m C 2 R cs VC |I lc Δt   (4)

A value of the amount Q of accumulated charge of input current Iin may be set by changing parameters in formula (4), such as by changing gain gm, sampling resistor Rcs or duration Δt of low clamp current Ilc. In one example, amount Q of accumulated charge of input current Iin during the half power frequency period can be controlled remain constant by setting various parameters.

In this example, control circuit 120 can control transistor Q 1 to generate the single-pulse current and the constant current respectively in time periods T 1 and T 2 that are consecutive in each half power frequency period of direct current bus voltage Vbus. Control circuit 120 can control a value of input current Iin to be relatively large when a voltage difference between two power terminals of transistor Q 1 is relatively small, and to control the value of input current Iin to be relatively small when the voltage difference between the two power terminals of transistor Q 1 is relatively large. For example, in time period T 1 , clock signal CLK may be generated based on voltage sampling signal Vbs of alternating current input voltage Vac, and time period T 1 may begin based on the clock signal, such that input current Iin flowing through transistor Q 1 is concentrated in a time period during which a turn-on voltage drop of transistor Q 1 is relatively small; that is, a time period during which a voltage difference between direct current bus voltage Vbus and load voltage Vled is relatively small.

In this case, the value of input current Iin is relatively large, and the amount of accumulated charge of input current Iin during time period T 1 may remain constant. In time period T 2 , the voltage difference between the two power terminals of transistor Q 1 is relatively large; that is, the difference between direct current bus voltage Vbus and load voltage Vled is relatively large. Charge control signal CHG may be generated based on current sampling signal Vs and current integration signal VA. Time period T 1 may end and time period T 2 begin based on charge control signal CHG. The value of input current Iin in time period T 2 may be relatively small and remain constant. Time periods T 2 in different half power frequency periods may have the same time length/duration, such that the amount of accumulated charge of input current Iin during time period T 2 remains constant.

In this example, voltage source Us 3 of single-pulse circuit 1241 and voltage source Us 4 of current limiting circuit 1243 can connect in series between the control terminal of transistor Q 1 and ground. In time period T 1 of the half power frequency period, voltage source Us 3 may provide drive signal V 1 as drive signal Vg. In time period T 2 of the half power frequency period, voltage source Us 4 may provide drive signal V 2 as drive signal Vg. In time period T 1 , transistor Q 1 can operate in the switching mode, in order to generate the single-pulse current. In time period T 2 , transistor Q 1 can operate in the linear mode/region, in order to generate the constant current.

Further, in time period T 1 , the current integration control may be performed based on the current sampling signal of the current flowing through transistor Q 1 , such that the amount of accumulated charge of input current Iin during time period T 1 remains constant. In time period T 2 , the timing control can be performed such that the amount of accumulated charge of input current Iin during time period T 2 remains constant. In this way, the amount of accumulated charge of input current Iin during the half power frequency period can be controlled to be constant, thereby achieving control for the current distribution range, and thus preventing light flickering that may be caused by the operation state of transistor Q 1 not being adjusted in time due to signal interference and/or grid jitter.

Referring now to FIG. 8 , shown is a waveform diagram of a first example operation mode of the first example LED drive circuit, in accordance with embodiments of the present invention. Here, |Vac| may represent an absolute value of an alternating current input voltage at input ends of the rectification bridge; that is, a theoretical output waveform of the rectification bridge. Vbus may represent a direct current bus voltage at an output of the rectification bridge. Vled may represent a terminal voltage between two terminals of the LED load. Iin may represent an input current (e.g., a current flowing through transistor Q 1 ). In addition, CLK may represent a clock signal generated based on alternating current input voltage Vac, VA and VC may respectively represent a current integration signal and a compensation signal generated based on current sampling signal Vs of input current Iin, and Vg may represent a drive signal of transistor Q 1 .

With reference to FIGS. 4-7 , the LED drive circuit in this example can include the main circuit and control circuit 120 . The main circuit can include rectification bridge 110 , the LED load, transistor Q 1 , capacitor C 1 , and sampling resistor Rcs. The LED load, transistor Q 1 , and sampling resistor Rcs can connect in series between the two outputs of rectification bridge 110 . Control circuit 120 may generate drive signal Vg based on current sampling signal Vs of the current flowing through transistor Q 1 , in order to control the operation state of the transistor Q 1 . In time period T 1 of the half power frequency period of direct current bus voltage Vbus, control circuit 120 may perform current integration control, such that transistor Q 1 operates in the switching mode to generate the single-pulse current. Further, the amount of accumulated charge of the single-pulse current during time period T 1 may be constant.

In time period T 2 of the half power frequency period of the direct current bus voltage Vbus, control circuit 120 may perform timing control, such that transistor Q 1 operates in the linear mode/region to generate the constant current. The amount of accumulated charge of the constant current during time period T 2 may remain constant. Clock generator 121 in control circuit 120 may generate clock signal CLK based on voltage sampling signal Vbs of alternating current input voltage Vac. Current feedback circuit 122 in control circuit 120 may generate current integration signal VA and compensation signal VC based on current sampling signal Vs of the current flowing through transistor Q 1 , and can generate charge control signal CHG based on a comparison result between current integration signal VA and compensation signal VC.

When transistor Q 1 is turned on, capacitor C 1 , the LED load and transistor Q 1 may form a current path. Rectification bridge 110 can supply input current Iin to capacitor C 1 and the LED load. One portion of input current Iin may flow to capacitor C 1 to charge capacitor C 1 . The other portion of input current Iin may flow to the LED load such that terminal voltage Vled of the LED load is increased to drive the LED to emit light. After flowing through capacitor C 1 and the LED load, input current Iin may flow to ground via transistor Q 1 . When transistor Q 1 is turned off, the current path between rectification bridge 110 , capacitor C 1 , and the LED load may be cut off, and input current Iin may decrease to zero. In this case, load current Iled can be supplied for the LED load by discharging capacitor C 1 , in order to drive the LED to continue to emit light, which may result in a decrease of the voltage across capacitor C 1 (e.g., a decrease of load voltage Vled). Further, direct current bus voltage Vbus may have a waveform that substantially periodically varies with a sinusoidal half-wave signal under the influence of alternating current input voltage Vac of rectification bridge 110 and the operation states of transistor Q 1 in the subsequent circuit.

As shown in FIG. 8 , a control period of drive signal Vg can be equal to the half power frequency period of direct current bus voltage Vbus, but the control period of drive signal Vg may have a delay with respect to the start time instant of the half power frequency period of direct current bus voltage Vbus. That is, a time length of the control period of drive signal Vg may be equal to a time length from time instant t 0 to time instant t 4 . At time instant t 0 , clock signal CLK may transition from an inactive state to an active state. Charge control signal CHG can be in an inactive state due to the reset of current integration signal VA. Drive signal Vg that is generated by control circuit 120 based on clock signal CLK and charge control signal CHG may be drive signal V 1 having a relatively high clamp value. Transistor Q 1 may be fully turned on and operate in the switching mode. In this example, when transistor Q 1 is turned on, absolute value |Vac| of alternating current input voltage Vac of the rectification bridge may be lower than direct current bus voltage Vbus. Thus, at time instant t 0 , although transistor Q 1 is turned on, rectification bridge 110 may not supply input current Iin to the LED load and capacitor C 1 . In this case, the value of input current Iin is zero, the load current Iled flowing through the LED load can be supplied by capacitor C 1 , and load voltage Vled and load current Iled may be decreased. For example, the pulse width of clock signal CLK may be about 500 μs.

Clock signal CLK may transition from the active state to the inactive state. At time instant t 1 , absolute value |Vac| of alternating current input voltage can be higher than load voltage Vled. Rectification bridge 110 may begin to supply input current Iin to capacitor C 1 and the LED load. In the rising phase of direct current bus voltage Vbus, load voltage Vled and load current Iled may continuously increase. Input current Iin can be increased with the sinusoidal half-wave waveform of direct current bus voltage Vbus, and load voltage Vled may also be increased. Direct current bus voltage Vbus can substantially change along with the waveform of the sinusoidal half-wave signal. In this case, the difference between load voltage Vled and direct current bus voltage Vbus may be relatively small, and input current Iin can be the single-pulse current having a relatively large value, such that that the power loss of transistor Q 1 may be relatively small. Correspondingly, current integration signal VA following load current Iled can be increased continuously, while compensation signal VC may substantially remain constant.

At time instant t 2 , since a value of current integration signal VA reaches a value equal to that of compensation signal VC, charge control signal CHG may transition from the inactive state to the active state. Clock signal CLK can be in the inactive state at this time. Drive signal Vg that is generated by control circuit 120 based on clock signal CLK and charge control signal CHG can be drive signal V 2 having a relatively low clamp value. Transistor Q 1 may generate the constant current and operate in the linear mode/region. Time instant t 2 can be an end time instant of time period T 1 , and also the start time instant of time period T 2 . During time period T 1 (e.g., a time period from time instant t 1 to time instant t 2 ), transistor Q 1 may operate in the switching mode, input current Iin can be the single-pulse current, the waveform of load voltage Vled of the LED load may be substantially the same as the sinusoidal half-wave waveform of direct current bus voltage Vbus, and load current Iled may linearly increase along with the sinusoidal half-wave waveform of direct current bus voltage Vbus.

At time instant t 3 , after a predetermined delay from time instant t 2 has elapsed, drive signal V 2 may transition from an active state to an inactive state, such that transistor Q 1 is turned off. Time instant t 3 can be an end time instant of time period T 2 . During time period T 2 (e.g., a time period from time instant t 2 to time instant t 3 ), transistor Q 1 may operate in the linear mode/region to limit the current, input current Iin can be a stable low clamp current, and load voltage Vled and current Iled flowing through the LED load may begin to decrease. During the time period from time instant t 3 to time instant t 4 , load current Iled and load voltage Vled can continuously be decreased, and input current Iin may decrease to zero. Direct current bus voltage Vbus may deviate from the standard half-wave signal waveform, and at time instant t 4 , a new control period may begin. Clock signal CLK may transition from the inactive state to the active state, such that transistor Q 1 is turned on again, and the control period/cycle repeated.

In particular embodiments, a balance between keeping the current constant and reducing power loss can be achieved in the LED drive circuit. In time period T 1 , the input current may be a single-pulse current, and the difference between load voltage Vled and direct current bus voltage Vbus can be relatively small; that is, the voltage difference between the two power terminals of transistor Q 1 is relatively small. In this way, heating generation and power loss due to the turn-on voltage drop of transistor Q 1 can be substantially reduced. In time period T 2 , the input current can be a constant current, and the difference between load voltage Vled and direct current bus voltage Vbus may be relatively large; that is, the voltage difference between the two power terminals of transistor Q 1 is relatively large. In this case, transistor Q 1 may operate in the linear mode to limit the current, and to widen the distribution range of input current Iin, thereby reducing harmonic distortion and increasing the power factor.

In particular embodiments, the LED drive circuit may perform current integration control in time period T 1 , in order to keep the amount of accumulated charge of the input current during time period T 1 constant. In addition, the LED drive circuit may perform timing control in time period T 2 , in order to keep the amount of accumulated charge of the input current during time period T 2 constant. In this way, the average of the load current may remain constant, and constant current control can be achieved, in order to avoid flickering when the input voltage fluctuates due to grid jitter and/or signal interference. In certain embodiments, in the LED drive circuit, by the current closed-loop control, the linear adjustment rate of the circuit system can be effectively improved, and the distribution range of input current Iin can be widened, thereby reducing the harmonic distortion and increasing the power factor.

Referring now to FIG. 9 , shown is a waveform diagram of a second example operation mode of the first example LED drive circuit, in accordance with embodiments of the present invention. In this particular example, the single-pulse current may also be distributed in the falling phase of direct current bus voltage Vbus. The control manner for the example shown in FIG. 9 may be similar to that for the example of FIG. 8 . In FIG. 9 , time period T 1 can be single-pulse current phase distributed in the falling phase of direct current bus voltage Vbus, and time period T 2 may be a constant current phase similar to that of the example shown in FIG. 8 , which may have substantially the same function for the LED drive circuit.

Referring now to FIG. 10 , shown is a schematic block diagram of a second example LED drive circuit, in accordance with embodiments of the present invention. In this particular example, LED drive circuit 200 can include a main circuit and control circuit 220 . The main circuit can include rectification bridge 210 , an LED load, capacitor C 1 , transistor Q 1 , and sampling resistor Rcs. The LED load, transistor Q 1 , and sampling resistor Rcs can connect in series between two outputs of rectification bridge 210 . The LED load and capacitor C 1 can connect in parallel.

In this example, control circuit 220 in the LED drive circuit may generate drive signal Vg based on current sampling signal Vs, to control the operation state of transistor Q 1 , in order to control the amount of accumulated charge of input current lin during a half power frequency period to be constant and to control the distribution range of input current Iin. This can improve the power factor and system efficiency of the LED drive circuit, and may prevent light flickering due to signal interference and/or grid jitter. Instead of control circuit 120 generating clock signal CLK based on voltage sampling signal Vbs indicating alternating current input voltage Vac, voltage sampling signal Vbs may be obtained by sampling drain voltage Vdrain of transistor Q 1 in this particular example. Therefore, diode D 0 can be connected in series between one output of rectification bridge 210 and an anode of the LED load, in order to prevent reverse flowing of the current. In other examples, voltage sampling signal Vbs may be obtained by sampling direct current bus voltage Vbus.

Referring now to FIG. 11 , shown is a schematic block diagram of an example control circuit of an example LED drive circuit, in accordance with embodiments of the present invention. In this particular example, control circuit 320 can include clock generator 321 , current feedback circuit 322 , logic circuit 323 , driver 324 , and counter 325 . Functions and operation principles of clock generator 321 , current feedback circuit 322 , logic circuit 323 , and driver 324 may be substantially the same as those described above. In this particular example, counter 325 may be included in control circuit 320 to generate a turn-off signal SHD, in order to control a turn-off time instant of transistor Q 1 . Control circuit 320 can control transistor Q 1 to generate a single-pulse current, a constant current, and a single-pulse current, respectively, in consecutive time periods T 1 , T 2 , and T 3 in a half power frequency period. For example, in time periods T 1 and T 3 , transistor Q 1 may operate in the switching mode, while in time period T 2 , transistor Q 1 may operate in the linear mode/region. For example, time period T 1 can be in a rising phase of direct current bus voltage Vbus, time period T 2 may be after time period T 1 , and time period T 3 may be in a falling phase of direct current bus voltage Vbus and after time period T 2 . Counter 325 can control transistor Q 1 to be turned off when time period T 3 ends.

Control circuit 320 can control a value of input current Iin to be relatively large when a voltage difference between two power terminals of the transistor Q 1 is relatively small, and to control the value of input current Iin to be relatively small when the voltage difference between the two power terminals of transistor Q 1 is relatively large. For example, in a rising phase or a falling phase of the half power frequency period, the voltage difference between the two power terminals of transistor Q 1 may be relatively small, and the value of input current Iin relatively large. In a peak time period of the half power frequency period, the voltage difference between the two power terminals of transistor Q 1 can be relatively large, and the value of input current Iin relatively small. For example, clock generator 321 may select one of clock signal clk 1 generated based on the sampling signal of alternating current input voltage Vac, and clock signal clk 2 generated by driver 324 , as clock signal CLK at a start time instant of the half power frequency period.

Current feedback circuit 322 may generate charge control signal CHG based on current sampling signal Vs and the current integration signal. Logic circuit 323 may generate, based on clock signal CLK and charge control signal CHG, complementary control signals Vctr 1 and Vctr 2 . Driver 324 can connect to outputs of logic circuit 323 , and driver 324 may generate drive signal Vg based on at least one of control signals Vctr 1 and Vctr 2 . Further, current feedback circuit 322 can connect to an output of logic circuit 323 , and current feedback circuit 322 may reset the current integration signal based on control signal Vctr 2 .

Counter 325 can receive charge control signal CHG generated by current feedback circuit 322 as a clock signal, and can count charge control signal CHG. The operation state of transistor Q 1 can be controlled by an output of counter 325 and drive signal Vg generated by driver 324 . When the count value of counter 325 reaches a predetermined value, counter 325 may activate turn-off signal SHD as drive signal Vg, in order to control transistor Q 1 to be turned off. A clear control end of counter 325 can connect to an input of clock generator 321 . When clock generator 321 selects clock signal clk 1 as clock signal CLK, clock signal clk 1 may be provided to counter 325 via the clear control end, in order to clear the count value.

Referring now to FIG. 12 , shown is a schematic circuit diagram of a third example LED drive circuit, in accordance with embodiments of the present invention. In this particular example, counter 325 , clock signal generator 3244 , and transistor Q 5 can be included in control circuit 320 . Driver 324 in control circuit 320 can include a single-pulse circuit, timer 3242 , a current limiting circuit, and clock signal generator 3244 . In driver 324 , clock signal generator 3244 can be provided after timer 3242 . For example, clock signal generator 3244 may be a one-shot circuit. An input of clock signal generator 3244 can connect to the output of inverter U 4 , and an output of clock signal generator 3244 may provide clock signal clk 2 . For example, the one-shot circuit may set a pulse width of the signal to be equal to Δt 1 , such as about 500 μs. Since clock signal generator 3244 may be arranged after timer 3242 and can connect to timer 3242 via inverter U 4 , clock signal generator 3244 may generate clock signal clk 2 when time period T 2 ends, to be provided to clock generator 321 .

OR-gate U 5 can be included in clock generator 321 . One-shot circuit 3211 may provide clock signal clk 1 . Clock signal generator 3244 may provide clock signal clk 2 . Two input terminals of OR-gate U 5 may respectively receive clock signals clk 1 and clk 2 . OR-gate U 5 can select one of clock signals clk 1 and clk 2 as clock signal CLK by performing a logic operation, and can provide the selected clock signal to the logic circuit 323 via an output terminal of OR-gate U 5 . For example, counter 325 can include a counter formed by two flip-flops. A counting input terminal CLK of counter 325 can receive charge control signal CHG as a clock signal, and counter 325 may count charge control signal CHG. An output terminal Q of the counter may provide turn-off signal SHD to driver 324 . Transistor Q 5 may be included in driver 324 and be connected between the control terminal of transistor Q 1 and ground. When transistor Q 5 is turned on by turn-off signal SHD at a control terminal thereof, the voltage at the control terminal of transistor Q 1 can be pulled down to ground, and transistor Q 1 can be turned off. Clear control terminal CLR of counter 325 can receive clock signal clk 1 as a clear signal.

For example, the resistor divider network of clock generator 321 may acquire alternating current input voltage Vac. Clock generator 321 can generate clock signal clk 1 as clock signal CLK via comparator CMP 1 and one-shot circuit 3211 . Clock signal CLK can be provided to logic circuit 323 at the start time instant of the half power frequency period, such that time period T 1 begins. Logic circuit 323 may generate control signal Vctr 1 based on clock signal CLK, and output control signal Vctr 1 to driver 324 . Counter 325 may clear the count value based on clock signal clk 1 and start to count. Driver 324 may generate drive signal Vg based on control signal Vctr 1 to turn on transistor Q 1 , in order to generate the single-pulse current. Current feedback circuit 322 can integrate sampling signal Vs of the input current. When current integration signal VA is increased to a value equal to a value of compensation signal VC, or a multiple of the value of compensation signal VC (VA=kVC), current feedback circuit 322 may activate charge control signal CHG provided to logic circuit 323 , such that logic circuit 323 may generate control signal Vctr 2 .

Charge control signal CHG may be output to counting input terminal CLK of counter 325 , such that “first” counting can begin. Driver 324 may generate drive signal Vg based on control signal Vctr 2 generated by logic circuit 323 , such that transistor Q 1 operates in the linear mode to generate a constant current at a clamp value, and time period T 2 may begin. Clock signal clk 2 may be generated by sampling an end time instant of time period T 2 . Clock generator 321 may select clock signal clk 2 as clock signal CLK, provide clock signal clk 2 to logic circuit 323 , and time period T 3 may begin. The control of clock signal clk 2 with respect to transistor Q 1 may be substantially the same as the control of clock signal clk 1 with respect to transistor Q 1 , such that transistor Q 1 may again be controlled to generate a single-pulse current.

Current feedback circuit 322 can integrate sampling signal Vs of the input current and may again activate charge control signal CHG. Since counter 325 may again count charge control signal CHG, and the “second” counting begins, the count value of counter 325 may reach a predetermined value (e.g., equal to 2) and counter 325 may activate turn-off signal SHD to transistor Q 5 according to the settings. Thus, the voltage of the control terminal of transistor Q 1 may be pulled down to ground and transistor Q 1 turned off. In this case, the current path can be cut off, the LED load may be supplied by capacitor C 1 , and the operation process in the half power frequency period completes until a next clock signal CLK.

Therefore, in this example, the amount of accumulated charge of input current Iin may be expressed as follows:

Parameters in this formula are the same as those in the above example, where T 3 =t 4 −t 3 , and Δt=t 3 −t 2 . Accordingly, the amount of accumulated charge of input current Iin during the half power frequency period may be constant to prevent light flickering, which can be caused by the operation state of transistor Q 1 not being adjusted in time due to signal interference and/or grid jitter.

Referring now to FIG. 13 , shown is a waveform diagram of example operation of the third example LED drive circuit shown in FIG. 12 , in accordance with embodiments of the present invention. In this example, a control period of drive signal Vg can be equal to the half power frequency period of direct current bus voltage Vbus, but the control period of drive signal Vg may have a delay with respect to the start time instant of the half power frequency period of direct current bus voltage Vbus. That is, a time length of the control period of drive signal Vg can be equal to a time length from time instant t 0 to time instant t 5 . At time instant t 3 , time period T 2 ends; that is, the low clamp current time period ends. Clock signal generator 3244 may obtain the end time instant of the fixed low clamp time period by performing sampling and can activate clock signal clk 2 , such that clock signal CLK transitions from an inactive state to an active state. Charge control signal CHG may be in an inactive state due to the reset of current integration signal VA. Drive signal Vg that is generated by control circuit 320 based on clock signal CLK and charge control signal CHG may be drive signal V 1 having a high clamp value. Time period T 3 can begin, and transistor Q 1 may gradually be turned on to operate in the switching mode.

In a time period from time instant t 3 to time instant t 4 , current integration signal VA may be continuously increased, while compensation signal VC may substantially remain constant. At time instant t 4 , VA=kVC. Counter 325 may perform the second counting on charge control signal CHG. When VA=kVC, an edge of charge control signal CHG arrives, turn-off signal SHD may be activated, transistor Q 5 can be turned on, drive signal Vg may be low, and transistor Q 1 can be turned off. In this case, the load current of the LED load can be supplied by capacitor C 1 , and time period T 3 ends. Transistor Q 5 can be maintained in the turn-off state until time instant t 5 , and then the operation process in the half power frequency period can complete.

At time instant t 5 , a new control period may begin. Clock signal CLK may transition from the inactive state to the active state, such that transistor Q 1 is turned on again. An edge of clock signal clk 1 may arrive, the count value of counter 325 can be cleared, and the counting restarted. The control period/cycle can be repeated. In the LED drive circuit, in time periods T 1 and T 3 , input current Iin may be a single-pulse current, and the difference between load voltage Vled and direct current bus voltage Vbus can be relatively small; that is, the voltage difference between the two power terminals of transistor Q 1 may be relatively small. In this way, heating generation and loss due to the turn-on voltage drop of transistor Q 1 can be greatly reduced. In time period T 2 , input current Iin may be constant low clamp current Ilc, and the difference between load voltage Vled and direct current bus voltage Vbus can be relatively large; that is, the voltage difference between the two power terminals of transistor Q 1 is relatively large. Transistor Q 1 can operate in the linear mode to limit the current to widen the distribution range of input current Iin and increase the power factor of the system.

Further, the LED drive circuit can perform current integration control in time periods T 1 and T 3 , to keep the amount of accumulated charge of the single-pulse current during time periods T 1 and T 3 constant. In addition, the LED drive circuit can perform timing control in time period T 2 , to keep the amount of accumulated charge of the constant current during time period T 2 constant. In this way, the average of the load current can remain constant, and constant current control can be achieved, such that that no flickering occurs when the input voltage fluctuates due to grid jitter and/or signal interference.

In particular embodiments, an example control method applied to control an LED driver can include, at a first step, a transistor (e.g., Q 1 ) and an LED load connected in series with each other may receive a direct current bus voltage (e.g., Vbus) to generate an input current (e.g., Iin). At a second step, an operation state of the transistor may be controlled to adjust a distribution range of the input current by controlling the amount of accumulated charge of an input current during a half power frequency period. In addition, the transistor can be controlled to operate in a switching mode in a first time period (e.g., T 1 ) to keep the input current as a single pulse current, and to operate in a linear mode in a second time period (e.g., T 2 ) to keep the input current constant. Further, the input current can be controlled to be relatively large when a voltage difference between two power terminals of the transistor is relatively small, and controlled to be relatively small when the voltage difference between the two power terminals of the transistor is relatively large.

For example, the transistor may operate in the switching mode such that the amount of accumulated charge of the input current is constant during the first time period by integrating a current sampling signal (e.g., Vs) of the input current flowing through the transistor. Also, the transistor may operate in a linear mode such that the amount of accumulated charge of the input current is constant during the second time period by controlling corresponding second time periods of different half power frequency periods to have the same time length. In addition, the first time period may be in a rising phase of the direct current bus voltage, and the second time period follows the first time period. In particular embodiments, the first time period may be in a falling phase of the direct current bus voltage, and the second time period may be before the first time period. Further, the transistor can operate in the switching mode again, such that the amount of accumulated charge of the input current is constant during a third time period (e.g., T 3 ) by integrating the current sampling signal of the input current flowing through the transistor. In addition, the first time period may be in the rising phase of the direct current bus voltage, the second time period can be after the first time period, and the third time period may be in the falling phase of the direct current bus voltage.

For example, a clock signal (e.g., CLK) can be generated based on a sampling signal of an alternating current input voltage, where the clock signal indicates a start time instant of the first time period. Alternatively, the clock signal may be generates based on a sampling signal of the direct current bus voltage or a drain voltage of the transistor. A charge control signal (e.g., CHG) may be generated based on the current sampling signal and a current integration signal of the current sampling signal, where the charge control signal indicates a start time instant of the second time period. First and second control signals (e.g., Vctr 1 and Vctr 2 ) that are complementary may be generated based on the clock signal and the charge control signal. Further, the drive signal (e.g., Vg) may be generated based on the first and second control signals, in order to control the transistor to operate in the switching mode in the first time period and control the transistor to operate in the linear mode in the second time period. In addition, a current integration signal (e.g., VA) may be generated by integrating the current sampling signal. A compensation signal (e.g., VC) may be generated based on an error between the current sampling signal and a reference voltage (e.g., VREF). In this way, the charge control signal may be generated by comparing the compensation signal against the current integration signal. In addition, a first drive signal as the drive signal may be generated based on the first control signal in the first time period, a timing signal may be generated based on the second control signal, and a second drive signal as the drive signal may be generated based on the timing signal.

For example, a second clock signal as the clock signal may be generated based on the timing signal in a third time period. Further, the second clock signal can indicate a start time instant of the third time period. In the third time period, the transistor may operate in the switching mode again, and the input current can be a single pulse current, such that the amount of accumulated charge of the input current is constant during the third time period by integrating the current sampling signal of the input current flowing through the transistor.

In particular embodiments, a linear-drive-controlled LED drive circuit can increase the power factor, reduce power consumption, improve efficiency, and prevent light flickering. In addition, the operation state of the transistor can be controlled in a time-sharing manner to control the magnitude and duration of the input current flowing through the LED load and capacitor C 1 , thereby increasing the current duration in the control period, reducing the current ripple, and increasing the power factor. By controlling the operation state of the transistor, the amount of accumulated charge of the input current during the half power frequency period can remain constant, thereby preventing light flickering due to grid jitter.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with modifications as are suited to particular use(s) contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.