Voltage level shifter

A voltage level shifter (or simply “level shifter”) is a circuit that translates a signal from one voltage domain to another voltage domain. The voltage of the output signal may be larger or smaller than the voltage of the input signal. A level shifter can be used, for example, when an input signal to a circuit has been generated in accordance with a particular voltage domain which differs from the supply voltage domain of the circuit itself. An n-type metal oxide semiconductor field effect transistor (NMOS) often has its source connected to the ground potential. As such, turning the NMOS device on simply requires a gate voltage in excess of the threshold voltage for the transistor, and the NMOS device is turned off with a gate voltage below the threshold, closer to ground. A p-type metal oxide semiconductor field effect transistor (PMOS) often has its source connected to the supply voltage. As such, turning the PMOS device off requires a gate voltage closer to the supply voltage (i.e., within the transistor's threshold voltage of the supply voltage). In a level shifter, the voltage levels to turn an NMOS device on and off, thus, will be different than the voltage levels to turn on and off a PMOS device.

In one example, a circuit includes first through fifth transistors. The first transistor has a first control input and first and second current terminals. The second transistor has a second control input and third and fourth current terminals. The third transistor has a third control input and fifth and sixth current terminals. The third control input is coupled to the third current terminal, and the fifth current terminal is coupled to a supply voltage node. The fourth transistor has a fourth control input and seventh and eighth current terminals. The fourth control input is coupled to the first current terminal, and the seventh current terminal coupled to the supply voltage node. The fifth transistor has a fifth control input and ninth and tenth current terminals. The fifth control input is coupled to the first control input, and the tenth current terminal coupled to the second current terminal.

For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

FIG. 1 illustrates an example of a level shifter.

FIG. 2 illustrates another example of a level shifter.

FIG. 3 illustrates another example of a level shifter.

FIG. 4 illustrates another example of a level shifter.

FIG. 1 shows an example of a high to low level shifter 100 which translates the incoming signal from a voltage domain that is lower than the supply voltage domain. The level shifter 100 includes NMOS transistors MN 1 , MN 2 , MN 3 , and MN 4 , PMOS transistors MP 1 and MP 2 , and inverters 102 , 104 , and 106 . Because the input signal is in a higher voltage domain than the voltage domain of the output signal (OUT_HV 2 ), MN 1 and MN 2 are high voltage transistors for reliability reasons, and thus the threshold voltage of MN 1 and MN 2 is higher than for MN 3 , MN 4 , MP 1 , and MP 2 . The sources of MP 1 and MP 2 are connected to the supply voltage node 110 (VDDHV 2 ). The drain of MP 1 is connected to the drain of MN 3 at node N 1 , and the drain of MP 2 is connected to the drain of MN 4 at node N 2 . The source of MN 3 is connected to the drain of MN 1 , and the source of MN 4 is connected to the drain of MN 2 . The sources of MN 1 and MN 2 are connected to the ground node 115 . The gate of MP 1 is connected to N 2 , and the gate of MP 2 is connected to N 1 . The gates of MN 3 and MN 4 are connected together and receive an enable (EN 1 ) input signal. When EN 1 is asserted high, MN 3 and MN 4 are both on; otherwise with EN 1 being low, MN 3 and MN 4 are both off, and the level shifter is disabled. The gate of MN 1 is configured to receive an input signal IN_HV 1 . Inverter 102 inverts IN_HV 1 to drive the gate of MN 2 . As such, only one of MN 1 and MN 2 are on at any point in time. Series connected inverters 104 and 106 are connected to N 2 , and the output of inverter 106 provides the output signal OUT_HV 2 from the level shifter 100 .

When IN_HV 1 is high, OUT_HV 2 also is high, and when IN_HV 1 is low, OUT_HV 2 also is low. When high, however, IN_HV 1 is at a different voltage than OUT_HV 2 . The voltage level of OUT_HV 2 is generally lower than the voltage level of IN_HV 1 (although in some conditions, OUT_HV 2 is higher than IN_HV 1 ). VDDHV 2 is the supply voltage for the level shifter 100 , and dictates the voltage level of OUT_HV 2 . When IN_HV 1 is logic high, MN 1 is on and MN 2 is off. With EN 1 asserted high, both MN 3 and MN 4 are on. With MN 1 and MN 3 being on, N 1 is pulled low to ground. As the voltage on N 1 drives the gate of MP 2 , the gate-to-source voltage (VGS) of MP 2 is sufficiently high to turn on MP 2 . With MP 2 on, N 2 is pulled high to VDDHV 2 , and OUT_HV 2 is thus also VDDHV 2 . Conversely, when IN_HV 1 is logic low, MN 1 is off and MN 2 is on. With MN 2 and MN 4 being on, N 2 is pulled low to ground, and thus OUT_HV 2 also is low. As the voltage on N 2 drives the gate of MP 1 , the VGS of MP 1 is sufficiently high to turn on MP 1 . With MP 1 on, N 1 is pulled high which, in turn, turns off MP 2 .

The NMOS devices MN 1 and MN 2 must be “strong” enough to cause the drains of MP 1 and MP 2 to discharge when IN_HV 1 transitions between low and high. For example, if IN_HV 1 is currently low, as explained above, MN 2 , MN 4 , and MP 1 are on. In this state N 1 is pulled high toward VDDHV 2 . During the transition of IN_HV 1 from low to high, MN 1 turns on and the charge on the drain of MP 1 should discharge to ground through MN 3 and MN 1 . For MP 1 's drain to discharge, the drain current (I 1 ) through MN 1 should be larger than the drain current (I 2 ) through MP 1 . I 1 is the sum of I 2 and the discharge current from the drain of MP 1 (the source-to-drain of MP 1 represents a capacitance that is charged when MN 1 is off, and then discharges when MN 1 is turned on).

The drain current through a MOS transistor is a function, at least in part, of its VGS and its size (size referring to the ratio of the transistor's channel width (W) to the channel length (L)). Under normal operating conditions, the VGS of MN 1 and MN 2 is higher than the VGS of MP 1 , and can easily pull down the voltage on the drains of MP 1 and MP 2 . Under conditions when the level shifter is enabled for lower voltage values of VDDHV 1 (close to the threshold voltage of MN 1 and MN 2 ), MN 1 and MN 2 are much weaker when their respective inputs become logic high (than with VDDHV 1 at higher voltages). In this latter condition (low value of VDDHV 1 ), because VDDHV 1 is smaller than VDDHV 2 , when IN_HV 1 transitions from low to high, the VGS of MP 1 is larger than the VGS of MN 1 . Thus, to discharge the drain of MP 1 , the size of MN 1 must be substantially larger than the size of MP 2 so that the drain current of MN 1 will be larger than the drain current of MP 1 , which in turn will cause N 1 to discharge. This problem is thus addressed in the example level shifter of 100 of FIG. 1 by making MN 1 larger than MP 1 . The same problem exists on the righthand side of the level shifter 100 for a high to low transition of IN_HV 1 , which causes MN 2 to turn on in an attempt to discharge the drain of MP 2 . MN 1 and MN 2 in this design are larger than MP 1 and MP 2 . There is thus a size penalty with the level shifter 100 of FIG. 1 . Further, the leakage current and average switching current is quite large as well.

FIG. 2 shows an example of a level shifter 200 that addresses the aforementioned problems. The level shifter 200 includes NMOS transistors MN 1 , MN 2 , and MN 3 A, PMOS transistors MP 1 , MP 2 , MP 3 , and MP 4 , and inverters 202 , 204 , and 206 . The sources of MP 1 and MP 2 are connected to the supply voltage node 110 (VDDHV 2 ). The drain of MP 1 is connected to the source of MP 3 at intermediate node int 3 , and the drain of MP 2 is connected to the source of MP 4 at intermediate node int 4 . The drain of MP 3 is connected to the drain of MN 1 at intermediate node int 1 , and the drain of MP 4 is connected to the drain of MN 2 at intermediate node int 2 . The sources of MN 1 and MN 2 are connected to drain of MN 3 A. The source of MN 3 is connected the ground node 115 , and an enable signal EN 2 is provided to the gate of MN 3 A to enable operation of the level shifter 100 . EN 2 being high (e.g., larger than the threshold voltage of MN 3 A) causes MN 3 A to be on, and EN 2 being low (e.g., ground potential) causes MN 3 A to be off. The level shifter 200 is enabled with EN 2 asserted high, and disabled otherwise.

The gate of MP 1 is connected to int 2 , and the gate of MP 2 is connected to int 1 . The gates of MP 3 and MN 1 are connected together and receive IN_HV 1 . Inverter 202 inverts IN_HV 1 to drive the gates of MP 4 and MN 2 , which are also connected together. Series connected inverters 204 and 206 are connected to int 2 , and the output of inverter 206 provides the output signal OUT_HV 2 from the level shifter 200 .

When IN_HV 1 is high, OUT_HV 2 also is high, and vice versa. When high, however, IN_HV 1 is at a different voltage than OUT_HV 2 . The voltage level of OUT_HV 2 may be higher or lower than the voltage level of IN_HV 1 . VDDHV 2 is the supply voltage for the level shifter 200 , and dictates the voltage level of OUT_HV 2 . When IN_HV 1 is logic high, MN 1 is on, and MN 2 and MP 3 are off. With MN 1 being on, in 1 is pulled low to ground. As the voltage on int 1 drives the gate of MP 2 , the VGS of MP 2 is sufficiently high to turn on MP 2 . With MP 2 on, the source voltage of MP 4 increases thereby causing MP 4 to turn on. As a result, int 2 is pulled high to VDDHV 2 , and OUT_HV 2 is thus also VDDHV 2 . Conversely, when IN_HV 1 is logic low MN 2 is on. With MN 2 being on, int 2 is pulled low to ground, and thus OUT_HV 2 also is low. As the voltage on int 2 drives the gate of MP 1 , the VGS of MP 1 is sufficiently high to turn on MP 1 . With MP 1 on, MP 3 also turns on, and int 1 is pulled high which, in turn, turns off MP 2 .

MP 3 and MP 4 in the example of FIG. 2 are used to isolate the input NMOS transistors MN 1 and MN 2 from the cross coupled PMOS transistors MP 1 and MP 2 . When IN_HV 1 is 0, MN 1 is off, and MP 1 and MP 3 are on. As IN_HV 1 transitions from low to high, MN 1 turns on and MP 3 turns off. As such, MN 1 need only sink enough current to discharge the drain of MP 3 . With MP 3 otherwise off, no current flows through MP 3 from MP 1 . In contrast to the level shifter 100 of FIG. 1 , MP 3 and MP 4 reduce or completely eliminate the drive fight between MN 1 and MP 1 and between MN 2 and MP 2 .

Instead of having MN 3 and MN 4 in FIG. 1 being the enable transistors, in FIG. 2 , that feature has been implemented with single tail transistor MN 3 A connected between the sources of MN 1 , MN 2 and the ground node 115 . Using a single tail transistor MN 3 A (versus two transistors MN 3 and MN 4 in FIG. 1 ) provides an area benefit, as well as improved performance from common mode noise as the level shifter 200 is perfectly differential.

In the example of FIG. 2 , while MN 2 turns on (when IN_HV 1 transitions from high to low), MP 4 turns off. At that point, MP 4 does not actively pull intermediate node int 4 low. This issue is addressed by having the input to inverter 204 connected to intermediate node int 2 instead of intermediate node int 4 . However, the rising transition of OUT_HV 2 will be slower if intermediate node int 2 is used rather than intermediate node int 4 .

FIG. 3 shows an example of a level shifter 300 , which includes NMOS transistors MN 1 , MN 2 , MN 3 A, MN 5 , and MN 6 , PMOS transistors MP 1 , MP 2 , MP 3 , and MP 4 , and inverters 302 , 304 , and 306 . The sources of MP 1 and MP 2 are connected to the supply voltage node 110 (VDDHV 2 ). The drain of MP 1 is connected to the source of MP 3 at intermediate node int 3 , and the drain of MP 2 is connected to the source of MP 4 at intermediate node int 4 . The drain of MP 3 is connected to the drain of MN 1 at intermediate node int 1 , and the drain of MP 4 is connected to the drain of MN 2 at intermediate node int 2 . The sources of MN 1 and MN 2 are connected to drain of MN 3 A. The source of MN 3 is connected the ground node 115 , and an enable signal EN 2 is provided to the gate of MN 3 A to enable operation of the level shifter 100 . As described above, EN 2 being high causes MN 3 A to be on, and EN 2 being low causes MN 3 A to be off. The level shifter 300 is enabled with EN 2 asserted high, and disabled otherwise.

Intermediate node int 4 is connected to the input of inverter 304 , and the output of inverter 304 is connected to the input of inverter 306 . The output of inverter 306 provides the output signal OUT_HV 2 from the level shifter 300 .

As was the case for FIG. 2 , MP 3 and MP 4 in the example of FIG. 3 are used to isolate the input NMOS transistors MN 1 and MN 2 from the cross coupled PMOS transistors MP 1 and MP 2 . When IN_HV 1 is 0, MN 1 is off, and MP 1 and MP 3 are on. As IN_HV 1 transitions from low to high, MN 1 turns on and MP 3 turns off. As such, MN 1 need only sink enough current to discharge the drain of MP 3 . With MP 3 otherwise off, no current flows through MP 3 from MP 1 . In contrast to the level shifter 100 of FIG. 1 , MP 3 and MP 4 reduce or completely eliminate the drive fight between MN 1 and MP 1 and between MN 2 and MP 2 .

The drain of MN 5 connects to the drain of MP 1 and to the source of MP 3 at int 3 . The source of MN 5 connects to the source of MN 1 . The drain of MN 6 connects to the drain of MP 2 and to the source of MP 4 at int 4 . The source of MN 6 connects to the source of MN 2 . As explained above regarding FIG. 2 , intermediate node int 4 is not actively pulled low when IN_HV 1 transitions from high to low thereby turning off MP 4 . This issue was addressed in the example level shifter 200 of FIG. 2 by having the series connected inverters 204 and 206 connected to intermediate node int 2 instead of intermediate node int 4 , but resulting in a lower slew rate for OUT_HV 2 when making a low to high transition. MN 5 and MN 6 in FIG. 3 solve this problem. MN 6 turns on wen MN 2 is turned on and MP 4 is turned off. As such, the charge on intermediate node int 4 is discharged through MN 6 to ground thereby quickly pulling the voltage on intermediate node int 4 low. The same action occurs when MN 1 is turned on and MP 3 is turned off (MN 5 is also turned on thereby quickly discharging intermediate nod int 3 ). As a result of quickly discharging the intermediate node int 4 , the voltage on the source of MP 4 is quickly pulled low which, in turn, causes MP 4 to turn off sooner during the high to low transition of IN_HV 1 than would have been the case in the example of FIG. 2 . Similarly, with MN 5 turning on during the low to high transition of IN_HV 1 , MP 3 is caused to turn off sooner during that transition than would have otherwise been the case in the example of FIG. 2 . Thus, the advantages of adding MN 5 and MN 6 are two-fold. First, discharge paths to int 4 and int 3 are provided. Second, isolation is improved for MN 1 , MP 1 , and for MN 2 , MP 2

FIG. 4 shows an example of a level shifter 400 , which includes NMOS transistors MN 1 , MN 2 , and MN 3 A, PMOS transistors MP 1 , MP 2 , MP 3 , MP 4 , MP 5 , MP 6 , MP 7 , and MP 8 , and inverters 402 , 404 , and 406 . The sources of MP 1 and MP 2 are connected to the supply voltage node 110 (VDDHV 2 ). The drain of MP 1 is connected to the source of MP 3 , and the drain of MP 2 is connected to the source of MP 4 . The drain of MP 3 is connected to the drain of MN 1 at intermediate node int 1 , and the drain of MP 4 is connected to the drain of MN 2 at intermediate node int 2 . The sources of MN 1 and MN 2 are connected to drain of MN 3 A. The source of MN 3 is connected the ground node 115 , and an enable signal EN 2 is provided to the gate of MN 3 A to enable operation of the level shifter 100 . As described above, EN 2 being high causes MN 3 A to be on, and EN 2 being low causes MN 3 A to be off. The level shifter 300 is enabled with EN 2 asserted high, and disabled otherwise.

Intermediate node int 2 is connected to the input of inverter 404 , and the output of inverter 404 is connected to the input of inverter 406 at intermediate node int 5 . The output of inverter 406 provides the output signal OUT_HV 2 from the level shifter 400 . The gate of MP 5 is connected to intermediate node int 5 . The gate of MP 6 is connected to intermediate node int 2 . The gate of MP 7 is connected to the output node of the level shifter 400 (OUT_HV 2 ). The gate of MP 8 is connected to intermediate node int 1 .

As was the case for FIG. 2 , MP 3 and MP 4 in the example of FIG. 3 are used to isolate the input NMOS transistors MN 1 and MN 2 from the cross coupled PMOS transistors MP 1 and MP 2 . When IN_HV 1 is 0, MN 1 is off, and MP 1 and MP 3 are on. As IN_HV 1 transitions from low to high, MN 1 turns on and MP 3 turns off. As such, MN 1 need only sink enough current to discharge the drain of MP 3 . With MP 3 otherwise off, no current flows through MP 3 from MP 1 . In contrast to the level shifter 100 of FIG. 1 , MP 3 and MP 4 reduce or completely eliminate the drive fight between MN 1 and MP 1 and between MN 2 and MP 2 .

MP 7 and MP 8 form a pull-up stack of transistors that are operative to quickly pull int 2 (and thus OUT_HV 2 ) from ground to VDDHV 2 . MP 7 and MP 8 assist the pull-up functionality of MP 2 and MP 4 in this regard. Similarly, MP 5 and MP 6 also form a pull-up stack of transistors that are operative to quickly pull int 1 from ground to VDDHV 2 . MP 5 and MP 6 assist the pull-up functionality of MP 1 and MP 3 in this regard. The operation of MP 7 and MP 8 will now be described when IN_HV 1 transitions from low to high. The same or similar explanation also applies to MP 5 and MP 6 when IN_HV 1 transitions from high to low.

When IN_HV 1 is low, MN 2 , MP 3 , and MP 1 are on. With MN 2 being on, int 2 is low, and through inverters 404 and 406 , OUT_HV 2 also is low. Because OUT_HV 2 is used as the gate voltage to MP 7 , MP 7 is on. However, MP 8 is off because intermediate node int 1 is high through MP 1 and MP 3 , both of which are on.

During the transition of IN_HV 1 from low to high, once IN_HV 1 reaches the threshold voltage of MN 1 , MN 1 turns on thereby pulling intermediate node int 1 low. With int 1 being low, MP 2 and MP 8 are both turned on. MP 4 also turns on. At this point, intermediate node int 2 begins to charge up via two transistor stacks. One transistor stack comprises MP 2 and MP 4 . The other transistor stack comprises MP 7 and MP 8 . Thus, MP 7 and MP 8 help to quickly increase the voltage on intermediate node int 2 (and thus OUT_HV 2 ) from ground towards VDDHV 2 .

As OUT_HV 2 begins to increase, once OUT_HV 2 reaches one transistor threshold voltage from VDDHV 2 , the VGS of MP 7 falls below its threshold voltage and MP 7 turns off, thereby effectively disabling the transistor stack of MP 7 /MP 8 . Thus, the rising transition of OUT_HV 2 is improved (i.e., its slew rate increases) due to the action of MP 7 and MP 8 during a portion of the transition phase of IN_HV 1 . The same explanation is applicable to MP 5 and MP 6 when IN_HV 1 transitions from high to low.

In this description, the term “couple” or “couples” means either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The recitation “based on” means “based at least in part on.” Therefore, if X is based on Y, X may be a function of Y and any number of other factors.

Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.