Predictive dead time generating circuit

This application is based upon and claims priority to Chinese Patent Application No. 201910051593.7, filed on Jan. 21, 2019, the entire contents of which are incorporated herein by reference.

The present invention belongs to the technical field of electronic circuits, and specifically relates to a predictive dead time generating circuit, which can be used to control a DC-DC converter.

As the battery size of electronic devices is getting smaller and smaller and the voltage is getting lower and lower, the requirements for a working efficiency of the switching mode power supply are getting higher and higher. Various techniques have been applied in the technology of the switching mode power supply to increase the efficiency. Among them, regarding the synchronous rectification technique, a metal oxide semiconductor field effect transistor (MOSFET) with a low on-state voltage drop is used to realize the rectification instead of the traditional diode, so as to reduce the conduction loss of the switching mode power supply system and improve the conversion efficiency of the switching mode power supply system. Since the MOSFET does not have the characteristic of unidirectional conduction as the diode does, it is necessary to insert a dead time between the on and off switching of the upper power transistor and the lower power transistor. During this dead time, both of the two transistors are turned off to avoid any damages to the power transistors.

A conventional dead time generating circuit with fixed dead time is shown in FIG. 1 . The PWM signal is a pulse width modulation signal of the DC-DC converter, P_Ctrl is a gate drive logic signal of the upper power transistor, and N_Ctrl is a gate drive logic signal of the lower power transistor.

When the PWM is flipped from low level to high level, the P_Ctrl gets delayed by ten gate circuits including inverters INV 9 , INV 1 , INV 2 , INV 3 , INV 4 , NAD 2 , INV 5 , INV 6 and INV 7 and an NAND gate NAD 1 to get flipped from low level to high level. While, the N_Ctrl to be flipped from high level to low level only gets delayed by five gate circuits including the inverters INV 9 , INV 1 , INV 2 , INV 3 and the NAND gate NAD 1 . A time margin is formed between the rising edge of the P_Ctrl and the falling edge of the N_Ctrl.

Similarly, when the PWM is flipped from high level to low level, the rising edge of the N_Ctrl is delayed by nine gate circuits including NAND gates NAD 2 and NAD 1 , and the inverters INV 5 , INV 6 , INV 7 , INV 8 , INV 1 , INV 2 , and INV 3 . While, the falling edge of the P_Ctrl is only delayed by four gate circuits including the NAND gate NAD 2 and the inverters INV 5 , INV 6 , and INV 7 . Another time margin is formed between the falling edge of the P_Ctrl and the rising edge of the N_Ctrl. As being delayed by different numbers of gate circuits, a dead time is formed between the output signals of the N_Ctrl and P_Ctrl.

The advantage of the fixed dead time is the simplicity. The disadvantage of the fixed dead time is that the fixed dead time should be long enough to meet the need of avoiding shoot-through under different temperatures and different process corners, etc. Since the body diode of the synchronous rectifying transistor is turned on during the dead time, a large power consumption will be caused and the efficiency of the system will be affected by using the fixed dead time technique. Therefore, although the fixed dead time technique can prevent the power transistor from getting burnout, the dead time is not the optimal value, and the power consumption is large, thereby limiting the overall efficiency of the converter.

In view of the problem that the dead time of the conventional fixed dead time generating circuit cannot reach the optimal value, so that the power consumption is large, the present invention provides a predictive dead time generating circuit, which not only ensures the time margin of the dead time, but also optimizes the duration of the dead time, thereby reducing the power consumption.

The technical solution of the present invention is as follows.

A predictive dead time generating circuit which sets a dead time by controlling an upper power transistor and a lower power transistor of a DC-DC converter including:

a dead time detecting module, a logic control module, and a delay module.

The dead time detecting module is configured to detect a dead time between a switching off of the upper power transistor and a switching on of the lower power transistor and dead time between a switching off of the lower power transistor and a switching on of the upper power transistor to generate a first detecting signal and a second detecting signal. The first detecting signal generates a high-level pulse when a detected dead time between the switching off of the upper power transistor and the switching on of the lower power transistor is excessive, otherwise the first detecting signal has a low-level pulse. And the second detecting signal generates a high-level pulse when a detected dead time between the switching off of the lower power transistor and the switching on of the upper power transistor is excessive, otherwise the second detecting signal has a low-level pulse.

The delay module includes M cascading first delay units, wherein M is a positive integer. An inversion signal of a pulse width modulation signal of the DC-DC converter generates M delay signals by the M cascading first delay units, wherein a delay signal generated by the last cascading first delay unit is used as an output signal of the delay module.

The logic control module includes a counting logic unit, a delay selecting unit, and a dead time generating module.

The counting logic unit includes a first bidirectional counter and a second bidirectional counter. When the second detecting signal has a low-level pulse, the first bidirectional counter decreases one count in a down direction. When the second detecting signal has a high-level pulse and the output signal of the delay module has a low-level pulse, the first bidirectional counter increments one count in an up direction. When the first detecting signal has a low-level pulse, the second bidirectional counter decreases one count in a down direction. When the first detecting signal has a high-level pulse and the output signal of the delay module has a high-level pulse, the second bidirectional counter increments one count in an up direction.

The delay selecting unit includes two decoders and two multiplexers. The first decoder is configured to convert an output code of the first bidirectional counter into a first control code of M bits. The first multiplexer is configured to select a corresponding delay signal from the M delay signals as the first control signal according to the first control code of M bits. The second decoder is configured to convert an output code of the second bidirectional counter into a second control code of M bits. The second multiplexer is configured to select a corresponding delay signal from the M delay signals as a second control signal according to the second control code of M bits.

The dead time generating module is configured to invert an output signal of the delay module to use as a driving signal of the upper power transistor, and to generate a driving signal of the lower power transistor according to the first control signal and the second control signal generated by the delay selecting unit. The first control signal generates a third control signal after being delayed for a time equal to a total delay time of the delay module. A rising edge of the driving signal of the lower power transistor is the same as a rising edge of the third control signal, and a falling edge of the driving signal of the lower power transistor is the same as a falling edge of the second control signal.

Specifically, when the dead time generating circuit is applied to a step-down (BUCK) converter, the dead time detecting module includes a first detecting unit and a second detecting unit. The first detecting unit and the second detecting unit are configured to generate the first detecting signal and the second detecting signal, respectively.

The second detecting unit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first resistor, and a first inverter, wherein the fourth NMOS transistor and the fifth NMOS transistor have the same bias current.

One terminal of the first resistor is connected to a signal at a switch node of the BUCK converter, and the other terminal of the first resistor is connected to a source terminal of the sixth NMOS transistor.

A gate terminal and a drain terminal of the first NMOS transistor are short-circuited and connected to gate terminals of the second NMOS transistor and the third NMOS transistor, and the bias current. A source terminal of the first NMOS transistor is connected to the source terminals of the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor and grounded.

A gate terminal and a drain terminal of the first PMOS transistor are short-circuited and connected to gate terminals of the third PMOS transistor, the fifth PMOS transistor, the seventh PMOS transistor, and the ninth PMOS transistor, and a drain terminal of the second NMOS transistor. A source terminal of the first PMOS transistor is connected to the source terminals of the second PMOS transistor, the fourth PMOS transistor, the sixth PMOS transistor, and the eighth PMOS transistor are connected to a power supply voltage.

A source terminal of the third PMOS transistor is connected to a drain terminal of the second PMOS transistor, and the drain terminal of the third PMOS transistor is connected to gate terminals of the second PMOS transistor, the fourth PMOS transistor, the sixth PMOS transistor, and the eighth PMOS transistor, and a drain terminal of the third NMOS transistor.

A gate terminal of the fifth NMOS transistor is connected to a gate terminal and a drain terminal of the fourth NMOS transistor and a drain terminal of the fifth PMOS transistor. A drain terminal of the fifth NMOS transistor is connected to a drain terminal of the seventh PMOS transistor and a gate terminal of the sixth NMOS transistor to output the second detecting signal after the first inverter. A source terminal of the fifth NMOS transistor is connected to drain terminals of the sixth NMOS transistor and the ninth PMOS transistor.

A drain terminal of the fourth PMOS transistor is connected to a source terminal of the fifth PMOS transistor, a drain terminal of the sixth PMOS transistor is connected to a source terminal of the seventh PMOS transistor, and a drain terminal of the eighth PMOS transistor is connected to a source terminal of the sixth PMOS transistor.

Specifically, the first detecting unit includes two Schmitt triggers and one NOR gate. Input terminals of the two Schmitt triggers are respectively connected to the signal at the switch node of the BUCK converter and the driving signal of the lower power transistor. Output terminals of the two Schmitt triggers are respectively connected to two input terminals of the NOR gate, and an output terminal of the NOR gate outputs the first detecting signal.

Specifically, the delay module includes a delay chain formed by cascading sixteen first delay units with a delay time of 4 ns.

Specifically, the counting logic unit further includes a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inversion, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, and a thirteenth inverter.

An input terminal of the second inverter is connected to an output signal of the delay module, and an output terminal of the second inverter is connected to input terminals of the third inverter and the fourth inverter.

An enable terminal of the fourth inverter is connected to the second detecting signal, and an output terminal of the fourth inverter is connected to an output terminal of the fifth inverter and an input terminal of the sixth inverter.

An input terminal of the seventh inverter is connected to an input terminal of the fifth inverter and an output terminal of the sixth inverter, and an output terminal of the seventh inverter is connected to a control terminal of the first bidirectional counter through the eighth inverter.

A clock terminal of the first bidirectional counter is connected to a delay signal generated by the fourteenth cascading first delay unit in the delay module.

An input terminal of the ninth inverter is connected to the output terminal of the third inverter, an enable terminal of the ninth inverter is connected to the first detecting signal, and an output terminal of the ninth inverter is connected to an output terminal of the tenth inverter and an input terminal of the eleventh inverter.

An input terminal of the twelfth inverter is connected to an input terminal of the tenth inverter and an output terminal of the eleventh inverter, and an output terminal of the twelfth inverter is connected to a control terminal of the second bidirectional counter through the thirteenth inverter.

A clock terminal of the second bidirectional counter is connected to the pulse width modulation signal.

Specifically, the dead time generating module includes an inverter chain formed by an odd number of inverters. The inverter chain is configured to convert the output signal of the delay module into the driving signal of the upper power transistor.

The dead time generating module further includes a fourteenth inverter, a fifteenth inverter, a sixteenth inverter, a seventeenth inverter, an eighteenth inverter, a nineteenth inverter, a twentieth inversion, a twenty-first inverter, a twenty-second inverter, a twenty-third inverter, a twenty-fourth inverter, and a second delay unit with a delay time same as a total delay time of the delay module.

An input terminal of the second delay unit is connected to the first control signal, and an output terminal of the second delay unit generates the third control signal and is connected to an enable terminal of the eighteenth inverter after going through a cascading structure of the fourteenth inverter and the fifteenth inverter.

The second control signal is connected to an input terminal of the eighteenth inverter after going through a cascading structure of the sixteenth inverter and the seventeenth inverter.

The nineteenth inverter and the twentieth inverter form a latch structure. An input terminal of the nineteenth inverter is connected to output terminals of the eighteenth inverter and the twentieth inverter. An output terminal of the nineteenth inverter is connected to input terminals of the twentieth inverter and the twenty-first inverter.

An output terminal of the twenty-first inverter generates the driving signal of the lower power transistor after sequentially going through a cascading structure of the twenty-second inverter, the twenty-third inverter, and the twenty-fourth inverter.

The advantages of the present invention are as follows. A predictive dead time generating circuit provided by the present invention can ensure the time margin of the dead time by adjusting the dead time, while optimize the duration of the dead time, thereby reducing power consumption.

FIG. 1 is a structural schematic diagram of a conventional fixed dead time generating circuit;

FIG. 2 is a topological structural diagram showing that a predictive dead time generating circuit of the present invention is applied to a DC-DC converter;

FIG. 3 is a structural schematic diagram of a first detecting circuit according to one embodiment;

FIG. 4 is a structural schematic diagram of a second detecting circuit according to one embodiment;

FIG. 5 is a structural schematic diagram of a delay circuit according to one embodiment;

FIG. 6 is a structural schematic diagram showing a counting logic according to one embodiment;

FIG. 7 is a structural schematic diagram of a bidirectional counter according to one embodiment;

FIG. 8 is a structural schematic diagram of a delay selecting circuit according to one embodiment;

FIG. 9 is a structural schematic diagram of a dead time generating circuit according to one embodiment; and

FIG. 10 is a waveform diagram of a dead time generating circuit according to the present embodiment.

The present invention will be described in the details below with references to the drawings and specific embodiments.

The idea of the predictive dead time generating circuit provided by the present invention is to determine whether the dead time reaches an optimum value according to working state of the preceding cycle, so as to determine whether the dead time of the next cycle should be increased or decreased. FIG. 2 shows a schematic diagram of a dead time detecting circuit. The predictive dead time generating circuit includes three parts: a dead time detecting module, a logic control module, and a delay module. The PWM signal of the DC-DC converter, after being delayed by the delay module, generates drive signal HDRV for the upper power transistor and drive signal LDRV for the lower power transistor in combination with the signal generated by the logic control module. The dead time detecting module is configured to detect the dead time between the switching off of the upper power transistor and the switching on of the lower power transistor, and the dead time between the switching off of the lower power transistor and the switching on of the upper power transistor. The first detecting signal D 1 and the second detecting signal D 2 are generated according to whether the detected dead time is optimal. The first detecting signal D 1 generates a high-level pulse when the detected dead time between the switching off of the upper power transistor and the switching on of the lower power transistor is excessive, otherwise the first detecting signal D 1 is a low-level pulse. The second detecting signal D 2 generates a high-level pulse when the detected dead time between the switching off of the lower power transistor and the switching on of the upper power transistor is excessive, otherwise the second detecting signal D 2 is a low-level pulse. The logic control module changes the output of the delay circuit according to the judgment result of the dead time detecting module, so as to change the dead time between drive signal HDRV for the upper power transistor and drive signal LDRV for the lower power transistor.

Now, taking an example that the predictive dead time generating circuit provided by the present invention is applied to a BUCK converter to explicitly illustrate the working process and working principle of the present embodiment, the structure of the dead time detecting module can be adjusted to be applicable to other DC-DC converters.

In the present embodiment, the dead time detecting module generates the first detecting signal D 1 and the second detecting signal D 2 according to the signal SW at the switch node of the BUCK converter and the drive signal LDRV of the lower power transistor. An implementation mode of the first detecting circuit is shown in FIG. 3 . The first detecting circuit is configured to detect the dead time between the switching off of the upper power transistor and the switching on of the lower power transistor. The first detecting circuit includes two Schmitt triggers, i.e. SCHM 1 and SCHM 2 , and one NOR gate NOR 1 . The input terminals of the two Schmitt triggers are respectively connected to the signal SW at the switch node of the BUCK converter and the drive signal LDRV of the lower power transistor. The output terminals of the two Schmitt triggers are respectively connected to the two input terminals of NOR gate NOR 1 , and the output terminal of NOR gate NOR 1 outputs the first detecting signal D 1 . The voltage levels of the SW point and the LDRV point are respectively detected by the two Schmitt triggers SCHM 1 and SCHM 2 . When the upper power transistor is turned on, the voltage level of the SW point will be pulled to a higher level. When the LDRV point has a low voltage level, the lower power transistor will be turned off. If during the process when the upper power transistor is turned off while the lower power transistor is turned on, and the two Schmitt triggers simultaneously output a low voltage level, it indicates that the two power transistors may be simultaneously turned off, and it is determined by the detecting circuit that the dead time is too long, thus the first detecting signal D 1 outputs a high-level pulse.

As shown in FIG. 4 , an implementation mode of the second detecting circuit is provided. The second detecting circuit is configured to detect the dead time between the switching off of the lower power transistor and the switching on of the upper power transistor. The second detecting circuit includes first NMOS transistor MN 1 , second NMOS transistor MN 2 , third NMOS transistor MN 3 , fourth NMOS transistor MN 4 , fifth NMOS transistor MN 5 , sixth NMOS transistor MN 6 , first PMOS transistor MP 1 , second PMOS transistor MP 2 , third PMOS transistor MP 3 , fourth PMOS transistor MP 4 , fifth PMOS transistor MP 5 , sixth PMOS transistor MP 6 , seventh PMOS transistor MP 7 , eighth PMOS transistor MP 8 , ninth PMOS transistor MP 9 , first resistor R 11 , and first inverter INV 14 . One terminal of first resistor R 11 is connected to signal SW at the switch node of the BUCK converter, and the other terminal of first resistor R 11 is connected to the source terminal of sixth NMOS transistor MN 6 . A gate terminal and a drain terminal of first NMOS transistor MN 1 are short-circuited and connected to gate terminals of second NMOS transistor MN 2 and third NMOS transistor MN 3 , and bias current IBIAS. A source terminal of first NMOS transistor MN 1 is connected to source terminals of second NMOS transistor MN 2 , third NMOS transistor MN 3 and fourth NMOS transistor MN 4 , and is connected to ground terminal GND. A gate terminal and a drain terminal of first PMOS transistor MP 1 are short-circuited and connected to gate terminals of third PMOS transistor MP 3 , fifth PMOS transistor MP 5 , seventh PMOS transistor MP 7 , and ninth PMOS transistor MP 9 , and a drain terminal of second NMOS transistor MN 2 . A source terminal of first PMOS transistor MP 1 is connected to source terminals of second PMOS transistor MP 2 , fourth PMOS transistor MP 4 , sixth PMOS transistor MP 6 , and eighth PMOS transistor MP 8 , and is connected to a power supply voltage VIN. A source terminal of third PMOS transistor MP 3 is connected to a drain terminal of second PMOS transistor MP 2 . A drain terminal of third PMOS transistor MP 3 is connected to gate terminals of second PMOS transistor MP 2 , fourth PMOS transistor MP 4 , sixth PMOS transistor MP 6 , and eighth PMOS transistor MP 8 , and a drain terminal of third NMOS transistor MN 3 . A gate terminal of fifth NMOS transistor MN 5 is connected to a gate terminal and a drain terminal of fourth NMOS transistor MN 4 and a drain terminal of fifth PMOS transistor MP 5 . A drain terminal of fifth NMOS transistor MN 5 is connected to a drain terminal of seventh PMOS transistor MP 7 and a gate terminal of sixth NMOS transistor MN 6 and outputs a second detecting signal D 2 after going through the first inverter INV 14 . A source terminal of fifth NMOS transistor MN 5 is connected to the drain terminals of sixth NMOS transistor MN 6 and ninth PMOS transistor MP 9 . A drain terminal of fourth PMOS transistor MP 4 is connected to a source terminal of fifth PMOS transistor MP 5 . A drain terminal of sixth PMOS transistor MP 6 is connected to a source terminal of seventh PMOS transistor MP 7 . A drain terminal of eighth PMOS transistor MP 8 is connected to a source terminal of sixth PMOS transistor MP 6 .

First PMOS transistor MP 1 , second PMOS transistor MP 2 , third PMOS transistor MP 3 , fourth PMOS transistor MP 4 , fifth PMOS transistor MP 5 , sixth PMOS transistor MP 6 , seventh PMOS transistor MP 7 , eighth PMOS transistor MP 8 , and ninth PMOS transistor MP 9 form a current mirror with a low voltage, a common source terminal, and a common gate terminal to ensure the mirror accuracy of the current. Fourth NMOS transistor MN 4 and fifth NMOS transistor MN 5 form a transistor pair that inputs from the source terminal, and the two transistors have the same bias current, so that the two transistors have the same gate-source voltage when operating in the saturation region. The source terminal of fourth NMOS transistor MN 4 is grounded, so if a potential of the source terminal of fifth NMOS transistor MN 5 is higher than the ground potential, the second detecting signal D 2 will output a low voltage level, and if the potential of the source terminal of fifth NMOS transistor MN 5 is lower than the ground potential, the second detecting signal D 2 will output a high voltage level. Sixth NMOS transistor MN 6 and first resistor R 11 are configured to determine the flip point of a comparator. Sixth NMOS transistor MN 6 operates in the linear region and can be regarded as a positive temperature resistor for fitting the change of the conduction resistance of the power transistor. This is because when the Buck circuit operates normally, signal SW also has a negative voltage, and the negative voltage varies as the conduction resistance of the external conduction power transistor varies, thus the flip point needs to be set lower than the normal conduction voltage. At normal temperature, the flip point of the comparator is −360 mV. In the process of switching off the lower power transistor and switching on the upper power transistor, if the voltage of the SW point is lower than −360 mV, it is indicated that the dead time is excessive, then second detecting signal D 2 will output a high-level pulse.

An implementation mode of the delay module, i.e. a 16-bit 4-ns delay chain, is shown in FIG. 5 . The inverted signal of pulse width modulation signal PWM generates sixteen delay signals from OUT_ 1 to OUT_ 16 when passing through a delay chain with a 4-ns unit delay, and the delay interval of each signal is 4 ns.

The digital control logic module can be divided into three parts. The first part is a counting logic unit, the second part is a delay selecting unit, and the third part is a dead time generating unit.

An implementation mode of the counting logic unit is shown in FIG. 6 . The counting logic unit includes second inverter INV 15 , third inverter INV 20 , fourth inverter ENINV 1 , fifth inverter INV 16 , sixth inverter INV 17 , seventh inverter INV 18 , eighth inverter INV 19 , ninth inverter ENINV 2 , tenth inverter INV 21 , eleventh inverter INV 22 , twelfth inverter INV 23 , thirteenth inverter INV 24 , first bidirectional counter Counter 1 , and second bidirectional counter Counter 2 . An input terminal of second inverter INV 15 is connected to output signal OUT_ 16 of the delay module, and an output terminal of the second inverter INV 15 is connected to the input terminals of third inverter INV 20 and fourth inverter ENINV 1 . The enable terminal of fourth inverter ENINV 1 is connected to second detecting signal D 2 , and the output terminal of fourth inverter ENINV 1 is connected to an output terminal of the fifth inverter INV 16 and an input terminal of sixth inverter INV 17 . An input terminal of seventh inverter INV 18 is connected to an input terminal of the fifth inverter INV 16 and an output terminal of sixth inverter INV 17 . An output terminal of seventh inverter INV 18 is connected to a control terminal of the first bidirectional counter Counter 1 through eighth inverter INV 19 . A clock terminal of first bidirectional counter Counter 1 is connected to delay signal OUT_ 14 generated by the fourteenth cascading the first delay unit in the delay module. An input terminal of ninth inverter ENINV 2 is connected to an output terminal of third inverter INV 20 , the enable terminal of ninth inverter ENINV 2 is connected to first the detecting signal D 1 , and an output terminal of the ninth inverter ENINV 2 is connected to an output terminal of the tenth inverter INV 21 and the input terminal of eleventh inverter INV 22 . The input terminal of twelfth inverter INV 23 is connected to the input terminal of tenth inverter INV 21 and an output terminal of eleventh inverter INV 22 . The output terminal of twelfth inverter INV 23 is connected to a control terminal of the second bidirectional counter Counter 2 after going through thirteenth inverter INV 24 . A clock terminal of the second bidirectional counter Counter 2 is connected to pulse width modulation signal PWM.

When the voltage levels of the enable terminal and the input terminal of fourth inverter ENINV 1 are both 1 , the voltage level of the output is 0. When the voltage levels of the enable terminal and the input terminal are 0 or voltage level of the enable terminal is 0 and the voltage level of the input terminal is 1, the output is latched by fifth inverter INV 16 and sixth inverter INV 17 . In other cases, the voltage level of the output is 1. A structure of the bidirectional counter is shown in FIG. 7 , where IN refers to a counting terminal. When the voltage level of the input to IN is 1, the counting direction is addition. When the voltage level of the input to IN is 0, the counting direction is subtraction, and the counting pulse is input from the C terminal.

In the present embodiment, when the output signal of the delay module, i.e., the falling edge of delay signal OUT_ 16 , comes along, if the voltage level of second detecting signal D 2 is 1, the voltage level of control terminal IN of first bidirectional counter Counter 1 is 1, and the counting direction of first bidirectional counter Counter 1 is addition. Thus, when the rising edge of delay signal OUT_ 14 generated by the fourteenth cascading delay unit in the delay module comes along, the first bidirectional counter Counter 1 increments one count. If the voltage level of the second detecting signal D 2 is not 1, the voltage level of the control terminal IN of the first bidirectional counter Counter 1 is 0, and the first bidirectional counter Counter 1 decreases one count. In the present embodiment, the reason why delay signal OUT_ 14 generated by the fourteenth cascading delay unit is in the delay module is selected as the clock signal for the first bidirectional counter Counter 1 is to ensure that after control terminal signal IN 1 changes in each cycle of the first bidirectional counter Counter 1 , the clock signal, i.e., the rising edge pulse of OUT_ 14 , again to adjusts the number of times of the first bidirectional counter Counter 1 .

When the output signal of the delay module, i.e., the rising edge of delay signal OUT_ 16 , comes along, if the voltage level of the first detecting signal D 1 is 1, the voltage level of control terminal signal IN of the second bidirectional counter Counter 2 is 1, the counting direction has an addition, and the pulse width modulation signal PWM is used as the clock signal of the second bidirectional counter Counter 2 . When the rising edge of pulse width modulation signal PWM comes along, second bidirectional counter Counter 2 increments one count. If the voltage level of the first detecting signal D 1 is not 1, second bidirectional counter Counter 2 decreases one count.

The structure of the delay selecting unit in the present embodiment is shown in FIG. 8 . The delay selecting unit includes two 4-to-16 decoders and two 16-to-1 multiplexers. The two decoders decode the outputs of first bidirectional counter Counter 1 and second bidirectional counter Counter 2 , respectively. Then, the first control signal OUT_ 18 and second control signal OUT_ 19 are obtained according to the corresponding signal selected by the 16-to-1 multiplexer from the sixteen delay signals from OUT_ 1 to OUT_ 16 generated by the delay module. The initial value of the first control signal OUT_ 18 is OUT_ 16 , and the initial value of second control signal OUT_ 19 is OUT_ 1 .

The dead time generating unit is configured to invert the output signal of the delay module, then use it as driving signal HDRV of the upper power transistor, and generate driving signal LDRV of the lower power transistor according to the first control signal OUT_ 18 and the second control signal OUT_ 19 generated by the delay selecting unit. First control signal OUT_ 18 generates third control signal OUT_ 20 after being delayed for the time equal to the total delay time of the delay module. The rising edge of the driving signal of the lower power transistor is the same as the rising edge of the third control signal OUT_ 20 . The falling edge of the driving signal of the lower power transistor is the same as the falling edge of second control signal OUT_ 19 .

A circuit implementation mode of the dead time generating unit is shown in FIG. 9 . The dead time generating unit includes an inverter chain composed of an odd number of inverters. The inverter chain is configured to convert output signal OUT_ 16 of the delay module into driving signal HDRV for the upper power transistor. The dead time generating module further includes a fourteenth inverter, a fifteenth inverter, a sixteenth inverter, a seventeenth inverter, an eighteenth inverter, a nineteenth inverter, a twentieth inverter, a twenty-first inverter, a twenty-second inverter, a twenty-third inverter, a twenty-fourth inverter, and a second delay unit. The delay time of the second delay unit is the total delay time of the delay module. In the present embodiment, since the delay module is formed by cascading sixteen 4-ns first delay units, the delay time of the second delay unit is 64 ns. The input terminal of the second delay unit is connected to first control signal OUT_ 18 , and the output terminal of the second delay unit generates third control signal OUT_ 20 and is connected to the enable terminal of the eighteenth inverter after going through the cascading structure of the fourteenth inverter and the fifteenth inverter. Second control signal OUT_ 19 is connected to the input terminal of the eighteenth inverter after going through the cascading structure of the sixteenth inverter and the seventeenth inverter. The nineteenth inverter and the twentieth inverter form a latch structure. The input terminal of the nineteenth inverter is connected to the output terminals of the eighteenth inverter and the twentieth inverter, and the output terminal of the nineteenth inverter is connected to the input terminals of the twentieth inverter and the twenty-first inverter. The output terminal of the twenty-first inverter generates driving signal LDRV for the lower power transistor after sequentially going through the cascading structure of the twenty-second inverter, the twenty-third inverter, and the twenty-fourth inverter.

First control signal OUT_ 18 generates third control signal OUT_ 20 after being delayed for 64 ns by the second delay unit. The rising edge of driving signal LDRV of the lower power transistor is determined by third control signal OUT_ 20 , the falling edge of driving signal LDRV of the lower driving transistor is determined by second control signal OUT_ 19 , and the waveform diagram is shown in FIG. 10 . The dead time between the switching off of the upper power transistor and the switching on of the lower power transistor can be expressed as: 60 ns−counter 2 output code×4 ns. The dead time between the switching off of the lower power transistor and the switching on of the upper power transistor can be expressed as: (16−counter 1 output code)×4 ns. The predictive dead time generating circuit can finally reach the optimal value of the approximate zero dead zone, which not only avoids the shoot-through between the upper power transistor and the lower power transistor, but also improves the efficiency.

The above embodiments are merely used to illustrate the technical solutions of the present invention. It should be understood by those skilled in the art that the technical solutions of the present invention may be modified or equivalently substituted without departing from the spirit and scope of the present solutions. Such modifications and substitutions should be considered as falling within the scope of the present invention.