USPatent applicationPatented

Segmented shielding using wirebonds

Granted 21 Sep 2021 · 3 office actions

Current assignee: Qorvo US, INC. · originally Qorvo, Inc.

Law firm: Law firm · Log in to unlock

Attorney: Attorney · Log in to unlock

Inventors: Domingo Farias, Kyle Sullivan, Donald Joseph Leahy, Brian H. Calhoun +3 · Examiner: Changhyun Yi · AU 2826 · TC 2800

Life of the application

16 dated events
⤢ drag to zoom201820202022202420262028203020322034203620382040ProsecutionOwnershipTerm & fees
ProsecutionOwnershipTerm & feeshover for detail · click to open

Abstract

The present disclosure relates to segmented shielding using wirebonds. In an exemplary aspect, a shield is formed from a series of wires (e.g., wirebonds) to create a wall and/or shielded compartment in an integrated circuit (IC) module. The wires can be located in any area within the IC module. The IC module may be overmolded with an insulating mold compound, and a top surface of the insulating mold can be ground or otherwise removed to expose ends of the wires to a shield layer which surrounds the insulating mold. Some examples may further laser ablate or otherwise form cavities around the ends of the wires to create stronger bonding between the wires of the shield and the shield layer.

Description

8 parts
›RELATED APPLICATIONS

This application claims the benefit of provisional patent application Ser. No. 62/679,178, filed Jun. 1, 2018, the disclosure of which is hereby incorporated herein by reference in its entirety.

›FIELD OF THE DISCLOSURE

This application relates to shielding for integrated circuit devices.

›BACKGROUND

Many electronic devices include multiple components, including integrated circuit (IC) modules. Such components are often mounted to circuit boards in order to provide various functionalities. Such IC modules may have need to suppress spurious noise fields.

›SUMMARY

The present disclosure relates to segmented shielding using wirebonds. In an exemplary aspect, a shield is formed from a series of wires (e.g., wirebonds) to create a wall and/or shielded compartment in an integrated circuit (IC) module. The wires can be located in any area within the IC module. The IC module may be overmolded with an insulating mold compound, and a top surface of the insulating mold can be ground or otherwise removed to expose ends of the wires to a shield layer which surrounds the insulating mold. Some examples may further laser ablate or otherwise form cavities around the ends of the wires to create stronger bonding between the wires of the shield and the shield layer.

An exemplary embodiment relates to a method for forming a shielded compartment in an IC module. The method includes providing a module substrate and forming an electromagnetic shield. Forming the electromagnetic shield includes placing a first series of wires to form a first wall separating a shielded compartment from a portion of the module substrate and bonding the first series of wires to a conductive plate in the module substrate. The method also includes depositing an insulating mold over the module substrate and depositing a shield layer over the insulating mold, the shield layer contacting an exposed end of each of the first series of wires.

Another exemplary embodiment relates to an IC module having a shielded compartment. The IC module includes a substrate comprising a ground conductor and an electromagnetic shield, comprising a first wall formed from a first series of wires bonded to the ground conductor. The IC module also includes an insulating mold disposed over the substrate and a shield layer disposed over the insulating mold and in contact with ends of each of the first series of wires.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

›BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

FIG. 1A is a schematic diagram of an exemplary integrated circuit (IC) module, which includes an electromagnetic shield forming a wall.

FIG. 1B is a schematic diagram of another exemplary IC module, which includes the electromagnetic shield forming a shielded compartment.

FIG. 2A is a cross-sectional view of the exemplary IC module of FIG. 1A or FIG. 1B , illustrating bonding wires of the electromagnetic shield to a conductive plate.

FIG. 2B is another cross-sectional view of the exemplary IC module of FIG. 2A , illustrating encapsulating the IC module in an insulating mold.

FIG. 2C is another cross-sectional view of the exemplary IC module of FIG. 2A , illustrating removing a top surface of the insulating mold.

FIG. 2D is another cross-sectional view of the exemplary IC module of FIG. 2A , illustrating forming a cavity around the wires of the electromagnetic shield.

FIG. 2E is another cross-sectional view of the exemplary IC module of FIG. 2A , illustrating forming a shield layer over the IC module.

FIG. 3 is a transparent isometric view of the exemplary IC module of FIG. 1A or FIG. 1B .

›DETAILED DESCRIPTION · 1 of 3

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The present disclosure relates to segmented shielding using wirebonds. In an exemplary aspect, a shield is formed from a series of wires (e.g., wirebonds) to create a wall and/or shielded compartment in an integrated circuit (IC) module. The wires can be located in any area within the IC module. The IC module may be overmolded with an insulating mold compound, and a top surface of the insulating mold can be ground or otherwise removed to expose ends of the wires to a shield layer which surrounds the insulating mold. Some examples may further laser ablate or otherwise form cavities around the ends of the wires to create stronger bonding between the wires of the shield and the shield layer.

FIG. 1A is a schematic diagram of an exemplary IC module 10 , which includes an electromagnetic shield 12 forming a wall 14 . It may be desirable to dampen spurious noise fields (e.g., undesired electromagnetic interferences) within the IC module 10 . The electromagnetic shield 12 is provided to form the wall 14 between portions of the IC module 10 needing separate shielding. For example, the IC module 10 may include a first IC which causes noise that interferes with a second IC, and the electromagnetic shield 12 may separate and electromagnetically isolate these ICs from each other.

FIG. 1B is a schematic diagram of another exemplary IC module 10 , which includes the electromagnetic shield 12 forming a shielded compartment 16 . In this regard, the shielded compartment 16 may electromagnetically isolate the shielded compartment 16 from other portions of the IC module 10 . This may reduce electromagnetic interference entering and/or leaving the shielded compartment 16 . In the example depicted in FIG. 1B , the electromagnetic shield 12 includes a first wall 14 and a second wall 18 defining the shielded compartment 16 .

It should be understood that the electromagnetic shield 12 can include any number of walls 14 , 18 , and that the walls may be any geometric shape and/or meet at different angles. It should be further understood that while FIGS. 1A and 1B are depicted with walls 14 , 18 which extend to edges of the IC module 10 and fully enclose the shielded compartment 16 , other examples may not extend to these edges, and the compartment 16 may not be fully enclosed by these walls 14 , 18 . An exemplary process of forming the electromagnetic shield 12 and additional details are further described below with respect to FIGS. 2A-2E . An exemplary IC module 10 having the electromagnetic shield 12 is illustrated in greater detail in FIG. 3 .

›DETAILED DESCRIPTION · 2 of 3

FIG. 2A is a cross-sectional view of the exemplary IC module 10 of FIG. 1A or FIG. 1B , illustrating bonding wires 20 of the electromagnetic shield 12 to a conductive plate 22 . In this regard, the electromagnetic shield 12 is formed by providing a module substrate 24 and placing a first series of wires 26 to form a wall 14 (e.g., a first wall) separating the shielded compartment 16 from a portion of the module substrate 24 (e.g., as shown in FIG. 1A or FIG. 1B ). The first series of wires 26 is bonded to the conductive plate 22 in the module substrate 24 .

The module substrate 24 may be a printed circuit board or other laminate having a number of layers. These layers of the module substrate 24 may include prepreg material. The conductive plate 22 may be a ground plate or similar element formed on or in the layers of the module substrate 24 (using an appropriate conductive material, such as gold, silver, copper, etc.). The module substrate 24 can also include module contacts 28 and other conductive elements, via structures, and the like, which may be formed from the same or another appropriate conductive material. The IC module 10 may be a single-sided IC module 10 (e.g., having ICs and other components coupled to only one side of the module substrate 24 ), or it may be a double-sided IC module (e.g., having ICs and other components coupled to a top and bottom side of the module substrate 24 ).

The wires 20 of the electromagnetic shield 12 can be formed from an appropriate conductive material, such as palladium coated copper, copper, gold, silver, or aluminum. The wires 20 may be between 0.6 mil and 2.0 mil diameter having wire loops whose ends 30 are bonded to the conductive plate 22 through an appropriate technique, such as ultrasonic bonding (e.g., ball bonding, wedge bonding), compliant bonding, soldering, combinations of these techniques, and so on. The bonded ends 30 of the wires 20 are generally separated from one another, but still function to electromagnetically isolate the shielded compartment 16 . In an exemplary aspect, each of the wires 20 spans 350 microns (μm) to 550 μm, and the bonded ends 30 of the wires 20 are separated by at least 80 μm.

With reference to FIG. 1B and FIG. 2A , second and/or additional walls of the electromagnetic shield 12 can be formed by placing a second and/or additional series of wires separating the shielded compartment 16 from other portions of the module substrate 24 . The second and/or additional series of wires is further bonded to the conductive plate 22 in a similar manner as the first series of wires 26 . It should be understood that the process further described in FIGS. 2B-2E can be similarly applied to this second and/or additional walls.

FIG. 2B is another cross-sectional view of the exemplary IC module 10 of FIG. 2A , illustrating encapsulating the IC module 10 in an insulating mold 32 . The insulating mold 32 is applied over the module substrate 24 (e.g., over the top side of the module substrate 24 ) to encapsulate each electronic component on the surface of the module substrate 24 and the electromagnetic shield 12 . The insulating mold 32 may be an organic epoxy resin or similar material deposited at a thickness of 350 μm or greater. The insulating mold 32 may be applied by various procedures, such as sheet molding, overmolding, compression molding, transfer molding, dam fill encapsulation, or screen print encapsulation. In an exemplary aspect, the insulating mold 32 fills any space below the wires 20 . A curing process hardens the insulating mold 32 .

FIG. 2C is another cross-sectional view of the exemplary IC module 10 of FIG. 2A , illustrating removing a top surface of the insulating mold 32 . A portion of the insulating mold 32 is removed to expose ends 34 (e.g., top ends) of the wires 20 (e.g., the first series of wires 26 ). The ends 34 are exposed through an appropriate technique, such as by strip level grinding the top surface of the insulating mold 32 (e.g., to a thickness of 320 μm) and the wires 20 such that each wire loop is cut in half. In some examples, the insulating mold 32 deposition process can leave the ends 34 exposed without grinding, or another removal process (e.g., chemical or mechanical) can be used.

FIG. 2D is another cross-sectional view of the exemplary IC module 10 of FIG. 2A , illustrating forming a cavity 36 around the wires 20 of the electromagnetic shield 12 . As shown in FIG. 2E , the exposed ends 34 of the wires 20 are bonded to a shield layer 38 over the insulating mold 32 . This bonding can be improved by first forming the cavity 36 around each exposed end 34 to increase a surface area of the wires 20 for bonding (e.g., by exposing sides of the wires 20 in addition to the exposed ends 34 ). In an exemplary aspect, the cavity 36 is formed by laser ablating about each of the exposed ends 34 of the wires 20 . Other techniques may also be applied, such as mechanical removal (e.g., water jets, grinding), ion milling, chemical removal, and so on. The cavity 36 may be between 1 μm and 20 μm about each wire 20 , and may be from 1 μm to 10 μm deep. The cavity 36 can further be cleaned in a chemical bath (e.g., with a permanganate etchant) and/or plated with an electroless or electroless/electrolytic plating process.

FIG. 2E is another cross-sectional view of the exemplary IC module 10 of FIG. 2A , illustrating forming the shield layer 38 over the IC module 10 . The shield layer 38 is deposited over the insulating mold 32 and contacts the exposed ends 34 of the wires 20 (e.g., the first series of wires 26 ). The shield layer 38 can be deposited by plating the insulating mold 32 and the exposed ends 34 , sputtering a conductive material over the insulating mold 32 and the exposed ends 34 , or another appropriate technique (e.g., applying a conductive paint or ink). In some examples, the shield layer 38 can be formed separately and coupled to the insulating mold 32 and the exposed ends 34 of the wires 20 .

The shield layer 38 can include a single layer of material, or it can include multiple layers of the same or different materials. For example, an interior layer (e.g., in contact with the insulating mold 32 ) may be formed of copper, aluminum, silver, gold, or other conductive materials with a thickness between 3 μm and 16 μm. An exterior layer may reside over the interior layer, and may be formed of nickel with a thickness between 1 μm and 3 μm.

›DETAILED DESCRIPTION · 3 of 3

In an exemplary aspect, the shield layer 38 entirely covers a top surface 40 of the IC module 10 and entirely or almost entirely covers a side surface 42 of the IC module 10 . The shield layer 38 does not cover a bottom side 44 of the IC module 10 . Herein and hereafter, entirely covering a surface refers to covering at least 99% of the surface, while almost entirely covering a surface refers to covering at least 90% of the surface.

FIG. 3 is a transparent isometric view of the exemplary IC module 10 of FIG. 1A or FIG. 1B . In this regard, the electromagnetic shield 12 forms the shielded compartment 16 to electromagnetically isolate the shielded compartment 16 from other portions of the IC module 10 . In the example depicted in FIG. 3 , the electromagnetic shield 12 includes the first wall 14 and the second wall 18 . The first wall 14 includes the first series of wires 26 bonded to the conductive plate 22 , and the second wall 18 includes a second series of wires 46 bonded to the conductive plate 22 . The electromagnetic shield 12 separates a first component 48 (e.g., a first IC, capacitor, inductor, etc.) coupled to the module substrate 24 from a second component 50 (e.g., a second IC, capacitor, inductor, etc.) coupled to the module substrate 24 . It should be understood that various combinations of components, including ICs, can be coupled to the top and/or bottom surface of the module substrate 24 , and one or more electromagnetic shields 12 can be formed to provide suppression of spurious noise fields as needed. In some examples, the wires 20 may be bonded between a component 48 , 50 and the shield layer 38 .

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims as granted

20 claims

Log in to read the claims of this application.

Log in to unlock

Classifications

3 codes
IPC · International Patent Classification
Section H — Electricity
  • H01L23/552
  • H01L23/00
  • H10W74/01

Claim changes

Soon
Coming soonHow the claims changed between publication and grant

See which claims were amended, added or cancelled during examination, with every added and removed word marked.

AmendedAddedCancelledUnchanged

The published claims of this application are not paired with the granted ones in what we hold.

File wrapper

⤢ drag to zoomApr 2019Jul 2019Oct 2019Jan 2020Apr 2020Jul 2020Oct 2020Jan 2021Apr 2021Jul 2021Oct 2021USPTOApplicantNon-final rejectionResponse after non-finalResponse after finalNon-final rejectionResponse after non-final
USPTOApplicanthover for detail · click to open
Pendency
2.5 y
903 days filing → grant
Office actions
3
non-final + final
Responses
3
1 RCE
Examiner
Changhyun Yi
art unit 2826 · TC 2800
Citations: 412 back · 0 forward

See the full prosecution history — every USPTO and applicant action on this file, in order.

Log in to unlock

Documents

Log in to open the documents of this file: the application as filed, every office action and response, the notice of allowance.

Log in to unlock

Chain of title

⤢ drag to zoom20202022202420262028203020322034203620382040Owner 1
Titlehover for detail · click to open

See the full assignment history — every owner this patent has passed through, with recordation dates and reel/frame numbers.

Log in to unlock