Fully compensated complementary duty cycle correction circuits

This application relates to duty cycle correction, and more particularly to fully compensated complementary duty cycle correction circuits.

It is conventional to control the duty cycle of a clock signal for clocking a digital system with a duty cycle correction circuit. For example, double data rate (DDR) transmission uses both the falling edge and the rising edge of a DDR clock signal for data transmission and reception. The data rate for a DDR system is thus twice that as for a single-clock-edge system at the same clocking frequency. Although the use of DDR is thus quite popular, its use faces a number of challenges due to its more stringent timing requirements as compared to single edge data transmission. For example, the DDR clock should have a 50% duty cycle. One can readily appreciate why in that a 50-50 split of the duty cycle for the rising/falling edges of the clock allows the receiver and transmitter the most time possible with each clock edge. As the duty cycle strays from this ideal 50-50 split, one of the clock states has less of each clock cycle than the remaining state. The data eye for the receiver then begins to collapse for the shortened clock state, which leads to undesirable data transmission errors.

Given the importance of obtaining a 50% duty cycle, various duty cycle correcting circuits have been implemented. A conventional duty cycle clock correction circuit 100 is shown in FIG. 1A . A first inverter 105 with a variable pull-up resistance and a variable pull-down resistance inverts an input clock (clk in) to produce a complement output clock signal (clkb out). The core of first inverter 105 is formed by a serial combination of a p-type metal-oxide-semiconductor (PMOS) inverter transistor P 1 and an n-type metal-oxide-semiconductor (NMOS inverter transistor M 1 . If the source of inverter transistor P 1 connected directly to a power supply node for a power supply voltage VDD, the pull-up resistance for first inverter 105 would be determined by the on-resistance for inverter transistor P 1 . To provide a variable pull-up resistance, the source of transistor P 1 instead couples to the power supply node through a PMOS pull-up transistor P 2 coupled in parallel with a variable-resistance transistor P 3 formed as a parallel combination of (N+1) PMOS transistors starting from a zeroth transistor P 3 0 through an Nth transistor P 3 N , where N is a plural positive integer. An active low enable signal (enb) drives the gate of pull-up transistor P 2 so that it is switched on during normal operation for first inverter 105 . A first pull-up tuning signal Ctrlbp<0:N> controls which of the transistors P 3 0 through P 3 N conduct. As more of these transistors conduct, the variable pull-up resistance for first inverter 105 lowers. Conversely, as fewer of the transistors P 3 0 through P 3 N conduct, the variable pull-up resistance increases. Since pull-up transistor P 2 is always on during normal operation, first inverter 105 is powered regardless of the state for the first pull-up tuning signal.

The variable pull-down resistance for first inverter 105 is controlled in an analogous fashion by a first pull-down tuning signal Ctrln<0:N> that controls a variable-resistance transistor M 3 formed as a parallel combination of (N+1) NMOS transistors starting from a zeroth transistor M 3 0 through an Nth transistor M 3 N . These transistors are arranged in parallel with a pull-down NMOS transistor M 2 having its gate controlled by an active-high enable signal (en) during normal operation.

A second inverter 110 with a variable pull-up resistance and a variable pull-down resistance inverts a complement input clock signal (clkb in) to form a clock output signal (clk out). The core of second inverter 110 is formed by a serial combination of a PMOS inverter transistor P 4 and an NMOS inverter transistor M 4 . The source of inverter transistor P 4 couples to the power supply node through a pull-up PMOS transistor P 5 coupled in parallel with a variable-resistance PMOS transistor P 6 formed as a parallel combination of (N+1) transistors starting from a zeroth transistor P 6 0 through an Nth transistor P 6 N . A second pull-up tuning signal ctrlbn<0:1> controls which of the P 6 transistors are conducting to control the variable pull-up resistance for second inverter 110 . The source of inverter transistor M 4 couples to ground through a pull-down NMOS transistor M 5 and a variable-resistance NMOS transistor M 6 formed as a parallel combination of (N+1) NMOS transistors starting from a zeroth transistor M 6 0 through an Nth transistor M 6 N . A second pull-down tuning signal Ctrl<0:N> controls which of the transistors M 6 are conducting to control the variable pull-down resistance for second inverter 110 .

The control of the duty cycle for the clock output signal by duty cycle correction circuit 100 may be better appreciated with reference to the clock waveforms shown in FIG. 1B . The duty cycle for the clock input signal (Clk in) is less than 50%. The complement input clock signal thus has a duty cycle greater than 50%. The variable pull-up resistance for first inverter 105 is thus increased so that a slope for a rising edge for the complement output signal (clkb out) is dampened or slowed. The duty cycle for the complement output signal is thus decreased to equal the desired 50% value. Conversely, the variable pull-down resistance for second inverter 110 is increased so that that a slope for the falling edges for the clock output signal (clk out) is lowered. The duty cycle for the output clock signal is thus increased to equal the desired 50% value.

Although operation of duty cycle correction circuit 100 thus achieves the desired duty cycle correction, note that this correction is only achieved at typical process, voltage, and temperature corners. At more extreme process corners, such as a fast NMOS/slow PMOS corner or a slow NMOS/fast PMOS corner, duty cycle correction circuit 100 cannot obtain the desired duty cycle correction without some duty cycle distortion across the various process corners. Accordingly, there is a need in the art for improved duty cycle correction circuits with reduced duty cycle distortion across a wide range of process, voltage, and temperature variations.

Duty cycle correction circuits are provided that include a first pair of inverters and also a second pair of inverters. The first pair of the inverters is formed by a first inverter arranged in serial with a second inverter to invert an input clock signal into an output clock signal having a corrected duty cycle. The second pair of inverters is similarly formed by a third inverter arranged in series with a fourth inverter to invert a complement input clock signal into a complement output clock signal having the corrected duty cycle. Each inverter has a variable pull-up resistance and a variable pull-up resistance that may both be tuned as necessary to provide the desired duty cycle correction.

The variable pull-up resistance for the first inverter is responsive to a first pull-up tuning signal. Similarly, the variable pull-down resistance for the first inverter is responsive to a first pull-down tuning signal. A second pull-up tuning signal tunes the variable pull-up resistance for the third inverter whereas a second pull-down tuning signal tunes the variable pull-down resistance for the third inverter. The second pull-up tuning signal also tunes the variable pull-up resistance for the second inverter. Similarly, the second pull-down tuning signal also tunes the variable pull-down resistance for the second inverter. The tuning for the fourth inverter is analogous in that it is controlled by the first pull-up tuning signal and the first pull-up tuning signal.

The resulting tuning symmetry for the four inverters is quite advantageous as it provides for a symmetric tuning of both the rising and falling edges for the output clock signal and also the rising and falling edges of the complement output clock signal. This symmetric tuning provides a robust duty cycle correction that reduces the duty cycle distortion for a wide range of process, voltage, and temperature corners.

These and other advantageous features may be better appreciated through the following detailed description.

FIG. 1A illustrates a conventional duty cycle correction circuit.

FIG. 1B illustrates some input and output clock waveforms for the conventional duty cycle correction circuit of FIG. 1A .

FIG. 2 illustrates a duty cycle correction circuit in accordance with an aspect of the disclosure in which variable-resistance transistors do not load the output clock signal nodes.

FIG. 3 illustrates a duty cycle correction circuit in accordance with an aspect of the disclosure in which variable-resistance transistors load the output clock signal nodes but provide for a greater duty cycle tuning range as compared to the duty cycle correction circuit of FIG. 2 .

FIG. 4 is a flowchart for a duty cycle correction method in accordance with an aspect of the disclosure.

FIG. 5 illustrates some example electronic systems incorporating a duty cycle correction circuit in accordance with an aspect of the disclosure.

Implementations of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.

Duty cycle correction circuits are provided that include a first inverter having a variable pull-up resistance and a variable pull-down resistance. As used herein, a “variable pull-up resistance” for an inverter refers to the resistance between a power supply node for the inverter and a node for its output signal. The variable pull-up resistance thus affects the strength of a rising edge for a clock signal produced by an inverter. The weaker the variable pull-up resistance, the steeper is the slope for the rising edge as the inverter charges its output clock signal to the power supply voltage carried on the power supply node. Conversely, the stronger the variable pull-up resistance, the more the slope for the rising edge is reduced. As used herein, a “variable pull-down resistance” for an inverter refers to the resistance between the inverter's output node and ground. The weaker the variable pull-down resistance, the steeper in the slope for the falling edge for the output clock signal from the inverter. Conversely, the stronger the variable pull-down resistance, the more the slope for the falling edge is reduced.

The first inverter inverts an input clock signal to produce an intermediate complement clock signal. The intermediate complement clock signal is referred to herein as intermediate because it not an output clock signal for the duty cycle correction circuit. A tuning for the variable pull-up and pull-down resistance for the first inverter depends upon a duty cycle for the input clock signal. In the following discussion, it will be assumed that a desired duty cycle is 50% but it will be appreciated that the disclosed duty cycle correction circuits and techniques may be readily adapted to provide whatever duty cycle is desired for the output clock signals. Depending upon the tuning, the variable pull-up and pull-down resistances each have a default resistance value. In the following discussion, it will be assumed that the default resistance is the minimum value in a tuning resistance range but the default resistance can be varied in alternative implementations.

If the duty cycle for the input clock signal is too small, the variable pull-up resistance is increased from its default value. The variable pull-down resistance may then remain at its default value. The slope for the rising edges in the intermediate complement clock signal would decrease in response to this increase in the pull-up resistance. Note that a “rising edge” as used herein refers to the clock signal phase in transition from its voltage low state (such as ground) to its voltage high state (e.g., the power supply voltage VDD). Conversely, if the duty cycle for the input clock signal is too large, the variable pull-down resistance is increased from its default value. The variable pull-up resistance may then remain at its default value. The slope for the falling edges in the intermediate complement clock signal would then be decreased. Analogous to the rising edges, a “falling edge” as used herein refers to the clock signal phase in transition from its voltage high state to its voltage low state.

The duty cycle correction circuit further includes a second inverter having a variable pull-up resistance and a variable pull-down resistance. The second inverter inverts a complement input clock signal to produce an intermediate clock signal. Analogous to the first inverter, the variable pull-up and pull-down resistances for the second inverter will each have a default value in the absence of any tuning. The variable pull-up resistance and the variable pull-down resistance for the second inverter are tuned from their default values in a complementary fashion as compared to the tuning of the variable pull-up and pull-down resistances for the first inverter. For example, if the duty cycle of the input clock signal is too large, the duty cycle for the complement input clock signal will be too small. In that case, the variable pull-up resistance for the second inverter is increased from its default value whereas the variable pull-down resistance may stay at its default value. Conversely, if the duty cycle is too large for the complement input clock signal, the variable pull-down resistance is increased from its default value. The variable pull-down resistance may then remain at its default value.

To provide a more robust control of the duty cycle for an output clock signal, the duty cycle correction circuits disclosed herein also include a third inverter having variable pull-up and pull-down resistances. The third inverter inverts the complement intermediate clock signal from the first inverter to form the output clock signal. A fourth inverter having variable pull-up and pull-down resistances inverts the intermediate clock signal from the second inverter to form a complement output clock signal. The tuning for the variable pull-up and pull-down resistances for the third inverter match that applied to the second inverter. Similarly, the tuning for the variable pull-up and pull-down resistances for the fourth inverter match that applied to the first inverter.

The resulting duty cycle correction is quite advantageous in that it is stable over a wide range of process, voltage, and temperature variations for an integrated circuit including an implementation of the disclosed duty cycle correction circuits. For example, suppose that the duty cycle for the input clock signal is too small. In that case, the duty cycle for the complement input clock signal would be too large. Since the duty cycle for the input clock signal is too small, the variable pull-up resistance for the first inverter is increased from its default value. Conversely, the variable pull-down resistance for the second inverter is increased from its default value. Since the third inverter gets the tuning of the second inverter, a variable pull-down resistance for the third inverter is increased from its default value by the same amount applied to the variable pull-down resistance for the second inverter. The variable pull-up resistance for the fourth inverter is increased from its default value by the same amount applied to the variable pull-up resistance for the first inverter. It will be appreciated that this complementary tuning of third and fourth inverters may be varied in alternative implementations such that the increases in the pull-up or pull-down resistances does not exactly match that increase applied to the corresponding first or second inverter.

Should the duty cycle for the input clock signal be too large, the variable pull-down resistances for the first and fourth inverters is increased from their default value by the same amount. Similarly, the variable pull-up resistances for the second and third inverters would be increased from their default level by the same amount (as noted earlier, the timing of the third and fourth inverters need not be exactly matched to the tuning for the corresponding first or second inverter). Regardless of whether the duty cycle for the input clock signal is too large or too small, the adjustment of both the rising and falling edges for the output clock signal and the complement output signal provides a stable duty cycle adjustment across a wide range of process, voltage, and temperature corners.

Each of the inverters includes an inverter PMOS transistor having a drain connected to a drain of an inverter NMOS transistor. These connected drains form an output node for the inverter. The input clock signal to each inverter drives a gate for the inverter's inverter PMOS transistor and a gate for the inverter NMOS transistor. The variable pull-up resistance is implemented by a variable-resistance PMOS transistor. This variable-resistance PMOS transistor may be coupled between a source of the inverter PMOS transistor and a power supply node in a first implementation for the duty cycle correction circuit. In such an implementation, the variable-resistance PMOS transistor does not load the output node for the inverter. Alternatively, the variable-resistance PMOS transistor may be coupled in parallel with the inverter PMOS transistor in a second implementation for a duty cycle correction circuit. Although the second implementation loads the output node, it provides a larger tuning range for the variable pull-up resistance as compared to the first implementation with the same size variable-resistance PMOS transistor. Analogous to the variable-resistance PMOS transistor, a source for the inverter NMOS transistor may couple to ground through a variable-resistance NMOS transistor. Alternatively, the variable-resistance NMOS transistor may be coupled in parallel with the inverter NMOS transistor. Some example duty cycle correction circuits will now be discussed in more detail.

A duty cycle correction circuit 200 is shown in FIG. 2 in which the variable resistance tuning for both pull-up and pull-down does not directly load the output nodes for an output clock signal (clk out) and a complement output clock signal (clkb out). As discussed earlier, there are four inverters with a variable pull-up resistance and a variable pull-down resistance in duty cycle correction circuit 200 . A first inverter 105 functions as discussed analogously with regard to duty cycle correction circuit 100 to invert an input clock signal (clk in). But the output of first inverter 105 in duty cycle correction circuit 200 is merely an intermediate complement clock signal (clkbi) that is inverted by a third inverter 210 to produce the output clock signal. A second inverter 110 also functions analogously as discussed with regard to duty cycle correction circuit 100 to invert a complement input clock signal (clkb in). But the output of inverter 110 in duty cycle correction circuit 200 is an intermediate clock signal (clki) that is inverted by a fourth inverter 205 to produce the complement output clock signal (clkb out).

Third inverter 210 is structurally identical to second inverter 110 except that third inverter 210 inverts the complement intermediate clock signal as opposed to inverting the complement input clock signal. Third inverter 210 thus includes an inverter PMOS transistor P 4 having its drain connected to a drain of an inverter NMOS transistor M 4 . The source of transistor P 4 couples to the power supply node through a parallel combination of a pull-up PMOS transistor P 5 and a variable-resistance PMOS transistor P 6 . Variable-resistance transistor P 6 is implemented by a plurality of (N+1) PMOS transistors ranging from a zeroth transistor P 6 0 to an Nth transistor P 6 N . During normal operation, pull-up transistor P 5 is maintained on by an active-low complement enable signal enb. The resistance of variable-resistance transistor P 6 depends upon the second pull-up tuning signal Ctrlbn<0:N>. The second pull-up tuning signal is an (N+1) bit-wide digital word. A zeroth bit (Ctrlbn<0>) of the second pull-up tuning signal drives the gate of zeroth transistor P 6 0 . Similarly, a first bit (Ctrlbn<1>) drives the gate of a first transistor P 6 1 (not illustrated) and so on such that an Nth bit (Ctrlbn<N>) drives the gate of the Nth transistor P 6 N .

The second pull-up tuning signal Ctrlpn<0:N> for inverter 210 depends upon the pull-up resistance tuning applied to the corresponding variable-resistance transistor P 6 in second inverter 110 . Should the complement input clock signal have too small of a duty cycle, one of more bits in the second pull-up tuning signal are asserted to the power supply voltage VDD to switch off their corresponding PMOS transistor in variable-resistance transistor P 6 to increase the variable pull-up resistance for second inverter 110 . Since the same second pull-up tuning signal is applied to third inverter 210 , its variable pull-up resistance is increased by the same amount as applied to second inverter 110 . The default state of the second pull-up tuning signal determines the default value for the variable pull-up resistance for second inverter 110 and also for third inverter 210 . For example, the default state for the bits in the second pull-up tuning signal may be all zeroes such that all the transistors P 6 0 through P 6 N are on in the default state.

The pull-down tuning for third inverter 210 is analogous. The source of inverter transistor M 4 couples to the ground through a parallel combination of a pull-down NMOS transistor M 5 and a variable-resistance NMOS transistor M 6 . Variable-resistance transistor M 6 is implemented by a plurality of (N+1) NMOS transistors ranging from a zeroth transistor M 6 0 to an Nth transistor M 6 N . During normal operation, pull-down transistor M 5 is maintained on by an active-high enable signal en (complement enable signal enb being the complement of the enable signal en). The resistance of variable-resistance transistor M 6 depends upon the second pull-down tuning signal Ctrl<0:N>. This second pull-down tuning signal is an (N+1) bit-wide digital word. A zeroth bit (Ctrl<0>) of the second pull-down tuning signal drives the gate of zeroth transistor M 6 0 . Similarly, a first bit (Ctrl<1>) drives the gate of a first transistor M 6 1 (not illustrated) and so on such that an Nth bit drives the gate of the Nth transistor M 6 N . Depending upon which bits are grounded or asserted in the second pull-down tuning signal determines the variable pull-down resistance for third inverter 210 .

The second pull-down tuning signal for third inverter 210 depends upon the variable pull-down resistance tuning applied to the corresponding variable-resistance transistor M 6 in second inverter 110 . Should the complement input clock signal have too large of a duty cycle, one of more bits in the second pull-up tuning signal are grounded to switch off their corresponding NMOS transistor in variable-resistance transistor M 6 to increase the variable pull-down resistance for second inverter 110 . Since the same second pull-up tuning signal is applied to third inverter 210 , its variable pull-down resistance is increased by the same amount as applied to second inverter 110 . The default state of the second pull-down tuning signal determines the default value for the variable pull-down resistance. For example, the default state may be that all the bits in the second pull-up tuning signal are binary ones such that all the transistors P 6 0 through P 6 N are on in the default state.

Fourth inverter 205 is structurally identical to first inverter 105 except that it inverts the intermediate clock signal clki as opposed to inverting the input clock signal. Fourth inverter 205 thus includes an inverter PMOS transistor P 1 having its drain connected to a drain of an inverter NMOS transistor M 1 . The source of transistor P 1 couples to the power supply node through a parallel combination of a pull-up PMOS transistor P 2 and a variable-resistance PMOS transistor P 3 . Variable-resistance transistor P 3 is implemented by a plurality of (N+1) PMOS transistors ranging from a zeroth transistor P 3 0 to an Nth transistor P 3 N . During normal operation, pull-up transistor P 2 is maintained on by the active-low complement enable signal enb. The resistance of variable-resistance transistor P 3 depends upon the first pull-up tuning signal Ctrlbp<0:N>. The first pull-up tuning signal is an (N+1) bit-wide digital word. A zeroth bit (Ctrlbp<0>) of the first pull-up tuning signal drives the gate of zeroth transistor P 3 0 . Similarly, a first bit (Ctrlbp<1>) drives the gate of a first transistor P 3 1 (not illustrated) and so on such that an Nth bit (Ctrlbp<N>) drives the gate of the Nth transistor P 3 N .

The first pull-up tuning signal (Ctrlbp<0:N>) for fourth inverter 205 depends upon the pull-up resistance tuning applied to the corresponding variable-resistance transistor P 3 in first inverter 105 . Should the input clock signal have too small of a duty cycle, one of more bits in the first pull-up tuning signal are asserted to the power supply voltage VDD to switch off their corresponding PMOS transistor in variable-resistance transistor P 3 to increase the variable pull-up resistance for first inverter 105 . Since the same first pull-up tuning signal is applied to fourth inverter 205 , its variable pull-up resistance is increased by the same amount as applied to first inverter 105 . The default state of the first pull-up tuning signal determines the default value for the variable pull-up resistance for inverters 105 and 205 . For example, the default state may be that the all the bits in the first pull-up tuning signal are zeroes such that all the transistors P 3 0 through P 3 N are on.

The pull-down tuning for fourth inverter 205 is analogous. The source of inverter transistor M 1 couples to ground through a parallel combination of a pull-down NMOS transistor M 2 and a variable-resistance NMOS transistor M 3 . Variable-resistance transistor M 3 is implemented by a plurality of (N+1) NMOS transistors ranging from a zeroth transistor M 3 0 to an Nth transistor M 3 N . During normal operation, pull-down transistor M 2 is maintained on by the active-high enable signal en. The resistance of variable-resistance transistor M 3 depends upon the first pull-down tuning signal Ctrln<0:N>. This first pull-down tuning signal is an (N+1) bit-wide digital word. A zeroth bit (Ctrln<0>) of the first pull-down tuning signal drives the gate of zeroth transistor M 3 0 . Similarly, a first bit (Ctrln<1>) drives the gate of a first transistor M 3 1 (not illustrated) and so on such that an Nth bit (Ctrln<N>) drives the gate of the Nth transistor M 3 N . Depending upon which bits are grounded or asserted in the first pull-down tuning signal determines the variable pull-down resistance for fourth inverter 205 .

The first pull-down tuning signal for fourth inverter 205 depends upon the pull-down resistance tuning applied to the corresponding variable-resistance transistor M 3 in first inverter 105 . Should the input clock signal have too large of a duty cycle, one of more bits in the first pull-down tuning signal are grounded to switch off their corresponding NMOS transistor in variable-resistance transistor M 3 to increase the variable pull-down resistance for first inverter 105 from its default value. Since the same first pull-down tuning signal is applied to fourth inverter 205 , its variable pull-down resistance is increased by the same amount as applied to first inverter 105 . The default state of the first pull-down tuning signal determines the default value for the variable pull-down resistance. For example, the default state may be that the all the bits in the first pull-down tuning signal are binary ones such that all the transistors P 3 0 through P 3 N are on in the default state. A memory 250 stores the first pull-up tuning signal (Ctrlbp<0:N>), the first pull-down tuning signal (Ctrln<0:N>), the second pull-up tuning signal (Ctrlbn<0:N>), and the second pull-down tuning signal (Ctrl<0:N>) to control the pull-up and pull-down tuning for duty cycle correction circuit 200 .

Duty cycle correction circuit 200 is an example of the first implementation discussed above in that the variable-resistance transistors do not directly couple to the output nodes for first inverter 105 , third inverter 210 , second inverter 110 , and fourth inverter 205 . Although the output clock signals are thus advantageously not loaded by the variable-resistance transistors, the tuning range is limited as compared to the second implementation in which the variable-resistance transistors directly couple to the output nodes. An example of the second implementation is shown in FIG. 3 for a duty cycle correction circuit 300 . Analogous to duty cycle correction circuit 200 , duty cycle correction circuit 300 includes four inverters, each with a variable pull-up resistance and a variable pull-down resistance. A first inverter 305 inverts the input clock signal (clk in) into an intermediate complement clock signal (clkbi) that is in turn inverted by a second inverter 315 to form the output clock signal (clk out). A third inverter 310 inverts the complement input clock signal (clkb in) into an intermediate clock signal (clki) that is turn is inverted by a fourth inverter 320 to form the complement output clock signal (clkb out).

Second inverter 315 replicates the structure of third inverter 310 and has the same pull-up or pull-down tuning. Similarly, fourth inverter 320 replicates the structure of first inverter 305 and has the same pull-up or pull-down tuning. Thus, FIG. 3 shows only the structure for first inverter 305 and third inverter 310 as the remaining inverters are duplicates but for their inputs and outputs. In first inverter 305 , an inverter PMOS transistor P 7 has its drain connected to a drain of an inverter NMOS transistor M 7 . The input clock signal drives the gates of inverter transistors P 7 and M 7 . The source of transistor P 7 connects to the power supply node through a pull-up PMOS transistor P 9 . The complement enable signal enb drives the gate of transistor P 9 so that first inverter 305 is powered during normal operation. A variable-resistance PMOS transistor P 8 couples in parallel with inverter transistor P 7 between the output node for first inverter 305 and the drain of pull-up transistor P 9 . Variable-resistance transistor P 8 is implemented by a plurality of (N+1) PMOS transistors ranging from a zeroth transistor P 8 0 to an Nth transistor P 8 N . The first pull-up tuning signal tunes variable-resistance transistor P 8 analogously as discussed with regard to the pull-up resistance tuning of first inverter 105 .

A source of inverter transistor M 7 couples to ground through an NMOS pull-down transistor M 9 . The enable signal en drives the gate of pull-down transistor M 9 so that first inverter 305 is grounded during normal operation. A variable-resistance NMOS transistor M 10 couples in parallel with inverter transistor M 7 between the output node for first inverter 305 and a drain of pull-down transistor M 9 . Variable-resistance transistor M 10 is implemented by a plurality of (N+1) NMOS transistors ranging from a zeroth transistor M 10 0 to an Nth transistor M 10 N . The first pull-down tuning signal tunes variable-resistance transistor M 10 analogously as discussed with regard to the pull-down resistance tuning of first inverter 105 . The complement intermediate clock signal on the output node of first inverter 305 (the drains of inverter transistors P 7 and M 7 ) drives an input node to second inverter 315 . Since the structure of second inverter 315 and its tuning duplicates that of third inverter 310 , third inverter 310 will now be discussed in more detail.

Third inverter 310 includes an inverter PMOS transistor P 11 having its drain connected to a drain of an inverter NMOS transistor M 11 . The complement input clock signal drives the gates of inverter transistors P 11 and M 11 . The source of transistor P 11 connects to the power supply node through a pull-up PMOS transistor P 13 . The complement enable signal enb drives the gate of transistor P 13 so that third inverter 310 is powered during normal operation. A variable-resistance PMOS transistor P 12 couples in parallel with inverter transistor P 11 between the output node for third inverter 310 (the drains of inverter transistors P 11 and M 11 ) and the drain of pull-up transistor P 13 . Variable-resistance transistor P 12 is implemented by a plurality of (N+1) PMOS transistors ranging from a zeroth transistor P 12 0 to an Nth transistor P 12 N . The second pull-up tuning signal tunes the resistance for variable-resistance transistor P 12 analogously as discussed with regard to the pull-up resistance tuning of second inverter 110 .

A source of inverter transistor M 11 couples to ground through an NMOS pull-down transistor M 12 . The enable signal en drives the gate of pull-down transistor M 12 so that third inverter 310 is grounded during normal operation. A variable-resistance NMOS transistor M 14 couples in parallel with inverter transistor M 11 between the output node for third inverter 310 and a drain of pull-down transistor M 12 . Variable-resistance transistor M 14 is implemented by a plurality of (N+1) NMOS transistors ranging from a zeroth transistor M 14 0 to an Nth transistor M 14 N . The second pull-down tuning signal tunes variable-resistance transistor M 14 analogously as discussed with regard to the pull-down resistance tuning of second inverter 110 . The intermediate clock signal on the output node of third inverter 310 (the drains of inverter transistors P 11 and M 11 ) drives an input node to fourth inverter 320 .

The tuning for fourth inverter 320 replicates the tuning applied to first inverter 305 . Similarly, the tuning for second inverter 315 replicates the tuning applied to third inverter 310 . A method of correcting the duty cycle for a clock signal will now be discussed.

A flowchart for an example method of correcting the duty cycle for an input clock signal is shown in FIG. 4 . The method includes an act 400 of inverting an input clock signal in a first inverter having a first pull-up resistance tuned according to a first pull-up tuning signal and having a first pull-down resistance tuned according to a first pull-down tuning signal, the first inverter inverting the input clock signal to produce an inverted clock signal. The inversion of the input clock signal (clk in) in either first inverter 105 of duty cycle correction circuit 200 or in first inverter 305 of duty cycle correction circuit 300 is an example of act 400 . The method further includes an act 405 of inverting a complement of the input clock signal in a second inverter having a second pull-up resistance tuned according to a second pull-up resistance and having a second pull-down resistance tuned according to a second pull-down signal, the second inverter inverting the complement of the input clock signal to form a first clock signal. The inversion of the complement input clock signal (clkb in) in either second inverter 110 of duty cycle correction circuit 200 or in third inverter 310 of duty cycle correction circuit 300 is an example of act 405 . Finally, the method includes an act 410 of inverting the inverted clock signal in a third inverter having the second pull-up resistance and having the second pull-resistance to produce an output clock signal having a corrected duty cycle. The inversion of the intermediate complement clock signal (clkbi) in either third inverter 210 of duty cycle correction circuit 200 or second inverter 315 in duty cycle correction circuit 300 is an example of act 410 .

The duty cycle correction circuit as disclosed herein may be incorporated into a wide variety of electronic systems. For example, as shown in FIG. 5 , a cell phone 500 , a laptop 505 , and a tablet PC 510 may all include a duty cycle correction circuit constructed in accordance with the disclosure. Other exemplary electronic systems such as a music player, a video player, a communication device, and a personal computer may also be configured with duty cycle correction circuits constructed in accordance with the disclosure.

It will be appreciated that many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular implementations illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.