Alternator and rectifier thereof

This application claims the priority benefit of Taiwan application serial no. 108100771, filed on Jan. 8, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

The disclosure relates to an alternator and a rectifier thereof, and more particularly to an alternator and a rectifier thereof for reducing power loss.

In an alternator, a rectifier is often used to rectify an alternating current (AC) input voltage and to produce a rectified voltage which may be considered as a direct current (DC) voltage. In the prior art, a diode or a transistor is often used to perform the rectification action of the input voltage. Under an ideal state, the voltage value of the rectified voltage in the negative half cycle should be maintained as equal to a base voltage (for example, 0 volts). However, under a practical situation, as shown in the waveform diagram of the conventional rectified voltage of FIG. 1 , the peak value is the rectified voltage of a voltage VP and in a negative half cycle TN thereof, the voltage value of the rectified voltage is lower than the base voltage V 0 thereof. In other words, in the negative half cycle TN of the rectified voltage, the phenomenon of power loss occurs, thereby reducing the working efficiency of the system.

The disclosure provides an alternator and a rectifier thereof for reducing power loss.

The rectifier of the disclosure includes a transistor and a gate driving circuit. The transistor has a first end for receiving an input voltage, a second end for generating a rectified voltage, and a control end for receiving a gate voltage. The gate driving circuit is coupled to the transistor and generates a gate voltage according to a voltage difference between a rectified voltage and an input voltage. The gate driving circuit detects an initial time point when the voltage difference is smaller than a first preset threshold voltage, provides the gate voltage to turn on the transistor during a first time period after the initial time point, and sets the voltage difference to be equal to a first reference voltage. The gate driving circuit gate sets the voltage difference to be equal to a second reference voltage through adjusting the gate voltage during a second time period after the first time period.

In an embodiment of the disclosure, the first reference voltage may be larger than, smaller than, or equal to the second reference voltage.

In an embodiment of the disclosure, the first reference voltage equals to the product of the conductive resistance of the transistor and the current flowing through the transistor.

In an embodiment of the disclosure, the gate driving circuit detects a second time point when the voltage difference rises from the second reference voltage to a second preset threshold voltage during a third time period after the second time period and adjusts the gate voltage to set the transistor to be cut off after the second time point.

In an embodiment of the disclosure, the gate driving circuit includes an operational amplifier, a first switch, and a second switch. The operational amplifier receives the voltage difference and adjusts the voltage according to a first control signal to generate the gate voltage at the output end. The first switch is connected in series between a first voltage and the output end, and is turned on or off according to a second control signal. The second switch is connected in series between a second voltage and the output end, and is turned on or off according to a third control signal.

In an embodiment of the disclosure, the gate driving circuit further includes a control signal generator. The control signal generator sets the voltage difference to be compared with the first preset threshold voltage or the second preset threshold voltage to generate a comparison result and generates the first control signal, the second control signal, and the third control signal according to the comparison result.

In an embodiment of the disclosure, the control signal generator includes a comparator, a selector, and a counter. The comparator receives the voltage difference and a selected voltage, and generates the comparison result. The counter is coupled to the comparator, performs a counting action according to the comparison result, and generates the first control signal, the second control signal, and the third control signal.

In an embodiment of the disclosure, the counter performs the counting action between the first time point and the second time point to generate a count value, wherein the first time period is when the count value is smaller than a reference value and the second time period is when the count value is between the reference value and the maximum count value.

In an embodiment of the disclosure, the gate driving circuit further includes a voltage generator. The voltage generator generates a second voltage, a second reference voltage, a first preset threshold voltage, and a second preset threshold voltage according to an operation power.

In an embodiment of the disclosure, the voltage generator includes a voltage regulator and a reference voltage generator. The power adjuster generates the first voltage according to the operation power and generates a first power source and a second power source of the operational amplifier and the counter. The reference voltage generator generates the first preset threshold voltage, the second preset threshold voltage, and an adjustment voltage according to the operation power.

In an embodiment of the disclosure, the rectifier further includes a diode and a capacitance. The anode of the diode is coupled to the first end of the transistor and the cathode of the diode is coupled to the endpoint of the gate driving circuit receiving the operation power. The capacitance is coupled between the cathode of the diode and the second end of the transistor.

The alternator of the disclosure includes a rotor, a stator, and a plurality of the rectifiers above. Each of the rectifiers receives the corresponding AC input voltage as the input voltage to generate the rectified voltage together with the rectifier.

Based on the above, the rectifier of the disclosure maintains the voltage difference in the negative half cycle across the two ends of the transistor to be equal to the first reference voltage during the first time period, wherein the first reference voltage is generated as the product value of the equivalent resistance of the conducting transistor and the current flowing through the conducting transistor, and the voltage difference in the negative half cycle across the two ends of the transistor is maintained to be equal to the second reference voltage during the second time period, wherein the first reference voltage may be larger than, smaller than, or equal to the second reference voltage. As such, power loss in the rectifier may be reduced, thereby improving the working efficiency.

To make the aforementioned and other features of the disclosure more comprehensible, several embodiments accompanied with drawings are described in detail as follows.

FIG. 1 illustrates a waveform of a conventional rectified voltage.

FIG. 2 is a schematic diagram of a rectifier according to an embodiment of the disclosure.

FIG. 3A is a schematic diagram of a waveform of a voltage difference according to an embodiment of the disclosure.

FIG. 3B and FIG. 3C are schematic diagrams of waveforms of voltage differences according to different embodiments of the disclosure.

FIG. 4A is a schematic diagram of waveforms of a voltage difference, a transistor current, and a gate voltage according to an embodiment of the disclosure.

FIG. 4B is a partially enlarged diagram of the waveforms of the voltage difference and the gate voltage in FIG. 4A .

FIG. 4C is a schematic diagram of waveforms of a voltage difference, a transistor current, and a gate voltage according to another embodiment of the disclosure.

FIG. 4D is a partially enlarged diagram of the waveforms of the voltage difference and the gate voltage in FIG. 4C .

FIG. 5 is a schematic diagram of a gate driving circuit according to an embodiment of the disclosure.

FIG. 6 illustrates implementing a control signal generator according to an embodiment of the disclosure.

FIG. 7 is a schematic diagram of implementing a counting action of a counter according to an embodiment of the disclosure.

FIG. 8 illustrates implementing a voltage generator according to an embodiment of the disclosure.

FIG. 9 is a schematic diagram of a rectifier according to another embodiment of the disclosure.

FIG. 10 is a schematic diagram of an alternator according to an embodiment of the disclosure.

Please refer to FIG. 2 . FIG. 2 is a schematic diagram of a rectifier according to an embodiment of the disclosure. A rectifier 200 includes a transistor TD 1 and a gate driving circuit 210 . The transistor TD 1 has a first end for receiving an input voltage VS, a second end for generating a rectified voltage VD, and a control end for receiving a gate voltage VG. In the embodiment, the operation of the transistor TD 1 is equivalent to a diode through the gate voltage VG. The first end of the transistor TD 1 may be equivalent to an anode of the diode, and the second end of the transistor TD 1 may be equivalent to a cathode of the diode.

The gate driving circuit 210 is coupled to the transistor TD 1 and is used to provide the gate voltage VG. The gate driving circuit 210 receives a voltage difference VDS between the rectifier voltage VD and the input voltage VS, and generates the gate voltage VG according to the voltage difference VDS. Regarding the details of generating the gate voltage VG, the gate driving circuit 210 detects a variation of the voltage difference VDS. The gate driving circuit 210 detects an initial time point when the voltage difference VDS is smaller than a first preset threshold voltage and provides the gate voltage VG to turn on the transistor TD 1 during a first time period after the initial time point. Also, under the condition that the transistor TD 1 is turned on according to the gate voltage VG, the voltage difference VDS may be equal to a first reference voltage.

Next, the gate driving circuit 210 adjusts the equivalent resistance value provided by the transistor TD 1 through adjusting the gate voltage VG during a second time period after the first time period and sets the voltage difference VDS to be equal to a second reference voltage, wherein the first reference voltage may be larger than, smaller than, or equal to the second reference voltage.

Please note that during the first time period, taking the transistor TD 1 as a N-type transistor as an example, the gate driving circuit 210 may provide the gate voltage VG with a relatively high voltage to the control end of the transistor TD 1 , and set the transistor TD 1 to be completely turned on. Under such situation, the first reference voltage above may be equal to the product of the conductive resistance of a completely or incompletely conducting transistor TD 1 and the current flowing through the transistor TD 1 . If the transistor TD 1 is in a completely conducting state, the conductive resistance of the transistor TD 1 is extremely small, so the voltage difference VDS may be maintained to be equal to the first reference voltage close to 0 volts (V). During the second time period after the first time period, the gate driving circuit 210 may lower the voltage value of the gate voltage VG, and set the resistance of the transistor TD 1 in the conducting state to increase. At this time, the gate voltage VG provided by the gate driving circuit 210 may set the voltage difference VDS to the second reference voltage which may be larger than, smaller than, or equal to the first reference voltage. In an embodiment, the second reference voltage may be approximately equal to −70 millivolts (mV).

On the other hand, the gate driving circuit 210 determines the initial time point through detecting whether the voltage difference VDS is smaller than the first preset threshold voltage or not. In the embodiment of the disclosure, the first preset threshold voltage may be smaller than the first reference voltage and the second reference voltage. When the voltage difference VDS falls below the first preset threshold voltage, the gate driving circuit 210 may determine the initial time point and initiate the adjustment mechanism of the gate voltage VG. In an embodiment, the first preset threshold voltage may be equal to −300 mV.

It can be known from the above description that in the rectifier 200 according to the embodiment of the disclosure, the voltage value range lower than 0V of the voltage difference VDS may be controlled by adjusting the gate voltage VG through the gate driving circuit 210 , thereby effectively reducing unnecessary power loss.

Continuing from the above embodiment, after the second time period, the current flowing through the transistor TD 1 becomes smaller as the input voltage changes. With the adjustment action of the gate voltage VG, the voltage difference VDS starts to rise during the third time period after the second time period. The gate driving circuit 210 may detect whether the voltage difference VDS rises from the second reference voltage to be equal to the second preset threshold voltage during the third time period and sets the second time point when the voltage difference VDS rises to be equal to the second preset threshold voltage. Furthermore, the gate driving circuit 210 sets the transistor TD 1 to be cut off through adjusting the gate voltage VG after the second time point.

Please refer to FIG. 2 and FIG. 3A for the following. FIG. 3A is a schematic diagram of a waveform of a voltage difference according to an embodiment of the disclosure. The voltage difference VDS has a peak value of a voltage VP and has a base voltage V 0 . A positive half cycle of the voltage difference VDS is between time points t 0 and t 1 , and a negative half cycle of the voltage difference VDS is between time points t 1 and t 2 . After the time point t 1 , the gate driving circuit 210 detects whether the voltage difference VDS is lower than a first preset threshold voltage VDS_ON and sets an initial time point TP 1 when the voltage difference VDS is lower than the first preset threshold voltage VDS_ON.

During the first time period TZ 1 after the initial time point TP 1 , the gate driving circuit 210 may set the transistor TD 1 to be turned on through providing the gate voltage VG and set the voltage difference VDS to be substantially maintained to be equal to a first reference voltage VDS_SW 2 . Here, the first reference voltage VDS_SW 2 is the product of the conductive resistance of the transistor and the current flowing through the transistor.

Next, the gate driving circuit 210 may set the voltage difference VDS to be maintained as equal to a second reference voltage VDS_REG through adjusting the gate voltage VG during a second time period TZ 2 after the first time period TZ 1 .

During a third time period TZ 3 after the second time period TZ 2 , the voltage difference VDS starts to rise as the current flowing through the transistor TD 1 decreases and the adjustment action of the gate voltage VG. Moreover, the gate driving circuit 210 may detect whether the voltage difference VDS is larger than a second preset threshold voltage VDS_OFF and sets a second time point TP 2 when the voltage difference VDS is larger than the second preset threshold voltage VDS_OFF. The gate driving circuit 210 sets the transistor TD 1 to be cut off through adjusting the gate voltage VG after the second time point TP 2 .

In the embodiment, the second preset threshold voltage VDS_OFF is larger than the first reference voltage VDS_SW 2 , the first reference voltage VDS_SW 2 is larger than the second reference voltage VDS_REG, and the second reference voltage VDS_REG is larger than the first preset threshold voltage VDS_ON.

In addition, please refer to FIG. 3B and FIG. 3C . FIG. 3B and FIG. 3C are schematic diagrams of waveforms of voltage differences according to different embodiments of the disclosure. Unlike the embodiment of FIG. 3A , in FIG. 3B , the first reference voltage VDS_SW 2 is smaller than the second reference voltage VDS_REG. In FIG. 3C , the first reference voltage VDS_SW 2 is equal to the second reference voltage VDS_REG.

Please refer to FIG. 4A and FIG. 4B for the following. FIG. 4A is a schematic diagram of waveforms of a voltage difference, a transistor current, and a gate voltage according to an embodiment of the disclosure. FIG. 4B is a partially enlarged diagram of the waveforms of the voltage difference and the gate voltage in FIG. 4A . In FIG. 4A , during the first time period TZ 1 , a gate voltage generating circuit adjusts the gate voltage VG to have a relatively high voltage value, thereby setting the transistor to be completely turned on, and sets the voltage difference VDS to be substantially maintained as equal to the first reference voltage. Between the second time period TZ 2 and the third time period TZ 3 , the gate voltage generating circuit sets the voltage difference VDS to be equal to the second reference voltage during the second time period and sets the voltage difference VDS to start rising slightly during the third time period through adjusting the gate voltage VG. The gate voltage generating circuit provides the gate voltage VG with a relatively low voltage to turn off the transistor after the third time period TZ 3 ends. In FIG. 4A , a transistor current IDS changes periodically.

Regarding the relationship between the first reference voltage and the second reference voltage, reference may be made to FIG. 4B . In FIG. 4B , the voltage difference VDS may be equal to the first reference voltage VDS_SW 2 during the first time period TZ 1 through the gate voltage VG having a relatively high voltage. It is worth mentioning that in FIG. 4B , the voltage difference VDS does not immediately equal to the first reference voltage VDS_SW 2 during the first time period TZ 1 . Instead, the voltage difference VDS gradually approaches the first reference voltage VDS_SW 2 due to parasitic capacitance effect in circuit components. Basically, the voltage difference VDS may be substantially equal to the first reference voltage VDS_SW 2 during the first time period TZ 1 .

During the second time period TZ 2 , the gate driving circuit provides a gradually decreasing gate voltage VG and sets the voltage difference VDS to be substantially equal to the second reference voltage VDS_REG during the second time period TZ 1 .

In FIG. 4A and FIG. 4B , a length of the third time period TZ 3 with respect to a length of the second time period TZ 2 is very short.

Please refer to FIG. 4C and FIG. 4D for the following. FIG. 4C is a schematic diagram of waveforms of a voltage difference, a transistor current, and a gate voltage according to another embodiment of the disclosure. FIG. 4D is a partially enlarged diagram of the waveforms of the voltage difference and the gate voltage in FIG. 4C . In FIG. 4C , during the first time period TZ 1 , the gate voltage generating circuit adjusts the gate voltage VG to have a relatively low (relative to the second time period TZ 2 ) voltage value, thereby setting the transistor to be partially turned on, and sets the voltage difference VDS to be substantially equal to the first reference voltage. Between the second time period TZ 2 and the third time period TZ 3 , the gate voltage generating circuit sets the voltage difference VDS to be equal to the second reference voltage during the second time period TZ 2 and sets the voltage difference VDS to start rising slightly during the third time period TZ 3 through increasing the gate voltage VG. It can be clearly known from FIG. 4D that the voltage difference VDS is substantially equal to the first reference voltage VDS_SW 2 during the first time period TZ 1 and is substantially equal to the second reference voltage VDS_REG during the second time period TZ 2 , wherein the first reference voltage VDS_SW 2 is smaller than the second reference voltage VDS_REG.

Similarly, in FIG. 4D , the voltage difference VDS does not immediately equal to the first reference voltage VDS_SW 2 during the first time period TZ 1 . Instead, the voltage difference VDS gradually approaches the first reference voltage VDS_SW 2 due to parasitic capacitance effect in circuit components. Basically, the voltage difference VDS may be substantially equal to the first reference voltage VDS_SW 2 during the first time period TZ 1 . The voltage difference VDS also does not immediately equal to the second reference voltage VDS_REG during the second time period TZ 2 . Instead, the voltage difference VDS gradually approaches the second reference voltage VDS_REG due to parasitic capacitance effect in circuit components. Basically, the voltage difference VDS may be substantially equal to the second reference voltage VDS_REG during the second time period TZ 2 .

Please refer to FIG. 5 . FIG. 5 is a schematic diagram of a gate driving circuit according to an embodiment of the disclosure. A gate driving circuit 500 includes an operational amplifier OP 1 , a switch SW 1 , and a switch SW 2 . The operational amplifier OP 1 receives the voltage difference VDS and the adjustment voltage as the second reference voltage VDS_REG, and generates the gate voltage VG at an output end OT according to a control signal EN_OPA. In addition, the operational amplifier OP 1 receives a power VA as the working power source and receives a voltage VS as the reference ground voltage. The switch SW 2 is connected in series between the voltage VH and the output end OT. The switch SW 2 is turned on or off according to the control signal EN_SW 2 . The switch SW 1 is connected in series between the voltage VS and the output end OT. The switch SW 1 is turned on or off according to the control signal EN_SW 1 .

In terms of action details, the gate driving circuit 500 sets the operational amplifier OP 1 to be disabled through the control signal EN_OPA after the initial time point when the voltage difference VDS is smaller than the first preset threshold voltage (during the first time period) and sets the switch SW 2 to be turned on through the control signal EN_SW 2 to raise the gate voltage VG to the voltage VH. At the same time, the switch SW 1 is cut off according to the control signal EN_SW 1 . Next, during the second time period after the first time period, the gate driving circuit 500 sets the switches SW 2 and SW 1 to be respectively cut off through the control signals EN_SW 2 and EN_SW 1 , and sets the operational amplifier OP 1 to be activated through the control signal EN_OPA. During the second time period, the operational amplifier OP 1 provides the gate voltage VG at the output end OT through controlling the voltage difference VDS to be equal to the second reference voltage VDS_REG. Next, during the third time period, the gate driving circuit 500 sets the switch SW 2 to be cut off through the control signals EN_SW 2 and EN_OPA respectively, and sets the operational amplifier OP 1 to be disabled. Also, during the third time period, the gate driving circuit 500 sets the switch SW 1 to be turned on through the control signal EN_SW 1 . Through the conducted switch SW 1 , the gate voltage VG is pulled down to be equal to the voltage VS and the transistor is cut off.

Regarding the above embodiment, the control signals EN_OPA, EN_SW 1 , and EN_SW 2 may be generated through setting a control signal generator in the gate driving circuit 500 . For the implementation of the control signal generator, reference may be made to FIG. 6 . In FIG. 6 , a control signal generator 600 includes a selector 610 , a comparator CMP 1 , and a counter 620 . The selector 610 receives a first preset threshold voltage VDS_ON and a second preset threshold voltage VDS_OFF, and is used to select the first preset threshold voltage VDS_ON or the second preset threshold voltage VDS_OFF to be provided to the comparator CMP 1 . The comparator CMP 1 is coupled to the selector 610 and sets the voltage difference VDS to be compared with one of the first preset threshold voltage VDS_ON and the second preset threshold voltage VDS_OFF to generate a comparison result VCMP. It is worth noting that the comparison result VCMP may be fed back to the selector 610 to set the selector 610 to select one of the first preset threshold voltage VDS_ON and the second preset threshold voltage VDS_OFF according to the comparison result VCMP for output. In details, under the initial state, the selector 610 selects the first preset threshold voltage VDS_ON to output to the comparator CMP 1 . The comparator CMP 1 sets the voltage difference VDS to be compared with the first preset threshold voltage VDS_ON and sets the selector 610 to change to selecting the second preset threshold voltage VDS_OFF to output to the comparator CMP 1 through adjusting the comparison result VCMP when the voltage difference VDS is smaller than the first preset threshold voltage VDS_ON (the initial time point).

Continuing from the above embodiment, next, the comparator CMP 1 sets the voltage difference VDS to be compared with the second preset threshold voltage VDS_OFF and changes the selector 610 to reselect the first preset threshold voltage VDS_ON to output to the comparator CMP 1 through adjusting the comparison result VCMP when the voltage difference VDS is larger than the second preset threshold voltage VDS_OFF (the second time point).

On the other hand, regarding the counting action of the counter 620 , please refer to FIG. 6 and FIG. 7 at the same time. FIG. 7 is a schematic diagram of implementing a counting action of a counter according to an embodiment of the disclosure. The counter 620 is coupled to the comparator CMP 1 and performs the counting action according to the comparison result VCMP. The counting action of the counter 620 starts at the initial time point TP 1 and ends at the second time point TP 2 . The counting action of the counter 620 may produce a gradually changing (incremental or decremental) count value. Taking an incremental counting action as an example, the counter 620 may set the gate driving circuit to operate during the first time period TZ 1 when the count value is smaller than a reference value REFV and set the gate driving circuit to operate during the second interval TZ 2 or the third time period TZ 3 when the count value is between the reference value REFV and a maximum count value C(n). Moreover, the counter 620 may generate the corresponding control signals EN_OPA, EN_SW 1 , and EN_SW 2 according to whether the gate driving circuit operates during the first time period TZ 1 , the second time period TZ 2 , or the third time period TZ 3 .

Regarding the setting of the reference value REFV above, the reference value REFV may be set as the product of the maximum count value C(n) of the counting action and a ratio value a1, wherein the ratio value a1 is larger than or equal to 0 and is smaller than or equal to 1. The C(n−1) in the drawing is the length of the initial time point TP 1 to the second time point TP 2 during the previous cycle.

On the other hand, in the embodiment regarding FIG. 5 above, the voltage VH, the second reference voltage VDS_REG, the first preset threshold voltage VDS_ON, the second preset threshold voltage VDS_OFF, the power VA, and the power VC may be generated through setting a voltage generator in the driving circuit 500 . Regarding the implementation of the voltage generator, reference may be made to FIG. 8 . In FIG. 8 , a voltage generator 800 includes a voltage regulator 810 and a reference voltage generator 820 . The voltage regulator 810 receives an operation power VHH and performs a voltage adjustment action according to the operation power VHH to generate the voltage VH, the power VA, and the power VC. The reference voltage generator 820 also receives the operation power VHH, which is used to generate the second reference voltage VDS_REG, the first preset threshold voltage VDS_ON, and the second preset threshold voltage VDS_OFF.

The hardware structure of the voltage regulator 810 and the reference voltage generator 820 may be constructed by applying any form of voltage generating circuit known by persons with ordinary skill in the art and is not limited thereto.

Please refer to FIG. 9 for the following. FIG. 9 is a schematic diagram of a rectifier according to another embodiment of the disclosure. A rectifier 900 includes a transistor TD 1 , a gate driving circuit 910 , a diode DP, and a capacitance CP. The gate driving circuit 910 may be implemented using the gate driving circuit 500 above. The anode of the diode DP is coupled to the first end of the transistor TD 1 and the cathode of the diode DP is coupled to the endpoint of the gate driving circuit 910 receiving the operation power VHH. The capacitance CP is coupled between the cathode of the diode DP and the second end of the transistor TD 1 .

Please refer to FIG. 10 . FIG. 10 is a schematic diagram of an alternator according to an embodiment of the disclosure. An alternator 1000 includes a rotor RT, a stator ST, and a plurality of rectifiers 1011 - 1032 . In the embodiment, the stator ST generates a plurality of phase voltages VU, VV, and VW. The phase voltages VU, VV, and VW respectively provides to a plurality of rectifier circuits 1010 , 1020 , and 1030 with different phases. The rectifier circuit 1010 includes rectifiers 1011 and 1012 coupled in series, the rectifier circuit 1020 includes rectifiers 1021 and 1022 coupled in series, and the rectifier circuit 1030 includes rectifiers 1031 and 1032 coupled in series. In the embodiment, the alternator 1000 includes a resistance R 1 (which is an equivalent load or an equivalent resistance of a rechargeable battery) coupled in parallel and a capacitance C 1 which is an equivalent charging capacitance used to generate a rectified output voltage close to a DC.

In summary, the disclosure generates the gate voltage through the gate driving circuit and controls the voltage value of the voltage difference in the negative half cycle across two ends of the transistor through the gate voltage. As a result, the power loss which may be generated by the rectifier can be reduced, thereby improving the working efficiency.

Although the disclosure has been disclosed in the above embodiments, the embodiments are not intended to limit the disclosure. It will be apparent to persons skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.