Switching regulator, semiconductor integrated circuit, and electronic appliance

The present invention relates to a switching regulator. The present invention also relates to a semiconductor integrated circuit used in a switching regulator. The present invention further relates to an electronic appliance using a switching regulator.

One example of switching regulators with high efficiency under a light load is a switching regulator proposed in Patent Document 1.

The switching regulator proposed in Patent Document 1 stops switching control under a light load and holds an upper switching element and a lower switching element in an off state. Stopping switching control eliminates switching loss, and thus the switching regulator proposed in Patent Document 1 offers high efficiency under a light load.

When the switching regulator proposed in Patent Document 1 finds an output voltage to have lowered while not performing switching control, it restarts switching control. After switching control is restarted, the switching regulator proposed in Patent Document 1 stops switching control again if the load is light, and continues switching control if the load is heavy.

Patent Literature

Patent Document 1: JP-A-H06-303766

Problem to be Solved by the Invention

However, in the switching regulator proposed in Patent Document 1, under a light load, if the charge current of an output capacitor that is generated by the leakage current of the upper switching element is larger than the discharge current of the output capacitor that is generated by the leakage current of the lower switching element and a consumption current of the load, the output voltage increases. In that case, switching control is not restarted, and the output voltage eventually becomes an overvoltage.

Against the background discussed above, it is an object of the present invention to provide a switching regulator that can prevent the output voltage from increasing while suppressing lowering of efficiency at low temperature during a period in which switching control is not performed, as well as to provide a semiconductor integrated circuit used in the switching regulator and an electronic appliance using the switching regulator.

Means for Solving the Problem

A switching regulator disclosed herein is a switching regulator configured to generate an output voltage from an input voltage, and comprises an upper switch of which a first terminal is connected to a first application terminal to which the input voltage is applied, a lower switch of which a first terminal is connected to a second terminal of the upper switch and of which a second terminal is connected to a second application terminal to which a predetermined voltage lower than the input voltage is applied, an inductor of which a first terminal is connected to a connection node between the upper switch and the lower switch, an output capacitor connected to a second terminal of the inductor, a controller configured to generate a control signal for complementarily turning on and off the upper switch and the lower switch according to the output voltage, and a current extractor configured to extract a constant current from the first terminal or the second terminal of the inductor. In the switching regulator disclosed herein, the controller is configured, under a light load, to stop switching control and hold the upper switch and the lower switch in an off state, and the constant current may have a positive temperature characteristic and the value of the constant current may be larger than the value obtained by subtracting the leakage current of the lower switch from the leakage current of the upper switch (a first configuration).

In the switching regulator of the first configuration described above, the upper switch may be a MOSFET (a second configuration).

In the switching regulator of the first or second configuration described above, the current extractor may be configured, during a period in which the controller is performing switching control, not to extract the constant current from the first terminal or the second terminal of the inductor (a third configuration).

In the switching regulator of any one of the first to the third configurations described above, the current extractor may include a transistor which is always in an off state and a constant current generator configured to generate the constant current which is substantially proportional to the leakage current of the transistor, and the leakage current of the transistor may be substantially proportional to the leakage current of the upper switch (a fourth configuration).

In the switching regulator of the fourth configuration described above, the leakage current of the transistor may be smaller than the leakage current of the upper switch. (a fifth configuration).

In the switching regulator of the fourth or fifth configuration described above, the constant current generator may be configured, during a period in which the controller is performing switching control, not to generate the constant current (a sixth configuration).

In the switching regulator of the sixth configuration described above, it may be configured that no leakage current of the transistor is supplied to the constant current generator during a period in which the controller is performing switching control (a seventh configuration).

A semiconductor integrated circuit disclosed herein forms at least a part of the switching regulator of any one of the first to the seventh configurations described above and has the upper switch and the current extractor (an eighth configuration).

The semiconductor integrated circuit of the eights configuration described above may further comprise a voltage divider circuit configured to divide the output voltage. In the semiconductor integrated circuit of the eights configuration described above, the current extractor may extract the constant current from the second terminal of the inductor externally fitted to the semiconductor integrated circuit (a ninth configuration).

An electronic appliance disclosed herein comprises the switching regulator according to any one of the first to the seventh configuration described above (a tenth configuration).

Advantageous Effects of the Invention

With a switching regulator, a semiconductor integrated circuit, and an electronic appliance which are disclosed herein, it is possible to prevent the output voltage from increasing while suppressing lowering of efficiency at low temperature during a period in which the switching regulator is not performing switching control.

FIG. 1 A diagram showing a first configuration example of a switching regulator.

FIG. 2 A top view of an example of arrangement of electrodes in an upper transistor and a transistor that is always in an off state.

FIG. 3 A diagram showing the leakage current of an upper transistor and a lower transistor.

FIG. 4 A time chart of a switch voltage in the first configuration example.

FIG. 5 A time chart of a switch voltage in a comparison example.

FIG. 6 A diagram showing a second configuration example of the switching regulator.

FIG. 7 A diagram showing a third configuration example of the switching regulator.

FIG. 8 A diagram showing a fourth configuration example of the switching regulator.

FIG. 9 A diagram showing a fifth configuration example of the switching regulator.

FIG. 10 An exterior view of a display device provided in a vehicle-mounted navigation device.

FIG. 11 An exterior view of a personal computer.

A First Configuration Example

FIG. 1 is a diagram showing a first configuration example of a switching regulator. The switching regulator of this configuration example includes a semiconductor integrated circuit 101 , an inductor L 1 , an output capacitor C 1 , and voltage division resistors R 1 and R 2 .

The semiconductor integrated circuit 101 includes a driver 1 , a reference voltage source 2 , an error amplifier 3 , a slope circuit 4 , comparators 5 and 7 , an oscillator 6 , an upper transistor Q 1 , a lower transistor Q 2 , transistors Q 3 to Q 5 , and terminals T 1 to T 4 . The upper transistor Q 1 and the transistor Q 3 are P channel MOSFETs (metal oxide semiconductor field-effect transistors). The lower transistor Q 2 , the transistor Q 4 , and the transistor Q 5 are N channel MOSFETs.

In accordance with a set signal SET, a reset signal RESET, and a reverse current sense signal Zc, the driver 1 generates a gate signal G 1 for the upper MOS transistor Q 1 and a gate signal G 2 for the lower MOS transistor Q 2 .

The upper transistor Q 1 is one example of an upper switch that switches, between conducting and cut-off states, a current path from the terminal T 1 , to which an input voltage Vin is applied, to the terminal T 2 . To the gate of the upper transistor Q 1 , the gate signal G 1 is fed from the driver 1 . The upper transistor Q 1 turns on when the gate signal G 1 is at low level, and turns off when the gate signal G 1 is at high level.

The lower transistor Q 2 is one example of a lower switch that switches, between conducting and cut-off states, the current path from the terminal T 3 , which is grounded, to the terminal T 2 . To the gate of the lower transistor Q 2 , the gate signal G 2 is fed from the driver 1 . The lower transistor Q 2 turns on when the gate signal G 2 is at high level, and turns off when the gate signal G 2 is at low level. Instead of the lower transistor Q 2 , a diode can be used as a lower switch.

The upper transistor Q 1 and the lower transistor Q 2 turn on and off in a complementary manner through switching control by the driver 1 . Thus, while the driver 1 performs switching control, the switch voltage Vsw that appears at the connection node between the upper transistor Q 1 and the lower transistor Q 2 is a pulsating voltage. When the upper transistor Q 1 and the lower transistor Q 2 switch between ON and OFF, it is preferable to provide a dead time during which both the upper transistor Q 1 and the lower transistor Q 2 are off.

The inductor L 1 and the output capacitor C 1 smooth the switch voltage Vsw to generate an output voltage Vout.

The voltage division resistors R 1 and R 2 divide the output voltage Vout to generate a feedback voltage Vfb.

The error amplifier 3 generates an error signal Verr commensurate with the difference between the feedback voltage Vfb and a reference voltage output from the reference voltage source 2 .

The slope circuit 4 , in synchronism with a clock signal of a predetermined frequency generated by the oscillator 6 , charges and discharges an unillustrated capacitor with an unillustrated constant current circuit, a resistor, and the like, and thereby generates and outputs a triangular or sawtooth slope voltage. It is also possible to configure the switching regulator as a current mode control type by reflecting information on the current passing the inductor L 1 on the slope voltage.

The comparator 5 compares the output voltage of the slope circuit 4 and the error signal Verr to generate a reset signal RESET as a comparison signal. The slope voltage generated by the slope circuit 4 has a fixed period, and thus the reset signal RESET is a PWM (pulse width modulation) signal.

The oscillator 6 generates a set signal SET as a clock signal of a predetermined frequency.

The comparator 7 compares the drain voltage and the source voltage of the lower transistor Q 2 to generate and output the reverse current sense signal Zc. If a forward current (normal current), that is, a current from the terminal T 3 to the terminal T 2 , passes through the lower transistor Q 2 , the reverse current sense signal Zc turns to low level. On the other hand, if a reverse current, that is, a current from the terminal T 2 to the terminal T 3 , passes through the lower transistor Q 2 , the reverse current sense signal Zc turns to high level. It is also possible to modify the interconnection between the comparator 7 and the lower transistor Q 2 such that the reverse current sense signal Zc has the opposite polarity to that in this configuration example.

The driver 1 , under a heavy load, performs switching control. Specifically, under a heavy load, when the set signal SET switches from low level to high level, the driver 1 switches the gate signal G 1 from high level to low level, and when the reset signal RESET switches from low level to high level, the driver 1 switches the gate signal G 1 from low level to high level.

On the other hand, the driver 1 , under a light load (except immediately after the output voltage Vout has become lower than a predetermined value), stops switching control. Specifically, the driver 1 , under a light load (except immediately after the output voltage Vout has become lower than the predetermined value), fixes the gate signal G 1 at high level and the gate signal G 2 at low level. With this, under a light load (except immediately after the output voltage Vout has become lower than the predetermined value), the upper transistor Q 1 and the lower transistor Q 2 are held in an off state. When the reverse current sense signal Zc switches from low level to high level, the driver 1 judges that the load has switched from a heavy load to a light load.

If the driver 1 , while not performing switching control, judges that the output voltage Vout has become smaller than the predetermined value, it restarts switching control. Specifically, the driver 1 , while not performing switching control, monitors whether the period from the time point when the set signal SET switches from low level to high level to the time point when the reset signal RESET switches from low level to high level is longer than or equal to a threshold value. If the period is longer than or equal to the threshold value, the driver 1 judges that the output voltage Vout has become smaller than the predetermined value. After switching control is restarted, if the load is light, the driver 1 stops switching control again, and if the load is heavy, the driver 1 continues switching control.

Stopping switching control eliminates switching loss, and thus the switching regulator of this configuration example which operates as described above offers high efficiency under a light load.

A current extractor formed by the transistors Q 3 to Q 5 is a circuit provided to prevent the output voltage from increasing while suppressing lowering of efficiency at low temperature during a period in which the driver 1 is not performing switching control.

The transistor Q 3 is a P channel MOSFET. The gate and the source of the transistor Q 3 are connected to the terminal T 1 . Thus the transistor Q 3 is always in an off state and lets only a leakage current pass.

In this configuration example, the gate length of the transistor Q 3 and the gate length of upper transistor Q 1 are made equal so that the leakage current (subthreshold leakage current) of the transistor Q 3 is substantially proportional to the leakage current (subthreshold leakage current) of the upper transistor Q 1 . Also, in this configuration example, the gate width of the transistor Q 3 is made smaller than the gate width of the upper transistor Q 1 so that the leakage current of the transistor Q 3 is smaller than the leakage current of the upper transistor Q 1 . In order to match the temperatures of the upper transistor Q 1 and the transistor Q 3 as well as possible, it is preferable to arrange the upper transistor Q 1 and the transistor Q 3 close to each other.

Thus, for example, gate electrodes Eg, drain electrodes Ed, and source electrodes Es of the upper transistor Q 1 and the transistor Q 3 can be arranged as shown in FIG. 2 . In the arrangement shown in FIG. 2 , the gate length of the transistor Q 3 is equal to the gate length of the upper transistor Q 1 , and the gate width of the transistor Q 3 is 1/10 of the gate width of the upper transistor Q 1 ; thus the leakage current of the transistor Q 3 is 1/10 of the leakage current of the upper transistor Q 1 .

The transistors Q 4 and Q 5 , which are N channel MOSFETs, constitute a current mirror circuit. The current mirror circuit formed by the transistors Q 4 and Q 5 extracts from the terminal T 2 a constant current Ic that is substantially proportional to the leakage current of the transistor Q 3 . The mirror ratio of the current mirror circuit is set such that the value of the constant current Ic is larger than or equal to the value obtained by subtracting the leakage current of the lower transistor Q 2 from the leakage current of the upper transistor Q 1 . For example, when the leakage current of the transistor Q 3 is 1/10 of the leakage current of the upper transistor Q 1 , if the mirror ratio of the current mirror circuit is made 10 times as large, the value of the constant current Ic equals the leakage current of the upper transistor Q 1 , and if the mirror ratio of the current mirror circuit is made 20 times as large, the value of the constant current Ic is twice as large as the leakage current of the upper transistor Q 1 . The leakage current of the transistor Q 3 has a positive temperature characteristic, and thus the constant current Ic also has a positive temperature characteristic.

Here, miniaturizing the upper transistor Q 1 that has the larger area makes the gate length of the upper transistor Q 1 smaller, and thus, for example as shown in FIG. 3 , the leakage current I OFF _ Q1 of the upper transistor Q 1 becomes much larger than the leakage current I OFF _ Q2 of the lower transistor Q 2 . Thus, miniaturization of the upper transistor Q 1 is more likely to cause a situation where, under a light load, the charge current of the output capacitor C 1 that is generated by the leakage current of the upper transistor Q 1 becomes larger than the discharge current of the output capacitor C 1 that is generated by the leakage current of the lower transistor Q 2 and a consumption current of the load. As will be clear from FIG. 3 , the above situation is more likely to occur when the temperature is high than when the temperature is low.

However, in the switching regulator of this configuration example, there is also the discharge current of the output capacitor C 1 generated by the constant current Ic, and the value of the constant current Ic is larger than the value obtained by subtracting the leakage current of the lower transistor Q 2 from the leakage current of the upper transistor Q 1 . Thus, under a light load, the charge current of the output capacitor C 1 never becomes larger than the total discharge current of the capacitor C 1 . Thus, as shown in FIG. 4 , while the driver 1 is not performing switching control, the switch voltage Vsw does not increase. Thus, the switching regulator of this configuration example can prevent the output voltage Vout from increasing while the driver 1 is not performing switching control. Furthermore, the constant current Ic has a positive temperature characteristic and thus the constant current Ic extracted from the terminal T 2 by the current extractor at low temperature does not become excessive. Thus, the switching regulator of this configuration example can suppress lowering of efficiency at low temperature.

On the other hand, if a current extractor is not provided unlike in this configuration example, when the above situation occurs, as shown in FIG. 5 , the switch voltage Vsw increases while the driver 1 is not performing switching control. As the switch voltage Vsw increases, the output voltage Vout increases. Thus the switching control is not restarted, and, inconveniently, the output voltage Vout eventually becomes an overvoltage.

A Second Configuration Example

FIG. 6 is a diagram showing a second configuration example of a switching regulator. The switching regulator of this configuration example has a configuration where the semiconductor integrated circuit 101 in the switching regulator of the first configuration example is replaced with a semiconductor integrated circuit 102 . The semiconductor integrated circuit 102 has a configuration where a transistor Q 6 is added to the semiconductor integrated circuit 101 . For features of this configuration example similar to those of the first configuration example, no overlapping description will be repeated.

The transistor Q 6 is an N channel MOSFET. The transistor Q 6 is connected in parallel with the transistor Q 4 . The driver 1 controls the ON/OFF state of the transistor Q 6 . Specifically, the driver 1 keeps on the transistor Q 6 in a period in which switching control is performed, and keeps off the transistor Q 6 in a period in which switching control is not performed. With this, in the period in which switching control is performed, the leakage current of the transistor Q 3 is not supplied to the current mirror circuit formed by the resistors Q 4 and Q 5 , and the constant current Ic is not extracted from the terminal T 2 . This results in improved efficiency in the period in which switching control is performed compared to in the first configuration example.

A Third Configuration Example

FIG. 7 is a diagram showing a third configuration example of a switching regulator. The switching regulator of this configuration example has a configuration where the semiconductor integrated circuit 102 in the switching regulator of the second configuration example is replaced with a semiconductor integrated circuit 103 . The semiconductor integrated circuit 103 has a configuration where a transistor Q 7 is added to the semiconductor integrated circuit 102 . For features of this configuration example similar to those of the second configuration example, no overlapping description will be repeated.

The transistor Q 7 is a P channel MOSFET. The transistor Q 7 is provided between the transistor Q 3 and the transistors Q 4 and Q 6 . The transistor Q 7 is given such a structure that its leakage current is smaller than that of the transistor Q 3 .

The driver 1 controls ON and OFF of the transistor Q 7 . Specifically, the driver 1 keeps off the transistor Q 7 in a period in which switching control is performed, and keeps on the transistor Q 7 in a period in which switching control is not performed. With this, the current that passes through the transistor Q 6 in the period in which switching control is performed can be made smaller than that in the first configuration example. This results in improved efficiency in the period in which switching control is performed compared to in the second configuration example.

A Fourth Configuration Example

FIG. 8 is a diagram showing a fourth configuration example of a switching regulator. The switching regulator of this configuration example has a configuration where the semiconductor integrated circuit 101 in the switching regulator of the first configuration example is replaced with a semiconductor integrated circuit 104 and an output voltage Vout is applied to a terminal T 5 , which will be described later, of the semiconductor integrated circuit 104 . The semiconductor integrated circuit 104 has a configuration where the terminal T 5 is added to the semiconductor integrated circuit 101 and the connection destination of the drain of the transistor Q 5 is changed from the terminal T 2 to the terminal T 5 . For features of this configuration example similar to those of the first configuration example, no overlapping description will be repeated.

In the switching regulator of this configuration example, unlike in the switching regulator of the first configuration example, the current mirror circuit constituted by the transistors Q 4 and Q 5 extracts the constant current Ic from the terminal T 5 instead of from the terminal T 2 . The switching regulator of this configuration example provides a similar effect to the switching regulator of the first configuration example. The switching regulator of this configuration example has a larger number of terminals in the semiconductor integrated circuit than the switching regulator of the first configuration example.

A Fifth Configuration Example

FIG. 9 is a diagram showing a fifth configuration example of a switching regulator. The switching regulator of this configuration example has a configuration where the semiconductor integrated circuit 104 in the switching regulator of the fourth configuration example is replaced with a semiconductor integrated circuit 105 and the voltage division resistors R 1 and R 2 are incorporated in the semiconductor integrated circuit 105 . The semiconductor integrated circuit 105 has a configuration where the voltage division resistors R 1 and R 2 are added to and the terminal T 4 is removed from the semiconductor integrated circuit 104 . For features of this configuration example similar to those of the fourth configuration example, no overlapping description will be repeated.

In this configuration example, the voltage division resistors R 1 and R 2 are incorporated in the semiconductor integrated circuit 105 , and thus the voltage dividing ratio of the voltage divider circuit formed by the voltage division resistors R 1 and R 2 is specific to the semiconductor integrated circuit 105 . The switching regulator of this configuration example provides a similar effect to the switching regulator of the fourth configuration example. In the switching regulator of this configuration example, unlike in the switching regulator of the fourth configuration example, the number of the terminals in the semiconductor integrated circuit can be made equal to that in the switching regulator of the first configuration example.

Examples of Application of the Switching Regulator

The switching regulator described above can be used, for example, as a power supply device for supplying a supply voltage to a CPU (unillustrated) in a vehicle-mounted navigation device X 1 . The vehicle-mounted navigation device X 1 includes a display device that displays navigation information. A display panel X 11 of the display device is provided in a front part of the cabin in a vehicle (see FIG. 10 ).

The switching regulator described above can also be used, for example, as a power supply device for supplying a supply voltage to a CPU (unillustrated) in a personal computer X 2 as shown in FIG. 11 .

<Points to Note>

The various technical features disclosed herein can be implemented in any other manner than in the embodiments described above and allow for many modifications and variations within the spirit of their technical ingenuity.

For example, in the above embodiments, a P channel MOSFET is used as an upper switch. Instead, any other switch that has a leakage current with a positive temperature characteristic may be used as an upper switch.

For another example, unlike in the above embodiments, it is also possible to use, instead of the transistor Q 3 , a constant voltage source that generates a constant voltage with a substantially zero temperature characteristic and a resistor that is connected to the constant current source and that has a negative temperature characteristic.

In the above embodiments, based on the reverse current sense signal Zc, it is judged that the load has switched from a heavy load to a light load. Instead, any other judging method may be used. For example, the current passing through the inductor L 1 may be monitored so that, when the average value of the current passing through the inductor L 1 has become lower than a predetermined value, it can be judged that the load has switched from a heavy load to a light load.

In the above embodiments, based on the set signal SET and the reset signal RESET, it is judged that the output voltage Vout has become smaller than a predetermined value. Instead, any other judging method may be used. For example, a comparator that compares the feedback voltage Vfb with the constant voltage may be provided so that it is possible to judge from the output of the comparator that the output voltage Vout has become smaller than a predetermined value.

It is possible to apply to the fourth configuration example modifications similar to those from the first configuration example to the second configuration example, and it is also possible to apply to the fifth configuration example modifications similar to those from the first configuration example to the second configuration example.

The above embodiments should be understood to be in every aspect illustrative and not restrictive. The scope of the present invention is defined not by the description of the embodiments given above but by the appended claims, and should be understood to encompass any modifications made in the sense and scope equivalent to those of the claims.

This invention finds application in switching regulators used in any fields (in the fields of electrical appliances, automobiles, industrial machinery, and so on).

1 driver

2 reference voltage source

3 error amplifier

4 slope circuit

5 , 7 comparator

6 oscillator

101 - 105 semiconductor integrated circuit

C 1 output capacitor

Eg gate electrode

Ed drain electrode

Es source electrode

L 1 inductor

R 1 , R 2 voltage division resistor

Q 1 upper transistor

Q 2 lower transistor

Q 3 -Q 7 transistor

T 1 -T 5 terminal

X 1 vehicle-mounted navigation device

X 11 display panel

X 2 personal computer