Power source circuit

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-172185, filed on Sep. 14, 2018; the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a power source circuit.

For a power source circuit that outputs a bandgap reference voltage, a configuration that includes a circuit that outputs a signal that indicates that the bandgap reference voltage is output has conventionally been known. A bandgap reference voltage is used as a reference voltage of a series regulator, a DC/DC converter, or the like. In a case where a signal is output that indicates that a bandgap reference voltage is output even though it is not provided in a desired state, a circuit that receives a voltage from a power source circuit to operate is caused to operate erroneously. Hence, it is desired that a signal that indicates being output is a signal that accurately reflects a state of a bandgap reference voltage that is output by a power source circuit.

FIG. 1 is an explanatory diagram that illustrates a power source circuit according to a first embodiment.

FIG. 2 is a diagram that illustrates a result of simulation of a power source circuit according to the first embodiment.

FIG. 3 is a diagram that illustrates a result of simulation where a temperature characteristic in the first embodiment is compared with a conventional power source circuit.

FIG. 4 is a diagram that illustrates a conventional power source circuit that is used for comparison.

FIG. 5 is a diagram that illustrates a power source circuit according to a second embodiment.

FIG. 6 is a diagram that illustrates a power source circuit according to a third embodiment.

According to one embodiment, a power source circuit has a first conductivity-type first bipolar transistor that has an emitter, a base, and a collector. The power source circuit has a first conductivity-type second bipolar transistor that has an emitter that has an emitter area that is different from an emitter area of the first bipolar transistor and is commonly connected to the emitter of the first bipolar transistor. The power source circuit has a first conductivity-type third bipolar transistor that has an emitter that has an emitter area that is different from the emitter area of the first bipolar transistor and is commonly connected to the emitter of the first bipolar transistor. The power source circuit has an output voltage setting circuit that has a first resistor that is connected between the base of the first bipolar transistor and a base of the second bipolar transistor and a second resistor that is connected between the base of the second bipolar transistor and a base of the third bipolar transistor. The power source circuit has a PN-junction diode that is connected in a forward direction between the base of the first bipolar transistor and a power source terminal. The power source circuit has a reference voltage output terminal that is connected to the output voltage setting circuit and outputs a reference voltage that is set by a voltage that is a sum of a forward voltage of the PN-junction diode and a voltage that is a predetermined times a voltage drop that is caused at the first resistor. The power source circuit has a detection signal output circuit that outputs a detection signal that indicates that the reference voltage reaches a predetermined threshold voltage in response to a potential at a collector of the third bipolar transistor.

Exemplary embodiments of power source circuit will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.

First Embodiment

FIG. 1 is a diagram that illustrates a configuration of a power source circuit according to a first embodiment. A power source circuit according to the present embodiment has three NPN bipolar transistors G 1 to Q 3 where emitters thereof are commonly connected. Emitters of the transistors Q 1 to Q 3 are connected to a ground terminal 17 via a current source 15 . A ground potential GND is applied to the ground terminal 17 .

For example, a ratio of emitter areas of the transistors Q 2 , Q 3 to that of the transistor Q 1 is set at 1:N (where N is an arbitrary positive number that is greater than or equal to 1). That is, the transistors Q 2 and Q 3 have emitters with identical areas and an emitter area of the transistor Q 1 has an emitter area that is N times those of the transistors Q 2 and Q 3 . It is possible to set an emitter area by, for example, the number of (non-illustrated) transistors that are connected in parallel and compose each of the transistors Q 1 to Q 3 . For example, the number of transistors that compose the transistor Q 1 is N times the number of transistors that compose the transistors Q 2 and Q 3 , so that it is possible to cause a ratio of emitter areas to be N: 1 .

A series circuit of a resistor R 3 and an NPN bipolar transistor Q 4 is connected between a base of the transistor Q 1 and the ground terminal 17 . The transistor Q 4 is provided with a base and a collector that are commonly connected to compose a PN-junction diode. The transistor Q 4 is connected between a base of the transistor Q 1 and the ground terminal 17 in a direction where a forward voltage is generated therein.

An input voltage VIN is applied to a power source terminal 11 by a power source 10 . A current mirror circuit 12 is connected between collectors of the transistors Q 1 to Q 3 and the power source terminal 11 . The current mirror circuit 12 has PMOS transistors M 1 to M 3 . The transistor M 1 is provided with a drain that is connected to a collector of the transistor Q 1 and a source that is connected to the power source terminal 11 . That is, a source-drain path that is a main current path of the transistor M 1 is connected between the power source terminal 11 and the collector of the transistor Q 1 .

The transistors M 2 , M 3 are provided with gates that are commonly connected to a gate of the transistor M 1 . Furthermore, sources of the transistors M 2 , M 3 are connected to the power source terminal 11 and drains thereof are connected to collectors of the transistors Q 2 , Q 3 , respectively.

Gates of the transistors M 1 to M 3 are commonly connected and respective sources are connected to the power source terminal 11 , so that gate-source voltages VGS of the transistors M 1 to M 3 are of identical values. Hence, the current mirror circuit 12 is configured to supply a drain current dependent on a dimension ratio of the transistors M 1 to M 3 to collectors of the transistors Q 1 to Q 3 . In the present embodiment, dimensions of the collectors of the transistors Q 2 , Q 3 are set so as to be identical, so that drain currents with identical values are supplied to collectors of the transistors Q 1 to Q 3 .

It has an NMOS transistor M 4 with a gate that is connected to a collector of the transistor Q 2 , a drain that is connected to the power supply terminal 11 , and a source that is connected to a reference voltage output terminal 13 . That is, a source-drain path that is a main current path of the transistor M 4 is connected between the power source terminal 11 and the reference voltage output terminal 13 .

An output voltage setting circuit 20 is connected between a source of the transistor M 4 and a base of the transistor Q 1 . The output voltage setting circuit 20 has a resistor R 41 and a resistor R 42 that are connected in series. The resistor R 41 is connected between a base of the transistor Q 1 and a base of the transistor Q 2 . The resistor R 42 is connected between a base of the transistor Q 3 and a base of the transistor Q 4 . Furthermore, one terminal of the resistor R 42 is connected to the reference voltage output terminal 13 via the resistors R 2 and R 1 .

The present embodiment has a detection signal output circuit 40 . The detection signal output circuit 40 has a transistor M 6 with a gate that is connected to a collector of the transistor Q 4 , a source that is connected to the power source terminal 11 , and a drain that is connected to a current source 16 . Conduction of the transistor M 6 is controlled by a collector potential of the transistor Q 3 . Furthermore, the detection signal output circuit 40 has an NMOS transistor M 5 with a source that is connected to the ground terminal 17 , a gate that is connected to a drain of the transistor M 6 , and a drain that is connected to the power source terminal 11 via a resistor R 5 and connected to a detection signal output terminal 14 .

A differential voltage ΔVbe between base-emitter voltages of the transistors Q 1 and Q 2 is applied to the resistor R 41 . In a state where transistors Q 1 and Q 2 are turned on completely and stabilized, a differential voltage ΔVbe is expressed by the following formula (1).

Δ Vbe=k×T/q ×ln N [ V ]  (1)

In formula (1), k is a Boltzmann constant (1.3807×10 −23 [JK −1 ]), T is an absolute temperature [K], q is a charge of an electron (1.602177×10 −19 [C]), ln is a natural logarithm, and N is a ratio of emitter areas of the transistors Q 1 and Q 2 .

For example, if a ratio of emitter areas N is “8”, ΔVbe in formula (1) is about 54 mV at an ordinary temperature. In such a case, in a state where a voltage drop at the resistor R 41 is less than such a differential voltage ΔVbe, the transistor Q 2 is not provided in a complete on-state. Hence, a drain potential of the transistor M 2 , that is, a gate potential of the transistor M 4 rises with an input voltage VIN.

The transistor M 4 is turned on as a gate potential exceeds a threshold voltage. Thereby, the output voltage setting circuit 20 is connected to the power source terminal 11 via the transistor M 4 . A voltage at the reference voltage output terminal 13 that is connected to the output voltage setting circuit 20 rises with a rise in a drain voltage of the transistor M 4 .

As a voltage drop at the resistor R 41 reaches a differential voltage ΔVbe as expressed in formula (1) with a rise in an input voltage VIN, the transistor Q 2 is provided in a complete on-state. That is, stabilization is provided in a state where a differential voltage ΔVbe that is set by a ratio of emitter areas N of the transistors Q 1 and Q 2 is generated at the resistor R 41 .

At a time of a state where a voltage drop at the resistor R 41 is stabilized by a differential voltage ΔVbe, a bandgap output voltage VBG at the reference voltage output terminal 13 is expressed by the following formula (2).

Herein, Vbe(Q 4 ) represents a forward voltage of the transistor Q 4 . Additionally, R 1 , R 2 , R 3 , R 41 , and R 42 in formula (2) conveniently represent resistance values of the corresponding resistors R 1 , R 2 , R 3 , R 41 , and R 42 , respectively. Hereinafter, a similar matter applies to each mathematical formula.

A current that is obtained by dividing a voltage drop that corresponds to a differential voltage ΔVbe by a resistance value of the resistor R 41 flows through the output voltage setting circuit 20 to cause voltage drops at the respective resistors R 1 , R 2 , R 3 , R 41 , and R 42 .

Therefore, in the present embodiment, as expressed in formula (2), a bandgap output voltage VBG is set by a sum of a forward voltage Vbe(Q 4 ) of the transistor Q 4 and a voltage that is predetermined times a differential voltage ΔVbe as expressed in formula (1) depending on resistance values of respective resistors of the output voltage setting circuit 20 and the resistor R 3 .

Furthermore, a temperature coefficient of a bandgap output voltage VBG is expressed by the following formula (3).

A temperature coefficient ∂Vbe(Q 4 )/∂T of Vbe(Q 4 ) indicates a negative temperature characteristic and is, for example, −1.8 m(V/° C.). Therefore, a value of a second term of formula (3) is adjusted so that it is possible to cause a temperature coefficient of a bandgap output voltage VBG to be 0 (V/° C.).

A value of a second term of formula (2) is a voltage that has a value that is equal to a voltage Vbe(Q 4 ) and a positive temperature coefficient, so that a temperature coefficient of a bandgap output voltage VBG is 0 (V/° C.). For example, Vbe(Q 4 ) is generally about 0.6 V, so that it is possible to configure a power source circuit that outputs a bandgap output voltage VBG with a voltage that is twice Vbe(Q 4 ) or about 1.25 V and a temperature coefficient that is 0 (V/° C.) as a bandgap output voltage VBG.

Serial connection of the resistors R 41 and R 42 is connected between bases of the transistors Q 1 and Q 3 . Therefore, in a state where a voltage that is a sum of voltage drops at the resistors R 41 and R 42 is lower than a voltage of formula (1) as described above, the transistor Q 3 is not provided in a complete on-state. Therefore, a collector potential of the transistor Q 3 , that is, a gate potential of the transistor M 6 is provided in a high state, so that the transistor M 6 is provided in an off-state.

As a voltage that is a sum of voltage drops at the resistors R 41 and R 42 reaches a differential voltage ΔVbe as expressed in figure ( 1 ), the transistor Q 3 is provided in a complete on-state and a gate potential of the transistor M 6 is lowered. Thereby, the transistor M 6 is turned on.

As the transistor M 6 is turned on, a gate potential of the transistor M 5 is raised to be turned on. Thereby, an input of an inverter IN 1 is provided at an L level and a detection signal BG_OK at an H level is output from the detection signal output terminal 14 .

A detection threshold voltage Vs(BG_OK) of the reference voltage output terminal 13 at a time when a voltage that is a sum of voltage drops at the resistors R 41 and R 42 reaches a differential voltage ΔVbe as expressed in figure ( 1 ) is expressed by the following formula (4). Hereinafter, Vs(BG_OK) will be referred to as a detection threshold voltage.

Formula (3) and formula (4) are different only in a denominator of a fraction part of a resistor in a second term. Therefore, it is possible to set a setting ratio of a detection threshold voltage Vs(BG_OK) arbitrarily by values of the resistor R 41 and the resistor R 42 . For example, R 42 =R 41 ×0.125 is provided, so that it is possible to set a detection threshold voltage Vs(BG_OK) at about 1.18 (V). That is, at a time when a voltage at the reference voltage output terminal 13 reaches a voltage that is 94.4% of about 1.25 V that is a set bandgap voltage, a detection signal BG_OK at an H level is output. Therefore, it is possible to provide a power source circuit that accurately reflects a state of a bandgap output voltage VBG to be output and outputs a detection signal BG_OK.

Furthermore, it is possible to cause a temperature coefficient of a detection threshold voltage Vs(BG_OK) to be a value that is substantially identical to that of a temperature coefficient of a bandgap output voltage VBG, by adjustment of resistance values of the resistors R 41 and R 42 . Therefore, a temperature coefficient of a bandgap output voltage VBG is set at about 0 (V/° C.), so that it is possible to cause a temperature coefficient of a detection threshold voltage Vs(BG_OK) to be also about 0 (V/° C.).

Therefore, according to the present embodiment, it is possible to output a bandgap output voltage VBG with a temperature coefficient of about 0 (V/° C.) and it is possible to cause a temperature coefficient of a detection threshold voltage Vs(BG_OK) to be also about 0 (V/° C.). Hence, it is possible to provide a power source circuit that outputs a detection signal BG_OK that accurately reflects a state of a bandgap output voltage VBG and is stable against a temperature change.

FIG. 2 is a diagram that illustrates a result of simulation of a power source circuit according to the first embodiment. A horizontal axis indicates a time (S) and a vertical axis indicates a voltage (V). A bandgap output voltage VBG and a detection signal BG_OK in a case where an input voltage VIN is raised from 0 V to 5 V and lowered to 0 V again at a temperature within a range of −50° C. to 175° C. are illustrated. At a time when a bandgap output voltage VBG ( 32 ) reaches a detection threshold voltage Vs(BG_OK) as represented by 33 with a rise in an input voltage VIN as represented by 30 - 1 , a detection signal BG_OK ( 31 - 1 ) is changed to an H level. A temperature coefficient of a detection threshold voltage Vs(BG_OK) is set at about 0 (V/° C.), so that a variation in a temperature change at a rise where a detection signal BG_OK is at an H level is small as represented by 40 _ 1 . Additionally, the inverter IN 1 is biased by an input voltage VIN, so that a voltage of a detection signal BG_OK at an H level rises with a rise in the input voltage VIN.

A bandgap output voltage VBG is stable in a state where a voltage drop at the resistor R 41 is a differential voltage ΔVbe, that is, about 54 mV, and indicates a stable value of voltage against a temperature change.

In a case where an input voltage VIN is lowered from 5 V to 0 V as indicated by a broken line 30 _ 2 , a voltage of a detection signal BG_OK at an H level as indicated by a solid line 31 _ 2 is lowered. As a sum of voltage drops at the resistors R 41 and R 42 is less than a differential voltage ΔVbe, the transistor Q 3 is provided in an off-state and the transistor M 6 is turned off, so that a detection signal BG_OK is provided at an L level. Even in a case where an input voltage VIN is lowered, a variation in a temperature change at a fall of a detection signal BG_OK is suppressed as represented by 40 _ 2 .

FIG. 3 illustrates a temperature change of a detection threshold voltage Vs(BG_OK) in the first embodiment as comparison with a conventional power source circuit as illustrated in FIG. 4 . A conventional power source circuit has transistors Q 1 , Q 2 where emitters thereof are commonly connected, and a current mirror circuit 120 . One terminal of a resistor R 4 of an output voltage setting circuit 200 is connected to a base of the transistor Q 1 and the other terminal thereof is connected to a base of the transistor Q 2 . The output voltage setting circuit 200 includes a transistor M 5 with a gate that is connected to a connection point of resistors R 1 and R 2 . The transistor M 5 is turned on at a time when a gate potential reaches a threshold voltage, for example, 0.6V, so that a detection signal BG_OK at an H level is output from a detection signal output terminal 14 .

In FIG. 3 , a solid line 50 indicates a power source circuit according to the first embodiment and a broken line 51 indicates a conventional power source circuit as illustrated in FIG. 4 . In the first embodiment, it is possible to set a temperature coefficient of a detection threshold voltage Vs(BG_OK) at about 0 (V/° C.) similarly to that of a bandgap output voltage VBG. Therefore, a power source circuit according to the first embodiment indicates a value of a detection threshold voltage that is stable against a temperature change as compared with a conventional power source circuit.

Second Embodiment

FIG. 5 is a diagram that illustrates a power source circuit according to a second embodiment. An identical sign is provided to a component that corresponds to that of the first embodiment and a redundant description is executed only in a case of need. Hereinafter, a similar matter applies. A power source circuit according to the present embodiment has a current mirror circuit 12 that is composed of PNP transistors Q 121 , Q 122 , Q 123 .

The present embodiment has an NPN transistor Q 14 . That is, an emitter-collector path that is a main current path of the transistor Q 14 is connected between a power source terminal 11 and a reference voltage output terminal 13 . As a collector potential of a transistor Q 2 is higher than a threshold voltage of the transistor Q 14 , the transistor Q 14 is turned on. Thereby, an output voltage setting circuit 20 is connected to the power source terminal 11 via the transistor Q 14 , and a bandgap output voltage VBG of the reference voltage output terminal 13 rises with a rise in an emitter voltage of the transistor Q 14 .

A detection signal output circuit 40 according to the present embodiment has a PNP transistor Q 16 . The transistor Q 16 is provided with a base that is connected to a collector of a transistor Q 3 , an emitter that is connected to the power source terminal 11 , and a collector that is connected to a current source 16 .

Furthermore, the detection signal output circuit 40 has an NPN transistor Q 15 . The transistor Q 15 is provided with an emitter that is connected to a ground terminal 17 and a collector that is connected to the power source terminal 11 via a resistor R 5 and a detection signal output terminal 14 .

As a sum of voltage drops at resistors R 41 and R 42 reaches a differential voltage ΔVbe as expressed by formula (1) similarly to that of the first embodiment, the transistor Q 3 is provided in a complete on-state and a base potential of the transistor Q 16 is lowered to be turned on.

As the transistor Q 16 is turned on, a base potential of the transistor Q 15 is raised to be turned on. Thereby, an input of an inverter IN 1 is provided at an L level, so that an output thereof is provided at an H level. Hence, a detection signal BG_OK at an H level is output from the detection signal output terminal 14 .

In a state where a voltage drop at the resistor R 41 is a differential voltage ΔVbe and transistors Q 1 and Q 2 are turned on completely and stabilized, an operation with a bandgap output voltage VBG that is set by formula (2) or an operation with a voltage of a detection threshold voltage Vs(BG_OK) that is capable of being set by formula (4) depending on values of the resistors R 41 , R 42 is identical to that of the first embodiment.

Relative errors or offsets of the transistors Q 121 , Q 122 , Q 123 are generally small as compared with those of transistors M 1 , M 2 , M 3 . Therefore, in the present embodiment, it is possible to improve accuracy of the current mirror circuit 12 , that is, accuracy of a ratio of currents that are supplied to transistors Q 1 , Q 2 , Q 4 .

Third Embodiment

FIG. 6 illustrates a power source circuit according to a third embodiment. A power source circuit according to the present embodiment has PNP transistors Q 10 , Q 20 , and Q 30 where emitters thereof are commonly connected, instead of the transistors Q 1 to Q 3 in the first embodiment. The transistor Q 10 has an emitter area that is N times those of the transistors Q 20 , Q 30 . The number of (non-illustrated) transistors that are connected in parallel and compose the transistor Q 10 is N times the number of (non-illustrated) transistors that compose each of the transistors Q 20 , Q 30 , so that it is possible to cause an emitter area of the transistor Q 10 to be N times.

Drains of NMOS transistors M 10 , M 20 , and M 30 that compose a current mirror circuit 12 are connected to collectors of the transistors Q 10 , Q 20 , and Q 30 .

An output voltage setting circuit 20 according to the present embodiment has a resistor R 41 that is connected between a base of the transistor Q 10 and a base of the transistor Q 20 and a resistor R 42 that is connected between a base of the transistor Q 20 and a base of the transistor Q 30 .

The present embodiment has a transistor M 40 with a gate that is connected to a collector of the transistor Q 20 , a source that is connected to a power source terminal 11 , and a drain that is connected to a reference voltage output terminal 13 and an output voltage setting circuit 20 .

At a time in a state where an input voltage VIN is low, a gate potential of the transistor M 40 is provided at an L level to be turned on. Thereby, a voltage drop is caused by the output voltage setting circuit 20 , so that a bandgap output voltage VBG is raised.

As a sum of voltage drops at the resistors R 41 and R 42 reaches a differential voltage ΔVbe with a rise in an input voltage VIN, the transistor Q 30 is provided in a complete on-state and a gate potential of a transistor M 6 is raised. Thereby, the transistor M 6 is turned off.

As the transistor M 6 is turned off, a gate potential of a transistor M 5 is lowered to be turned off. Thereby, an input of a buffer BUF 1 is provided at an H level, so that an output thereof is provided at an H level. Hence, a detection signal BG_OK at an H level is output from a detection signal output terminal 14 .

A detection threshold voltage Vs(BG_OK) at a time when a sum of voltage drops at the resistors R 41 and R 42 reaches a differential voltage ΔVbe is expressed by formula (4) as already described.

As a voltage drop at the resistor R 41 is a differential voltage ΔVbe with a rise in an input voltage VIN, the transistor Q 20 is provided in an on-state and a gate potential of the transistor M 40 is controlled by a negative feedback operation. Thereby, stabilization is provided in a state where collector currents of the transistors Q 10 and Q 20 , that is, drain currents of the transistors M 10 and M 20 are equal to each other. At a time of such a stabilized state, a bandgap output voltage VBG is expressed by formula (2) as already described.

In the present embodiment, the transistors Q 10 , Q 20 , and Q 30 where emitters thereof are commonly connected are included and the transistor M 40 is turned on in a state where an input voltage VIN is low, so that activation at a low voltage is possible. Furthermore, variations in base-emitter voltages Vbe of the transistors Q 10 , Q 20 , Q 30 are generally small as compared with those of the transistors Q 1 to Q 3 , so that it is possible to suppress a variation in a bandgap output voltage VBG.

Additionally, although an embodiment as already described is configured to include a current mirror circuit 12 connected to collectors of the transistors Q 1 to Q 3 or transistors Q 010 , Q 20 , Q 30 where emitters thereof are commonly connected, a configuration may be provided in such a manner that connection between respective collectors of the transistors Q 1 to Q 3 or transistors Q 10 , Q 20 , Q 30 and a power source terminal is provided by resistors, instead of the current mirror circuit 12 .

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.