Sense amplifiers for wider I/O memory device

The present invention generally relates to semiconductor devices, and more particularly to sense amplifiers for wider I/O memory devices.

In the context of computer memory, sense amplifiers are components of read circuitry on a memory chip used to read data from memory. Sense amplifiers are configured to sense low power signals from a bit-line representing a data bit (e.g., 1 or 0) stored in a memory cell, and amplify the small voltage to recognizable logical levels so that the data can be interpreted by logic.

In accordance an embodiment of the present invention, a sense amplifier is provided. The sense amplifier includes a first transistor having a source/drain connected to a data line, a drain/source connected to a first node and a gate connected to a setting line. The sense amplifier further includes a second transistor having a source/drain connected to ground or a power supply voltage, a drain/source connected to a second node and a gate connected to the setting line.

In accordance another embodiment of the present invention, a memory device is provided. The memory device include a memory cell allocated to a sub-array, a sense amplifier provided for the sub-array and connected to a bit-line pair, and a data line provided for the sub-array and connected to an output of the sense amplifier. The sense amplifier includes a first transistor having a source/drain connected to a data line, a drain/source connected to a first node and a gate connected to a setting line. The sense amplifier further includes a second transistor having a source/drain connected to ground or a power supply voltage, a drain/source connected to a second node and a gate connected to the setting line.

In accordance yet another embodiment of the present invention, a method for implementing a sense amplifier is provided. The method includes sensing, by a sense amplifier provided for a sub-array and connected to a bit-line pair and a data line of a memory device, a signal. The method further includes amplifying, by the sense amplifier, the sensed signal. The sense amplifier includes a first transistor having a source/drain connected to a data line, a drain/source connected to a first node and a gate connected to a setting line. The sense amplifier further includes a second transistor having a source/drain connected to ground or a power supply voltage, a drain/source connected to a second node and a gate connected to the setting line.

These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

The following description will provide details of preferred embodiments with reference to the following figures wherein:

FIG. 1 is a block diagram of a memory cell, in accordance with an embodiment of the present invention.

FIG. 2 is a block diagram of a memory device architecture, in accordance with an embodiment of the present invention;

FIG. 3 is a block diagram of a portion of a sense amplifier, in accordance with an embodiment of the present invention;

FIG. 4 is a schematic of a sense amplifier, in accordance with an embodiment of the present invention;

FIG. 5 is a schematic of a sense amplifier, in accordance with another embodiment of the present invention;

FIG. 6 is a schematic of a sense amplifier, in accordance with yet another embodiment of the present invention; and

FIG. 7 is a block/flow diagram of a system/method for implementing a sense amplifier, in accordance with an embodiment of the present invention.

One factor that can be considered in manufacturing semiconductor devices is chip size (e.g., chips per wafer). In the context of memory devices, the cell array area can be over half in memory chip. The embodiments described herein provide for sense amplifiers for wider I/O memory devices. For example, the sense amplifiers described herein can be implemented as primary sense amplifiers (PSAs) and/or secondary sense amplifiers (SSAs) in memory devices (e.g., DRAM or SRAM). The embodiments described herein can be used to minimize memory cell size for reducing cost, and maximize bandwidth to read all PSA outputs from activated sub-arrays without waste.

It is to be understood that aspects of the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps can be varied within the scope of aspects of the present invention.

It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

The present embodiments can include a design for an integrated circuit chip, which can be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer can transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.

Methods as described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher-level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

It should also be understood that material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes Si x Ge 1-x where x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.

Reference in the specification to “one embodiment” or “an embodiment”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. For example, if the device in the FIGS. is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.

It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.

With reference to FIG. 1 , a memory cell 100 is shown. In one embodiment, the memory cell 100 includes dynamic RAM (DRAM) cell. For example, the memory cell 100 can illustratively employ a DRAM memory cell design having a storage cell size of 6F 2 , where F refers to the feature of the semiconductor device manufacturing technology (e.g., 90/65/28 nm). Thus, F 2 is the square of the feature, which is a minimum unit size of the manufacturing technology. However, the memory cell 100 can include any suitable memory cell in accordance with the embodiments described herein.

The memory cell 100 includes pairs of bit-lines (BLs) and complementary bit-lines (*BLs), including a first pair having a first BL 110 a and a first *BL 110 a , and a second pair having a second BL 120 a and a second *BL 120 b . The memory cell 100 further includes word-line (WL) 130 , a first data-line (DL) 140 - 1 , a second DL 140 - 2 and power supply voltage (VDD)/ground (GND) 150 .

Generally, a lowest level metal (e.g., M 1 ) can be assigned to the BLs/*BLs, and a highest level metal (e.g., M 3 ) can be assigned to the DLs. The higher level metal pitch can be bigger as compared to the lower level metal pitch. The cell size, and thus cost of memory, can be reduced by tightening the BL/WL pitch. Therefore, the same number of BL/DL cannot be allocated, further no wires cannot be allocated for VDD/GND.

A primary sense amplifier (PSA) (not shown) can be attached to each BL pair selected by the WL 130 , which data cannot be transferred through DL pairs. Therefore, a secondary sense amplifier (SSA) (not shown) working with single-ended DL can be needed. However, this constraint doesn't occur if the memory cell 100 includes SRAM. For example, since the cell size is much larger compared to DRAM, then it can be possible to allocate enough wires. Further details regarding memory architectures including PSAs and SSAs will now be described below with reference to FIG. 2 .

With reference to FIG. 2 , a memory architecture 200 is provided. As shown, the architecture 200 includes a plurality of sub-arrays 210 - 1 through 210 - 7 . The sub-arrays 210 - 1 through 210 - 7 have respective memory cells allocated thereto. The memory architecture 200 further includes a plurality of primary sense amplifiers (PSAs)/primary write drivers (PWDs) 220 - 1 through 220 - 7 coupled to respective ones of the plurality of sub-arrays 210 - 1 through 210 - 7 , and a secondary sense amplifier (SSA)/secondary write driver (SWD) 230 . In this illustrative embodiment, the plurality of sub-arrays 210 - 1 through 210 - 7 share the SSA/SWD 230 , and once a given one of the sub-arrays 210 - 1 through 210 - 7 is activated, then the corresponding one of the PSAs 220 - 1 through 220 - 7 can have its outputs driven to the SSA 230 through the DL. Memory cells selected by WLs in each sub-array 210 - 1 through 210 - 7 are read out.

In memory architectures like DRAM or SRAM, a read operation can be carried out by selecting 1 WL from 512×9 row addresses and 64 BL pairs from 2k×5 column addresses, and connecting the 64 BL pairs to 64 DL pairs via the PSA in the activated sub-array (e.g., 512 WL*2k BL). Generally, a portion of the data (e.g., 1/32 of the data) is transferred by column selection while the remaining data (e.g., 31/32 of the data) is wasted. Since there are total 2k BL pairs/PSAs, 2k data can be read simultaneously if the SSA 230 is working with a single-ended DL, which maximizes bandwidth and eliminates wasting data and power.

Examples of sense amplifiers that can implement the PSA and/or SSA of the memory architecture shown above in FIG. 2 will now be described with reference to FIGS. 3-6 .

With reference to FIG. 3 , a block diagram is provided illustrating a portion 302 of a sense amplifier 300 including a first transistor (T 1 ) 310 , a second transistor (T 2 ) 320 and a cross-coupled inverter 330 .

T 1 310 can be connected to a data line (DL) 340 , a first node (N 1 ) 350 - 1 and a setting line (SL) 360 . For example, a source/drain of T 1 310 can be connected to DL 350 , a drain/source of T 1 310 can be connected to N 1 350 - 1 , and a gate of T 1 310 can be connected to SL 360 . Further details regarding T 1 310 will be described below with reference to FIGS. 4-7 .

T 2 320 can be connected to ground (GND) or power supply voltage (PS) 370 , a second node (N 2 ) 350 - 2 and SL 360 . For example, a source/drain of T 2 320 can be connected to GND/PS 370 , a drain/source of T 2 320 can be connected to N 2 350 - 2 and a gate of T 2 320 can be connected to SL 360 . Further details regarding T 2 320 will be described below with reference to FIGS. 4-7 .

Cross-coupled inverter 330 , which can include four transistors (not shown), can be connected to N 1 350 - 1 , N 2 350 - 2 and PS/GND 380 . For example, if T 2 320 is connected to GND, then cross-coupled inverter 330 can be connected to PS. As another example, if T 2 320 is connected to PS, then cross-coupled inverter 330 can be connected to GND. Further details regarding cross-coupled inverter 330 will be described below with reference to FIGS. 4-7 .

FIG. 3 depicts an overview of a portion 302 of a sense amplifier 300 . Additional components that are not shown in FIG. 3 , such as, e.g., other transistors and nodes, can be included within the sense amplifier 300 . For example, in some embodiments, the sense amplifier 300 can include nine transistors. In other embodiments, the sense amplifier 300 can include ten transistors. Exemplary sense amplifiers will now be described in further detail below with reference to FIGS. 4-7 .

With reference to FIG. 4 , a schematic of a sense amplifier 400 is provided in accordance with an embodiment of the present invention. Illustratively, the sense amplifier 400 can be implemented in a memory device. For example, the sense amplifier 400 can be implemented in, e.g., DRAM.

As shown, the sense amplifier 400 can include nine transistors T 1 -T 9 . In one embodiment, T 1 -T 9 include field-effect transistors (FETs). In this illustrative example, T 1 , T 2 , T 5 and T 6 can include n-type FETs (NFETs), while T 3 , T 4 and T 7 -T 9 can include p-type FETs (PFETs). As will be described below with reference to FIG. 5 , in an alternative embodiment, T 1 , T 2 , T 5 and T 6 can include PFETs, while T 3 , T 4 and T 7 -T 9 can include NFETs.

As further shown, T 1 has a source/drain connected to a data line (DL), a drain/source connected to a first node (N 1 ) and a gate connected to a setting line (/SETN), T 2 has a source/drain connected to ground (GND) (0V), a drain/source connected to a second node (N 2 ) and a gate connected to /SETN, T 3 has a source/drain connected to a power supply voltage (VDD), a drain/source connected to a first output node (V 1 ) and a gate connected to a second output node (V 2 ), T 4 has a source/drain connected to VDD, a drain/source connected to V 2 and a gate connected to V 1 , T 5 has a source/drain connected to N 1 , a drain/source connected to V 1 and a gate connected to V 2 , T 6 has a source/drain connected to N 2 , a drain/source connected to V 2 and a gate connected to V 1 , T 7 has a source/drain connected to VDD, a drain/source connected to V 1 and a gate connected to /SETN, T 8 has a source/drain connected to VDD, a drain/source connected to V 2 and a gate connected to /SETN, and T 9 has a source/drain connected to N 1 , a drain/source connected to N 2 and a gate connected to /SETN.

The DL can be driven 0V at low and 0.2 V at high. The T 1 current can be made larger when DL is low (0V) since N 1 /N 2 are at VDD (e.g., 1.2V). The nodes N 1 /N 2 are at NMOS threshold voltage (Vth) initially and the T 1 /T 2 drain/source voltage (Vds) are the same and are used to make the T 1 current larger when DL is high (0.2V) since the T 1 Vds is lower to the T 2 Vds, thereby generating the voltage difference between the nodes N 1 and N 2 . The voltage difference between N 1 and N 2 is sensed and amplified by cross-coupled inverters formed by T 3 /T 4 /T 5 /T 6 . Thus, fully railed voltages can be achieved at the output nodes V 1 and V 2 . /SETN is active high and activates the sense amplifier 400 . When it is inactive, /SETN is low and thus T 7 /T 8 are turned on, V 1 /V 2 are set to 1.2V, N 1 /N 2 go to NMOS threshold voltage (Vth) and T 9 shorts N 1 /N 2 .

With reference to FIG. 5 , a schematic of a sense amplifier 500 is provided in accordance with another embodiment of the present invention. Illustratively, the sense amplifier 500 can be implemented in a memory device. For example, the sense amplifier 500 can be implemented in, e.g., DRAM.

As shown, the sense amplifier 500 can include nine transistors T 1 -T 9 . In one embodiment, T 1 -T 9 include field-effect transistors (FETs). In this illustrative example, T 1 , T 2 , T 5 and T 6 can include p-type FETs (PFETs), while T 3 , T 4 and T 7 -T 9 can include n-type FETs (NFETs). As described above with reference to FIG. 4 , in an alternative embodiment, T 1 , T 2 , T 5 and T 6 can include NFETs, while T 3 , T 4 and T 7 -T 9 can include PFETs.

As further shown, T 1 has a source/drain connected to a data line (DL), a drain/source connected to a first node (N 1 ) and a gate connected to a setting line (/SETP), T 2 has a source/drain connected to a power supply voltage (VDD), a drain/source connected to a second node (N 2 ) and a gate connected to /SETP, T 3 has a source/drain connected to ground (GND), a drain/source connected to a first output node (V 1 ) and a gate connected to a second output node (V 2 ), T 4 has a source/drain connected to VDD, a drain/source connected to V 2 and a gate connected to V 1 , T 5 has a source/drain connected to N 1 , a drain/source connected to V 1 and a gate connected to V 2 , T 6 has a source/drain connected to N 2 , a drain/source connected to V 2 and a gate connected to V 1 , T 7 has a source/drain connected to GND, a drain/source connected to V 1 and a gate connected to /SETP, T 8 has a source/drain connected to GND, a drain/source connected to V 2 and a gate connected to /SETP, and T 9 has a source/drain connected to N 1 , a drain/source connected to N 2 and a gate connected to /SETP.

The DL can be driven 1V at low and 1.2 V at high. Basically, in the FIG. 5 embodiment, the NMOS/GND (0V) of the sense amplifier 400 of FIG. 4 is replaced by PMOS/VDD (1.2V). The T 1 current can be made larger when DL is low (0V) since N 1 /N 2 are at PMOS threshold voltage (Vth) initially and the T 1 /T 2 drain/source voltage (Vds) are the same and are used to make the T 1 current larger when DL is high (1.2V) since the T 1 Vds is lower to the T 2 Vds, thereby generating the voltage difference between the nodes N 1 and N 2 . The voltage difference between N 1 and N 2 is sensed and amplified by cross-coupled inverters formed by T 3 /T 4 /T 5 /T 6 . Thus, fully railed voltages can be achieved at the output nodes V 1 and V 2 . /SETP is active high and activates the sense amplifier 500 . When it is inactive, /SETP is low and thus T 7 /T 8 are turned on, V 1 /V 2 are set to 1.2V, N 1 /N 2 go to PMOS Vth, and T 9 shorts N 1 /N 2 .

The sense amplifiers 400 and 500 shown in FIGS. 4 and 5 , respectively, do not require a reference voltage (Vref) generator circuit. Additionally, the DL voltage amplitude can be ⅙ (0.2V) from ⅓ (0.4V) to VDD (1.2V).

With reference to FIG. 6 , a schematic of a sense amplifier 600 is provided in accordance with an embodiment of the present invention. Illustratively, the sense amplifier 600 can be implemented in a memory device. For example, the amplifier 600 can be implemented in, e.g., DRAM.

In contrast to the sense amplifiers described above with reference to FIGS. 4 and 5 , the sense amplifier 600 is shown including ten transistors T 1 -T 10 . In this illustrative example, T 1 , T 2 , T 5 , T 6 and T 10 can include p-type FETs (PFETs), while T 3 , T 4 and T 7 -T 9 can include n-type FETs (NFETs). However, in another embodiment, T 1 , T 2 , T 5 , T 6 and T 10 can include NFETs, while T 3 , T 4 and T 7 -T 9 can include PFETs.

As further shown, T 1 has a source/drain connected to a data line (DL), a drain/source connected to a first node (N 1 ) and a gate connected to a setting line (/SETP), T 2 has a source/drain connected to a power supply voltage (VDD), a drain/source connected to a second node (N 2 ) and a gate connected to /SETP, T 3 has a source/drain connected to ground (GND), a drain/source connected to a first output node (V 1 ) and a gate connected to a second output node (V 2 ), T 4 has a source/drain connected to VDD, a drain/source connected to V 2 and a gate connected to V 1 , T 5 has a source/drain connected to N 1 , a drain/source connected to V 1 and a gate connected to V 2 , T 6 has a source/drain connected to N 2 , a drain/source connected to V 2 and a gate connected to V 1 , T 7 has a source/drain connected to GND, a drain/source connected to V 1 and a gate connected to /SETP, T 8 has a source/drain connected to GND, a drain/source connected to V 2 and a gate connected to /SETP, T 9 has a source/drain connected to N 1 , a drain/source connected to N 2 and a gate connected to /SETP, and T 10 has a source/drain connected to VDD, a drain/source connected to N 1 and a gate connected to /SETP. Accordingly, the sense amplifier 600 shown in FIG. 6 is to similar to the sense amplifier 500 shown in FIG. 5 , with an additional transistor T 10 .

In the embodiment in which T 1 , T 2 , T 5 , T 6 and T 10 can be NFETs, while T 3 , T 4 and T 7 -T 9 can be PFETs, T 1 can have a source/drain connected to a data line (DL), a drain/source connected to a first node (N 1 ) and a gate connected to a setting line (/SETN), T 2 can have a source/drain connected to ground (GND) (0V), a drain/source connected to a second node (N 2 ) and a gate connected to /SETN, T 3 can have a source/drain connected to a power supply voltage (VDD), a drain/source connected to a first output node (V 1 ) and a gate connected to a second output node (V 2 ), T 4 can have a source/drain connected to VDD, a drain/source connected to V 2 and a gate connected to V 1 , T 5 can have a source/drain connected to N 1 , a drain/source connected to V 1 and a gate connected to V 2 , T 6 can have a source/drain connected to N 2 , a drain/source connected to V 2 and a gate connected to V 1 , T 7 can have a source/drain connected to VDD, a drain/source connected to V 1 and a gate connected to /SETN, T 8 can have a source/drain connected to VDD, a drain/source connected to V 2 and a gate connected to /SETN, T 9 can have a source/drain connected to N 1 , a drain/source connected to N 2 and a gate connected to /SETN, and T 10 can have a source/drain connected to GND, a drain/source connected to N 1 and a gate connected to /SETN. Accordingly, a sense amplifier similar to the sense amplifier 400 of FIG. 4 can be realized, with an additional transistor T 10 .

The tenth transistor T 10 can prevent floating situations resulting from the pre-charging of the DL at VDD/GND.

With reference to FIG. 7 , a block/flow diagram is provided illustrating a system/method 600 for implementing a sense amplifier. The system/method 700 can be performed to improve (e.g., maximize) bandwidth to read sense amplifier outputs, and eliminates wasting data and power.

At block 710 , a signal is sensed by a sense amplifier provided for a sub-array and connected to a bit-line pair and a data line of a memory device. The signal can be a low power signal received from the bit-line that represents a data bit (e.g., 1 or 0) stored in a memory cell. For example, the sense amplifier can be, e.g., a primary sense amplifier or a secondary sense amplifier.

The sense amplifier can include a first transistor having a source/drain connected to a data line, a drain/source connected to a first node and a gate connected to a setting line, a second transistor having a source/drain connected to ground or a power supply voltage, a drain/source connected to a second node and a gate connected to the setting line

The sense amplifier can further include a cross-coupled inverter. More specifically, the cross-coupled inverter can include a third transistor having source/drain connected to the power supply voltage or ground, a drain/source connected to a first output node and a gate connected to a second output node, a fourth transistor having a source/drain connected to the power supply voltage or ground, a drain/source connected to the second output node and a gate connected to the first output node, a fifth transistor having a source/drain connected to the first node, a drain/source connected to the first output node and a gate connected to the second output node, and a sixth transistor having a source/drain connected to the second node, a drain/source connected to the second output node and a gate connected to the first output node.

The sense amplifier can further include a seventh transistor having a source/drain connected to the power supply voltage or ground, a drain/source connected to the first output node and a gate connected to the setting line, an eighth transistor having a source/drain connected to the power supply voltage or ground, a drain/source connected to the second output node and a gate connected to the setting line, and a ninth transistor having a source/drain connected to the first node, a drain/source connected to the second node and a gate connected to the setting line.

In some embodiments, the sense amplifier can further include a tenth transistor having a source/drain connected to the power supply voltage or ground, a drain/source connected to the first node and a gate connected to the setting line.

Further details regarding the sense amplifier are described above with reference to FIGS. 1-5 .

At block 720 , the sensed signal is amplified by the sense amplifier. More specifically, the cross-coupled inverter can be configured to amplify the sensed signal. The amplification can be performed so that the signal can be interpreted by logic outside of the memory.

Having described preferred embodiments of sense amplifiers for wider I/O memory devices (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.