Isolated synchronous rectifying DC/DC converter

The present application claims priority under 35 U.S.C. § 119 to Japanese Patent Application No. 2018-005620, filed on Jan. 17, 2018, the entire contents of which are incorporated herein by reference.

The present disclosure relates to an isolated synchronous rectifying DC/DC converter.

An isolated synchronous rectifying DC/DC converter is utilized for various power source circuits including an AC/DC converter. As a kind of isolated synchronous rectifying DC/DC converter, an LLC converter is used.

FIG. 5 is a circuit diagram illustrating an example of a partial configuration of a secondary side of an LLC converter. A secondary winding W 200 illustrated in FIG. 5 is included in a transformer Tr. A primary side (not shown) of the LLC converter includes a primary winding of the transformer Tr, a switching transistor, a primary side controller that drives the switching transistor, and the like.

One end of the secondary winding W 200 is connected to an output terminal P 200 , and the other end of the secondary winding W 200 is connected to a drain of a synchronous rectification transistor M 200 . A source of the synchronous rectification transistor M 200 is connected to a ground application terminal. An output capacitor C 200 is connected between the output terminal P 200 and a ground.

The LLC converter has a synchronous rectification controller 300 S on the secondary side. The synchronous rectification controller 300 S has a gate terminal Tg 1 , a drain terminal Td 1 , a source terminal Tg 2 , and a drain terminal Td 2 as external terminals. A gate of the synchronous rectification transistor M 200 is connected to the gate terminal Tg 1 . The drain of the synchronous rectification transistor M 200 is connected to the drain terminal Td 1 . The gate terminal Tg 2 and the drain terminal Td 2 are respectively connected to a gate and a drain of another synchronous rectification transistor (not shown) which may be provided in addition to the synchronous rectification transistor M 200 on the secondary side.

The synchronous rectification controller 300 S outputs a gate signal SG 2 from the gate terminal Tg 1 based on a drain voltage VDS 2 generated at the drain terminal Td 1 , and controls switching of the synchronous rectification transistor M 200 . By the switching of the switching transistor on the primary side and the switching of the synchronous rectification transistor M 200 on the secondary side, an input voltage applied to the primary winding is converted into an output voltage and output from the output terminal P 200 .

FIG. 7 is a timing chart illustrating a switching control of the synchronous rectification transistor M 200 in the circuit illustrated in FIG. 5 . In FIG. 7 , a current IS 2 flowing through the synchronous rectification transistor M 200 , the drain voltage VDS 2 , and the gate signal SG 2 are shown sequentially from the top side.

When the switching transistor on the primary side is switched at timing t 10 of FIG. 7 where the synchronous rectification transistor M 200 is in an OFF state, the drain voltage VDS 2 drops from a positive voltage to a negative voltage. Accordingly, the current IS 2 starts to flow through a body diode BD of the synchronous rectification transistor M 200 . The current IS 2 is a resonance current and has a sinusoidal form.

When the synchronous rectification controller 300 S detects that the drain voltage VDS 2 has become a negative voltage as described above, the synchronous rectification controller 300 S sets the gate signal SG 2 to an ON level and turns on the synchronous rectification transistor M 200 (timing t 11 ). Accordingly, the drain voltage VDS 2 is changed to a voltage value (IS 2 ×Ron) based on an on-resistance of the synchronous rectification transistor M 200 and the current IS 2 .

When the synchronous rectification controller 300 S detects that the drain voltage VDS 2 has become equal to or higher than a predetermined threshold value Vth at timing t 12 , the synchronous rectification controller 300 S sets the gate signal SG 2 to an OFF level and turns off the synchronous rectification transistor M 200 . Thereafter, the current IS 2 flows through the body diode BD until the current IS 2 becomes zero at timing t 13 .

However, a state of the circuit in FIG. 5 described above is an ideal state, and actually, as illustrated in FIG. 6 , a parasitic inductor L exists between the drain of the synchronous rectification transistor M 200 and a connection node N 2 to which the drain terminal Td 1 is connected. The parasitic inductor L is generated by a substrate pattern, a bonding wire and lead of the synchronous rectification transistor M 200 , or the like.

Therefore, the drain voltage VDS 2 becomes a value obtained by adding an induced voltage ΔVL generated in the parasitic inductor L to a drain-source voltage ΔVDS of the synchronous rectification transistor M 200 . The induced voltage ΔVL is ΔVL=L×di/dt.

FIG. 8 is a timing chart illustrating a switching control of the synchronous rectification transistor M 200 in the circuit illustrated in FIG. 6 . In FIG. 8 , the current IS 2 flowing through the synchronous rectification transistor M 200 , the drain-source voltage ΔVDS, the induced voltage ΔVL, the drain voltage VDS 2 , and the gate signal SG 2 are shown sequentially from the top side.

When the switching transistor on the primary side is switched at timing t 20 of FIG. 8 , the drain-source voltage ΔVDS is changed from a positive voltage to a negative voltage, and the current IS 2 starts to flow through the body diode BD. The induced voltage ΔVL, which is a negative voltage, is generated by a temporal slope di/dt of the increasing current IS 2 . The drain voltage VDS 2 is a sum of the drain-source voltage ΔVDS and the induced voltage ΔVL.

When the synchronous rectification controller 300 S detects that the drain voltage VDS 2 has become a negative voltage, the synchronous rectification controller 300 S sets the gate signal SG 2 to an ON level and turns on the synchronous rectification transistor M 200 (timing t 21 ). Accordingly, the drain-source voltage ΔVDS is changed to a voltage value based on the on-resistance of the synchronous rectification transistor M 200 and the current IS 2 .

The induced voltage ΔVL becomes zero at timing t 22 where the current IS 2 reaches a peak, and thereafter, the induced voltage ΔVL rises to a positive voltage by a decrease of the current IS 2 . Accordingly, the drain voltage VDS 2 , which is a value obtained by adding the induced voltage ΔVL of the positive voltage to the drain-source voltage ΔVDS, becomes equal to or higher than the threshold voltage Vth at timing t 23 , which is earlier than the timing t 12 illustrated in FIG. 7 described above. Thus, at a timing earlier than that in FIG. 7 , the gate signal SG 2 becomes an OFF level and the synchronous rectification transistor M 200 is turned off. Thereafter, the current IS 2 flows through the body diode BD until the current IS 2 becomes zero at timing t 24 .

As described above, due to the existence of the parasitic inductor L in the actual LLC converter, there was a problem that the timing when the synchronous rectification transistor M 200 is turned off arrives earlier, which results in efficiency reduction. There was also a problem that influence of the parasitic inductor L on the efficiency increases as a load (i.e., the peak of the sinusoidal current IS 2 ) increases.

Some embodiments of the present disclosure provide an isolated synchronous rectifying DC/DC converter capable of suppressing efficiency reduction.

According to one embodiment of the present disclosure, there is provided an isolated synchronous rectifying DC/DC converter configured as an LLC converter includes a synchronous rectification transistor disposed on a secondary side of the DC/DC converter and a synchronous rectification controller configured to control driving of the synchronous rectification transistor, wherein the synchronous rectification controller includes: a drain terminal connected to a drain of the synchronous rectification transistor; a first comparator configured to compare a drain voltage of the drain terminal with a first threshold voltage; a second comparator configured to compare the drain voltage of the drain terminal with a second threshold voltage; a flip-flop to which an ON signal output from the first comparator and an OFF signal output from the second comparator are input; a driver configured to output a gate signal to the synchronous rectification transistor based on an output signal of the flip-flop; and a threshold adjusting part configured to adjust the second threshold voltage based on the drain voltage (first configuration).

In the first configuration, the threshold adjusting part may include a sample hold circuit configured to sample and hold the drain voltage, and may be configured to adjust the second threshold voltage based on a sampling voltage output from the sample hold circuit (second configuration).

In the first or the second configuration, the threshold adjusting part may further include at a front stage of the sample hold circuit: a V/I conversion circuit configured to perform voltage-current conversion on the drain voltage; a first current mirror circuit receiving an output of the V/I conversion circuit as an input current; and a first resistor through which an output current of the first current mirror circuit flows (third configuration).

In the second or the third configuration, the threshold adjusting part may include a delay circuit to which an output of the flip-flop is input, and a sampling mode and a hold mode of the sample hold circuit may be switched according to a delayed signal output from the delay circuit (fourth configuration).

In the fourth configuration, a delay time of the delay circuit may be near half of a period of a current flowing through the synchronous rectification transistor (fifth configuration).

In any one of the second to the fourth configurations, the synchronous rectification controller may further include a threshold setting terminal to which a setting resistor is connected, the threshold adjusting part may further include a constant voltage circuit configured to control an output voltage to the sampling voltage, and the output voltage may be applied to the threshold setting terminal (sixth configuration).

In the sixth configuration, the threshold adjusting part may further include: a second current mirror circuit receiving a current flowing through the setting resistor as an input current; and a second resistor through which an output current of the second current mirror circuit flows so that a predetermined voltage is applied to one end of the second resistor (seventh configuration).

FIG. 1 is a circuit diagram of a DC/DC converter according to one embodiment of the present disclosure.

FIG. 2 is a circuit diagram illustrating one configuration example of a frequency divider.

FIG. 3 is a timing chart illustrating a normal operation of the DC/DC converter according to one embodiment of the present disclosure.

FIG. 4 is a timing chart illustrating an example of adjusting a second threshold voltage according to one embodiment of the present disclosure.

FIG. 5 is a circuit diagram illustrating an example of a partial configuration of a secondary side of an LLC converter.

FIG. 6 is a circuit diagram illustrating an example of a partial configuration of a secondary side of an LLC converter, where a parasitic inductor is considered.

FIG. 7 is a timing chart illustrating a switching control of a synchronous rectification transistor in the circuit illustrated in FIG. 5 .

FIG. 8 is a timing chart illustrating a switching control of a synchronous rectification transistor in the circuit illustrated in FIG. 6 .

One embodiment of the present disclosure will be now described in detail with reference to the drawings.

<Overall Configuration of LLC Converter>

FIG. 1 is a circuit diagram of a DC/DC converter 200 A according to one embodiment of the present disclosure. The DC/DC converter 200 A is an isolated synchronous rectifying DC/DC converter as an LLC converter. The DC/DC converter 200 A generates an output voltage Vout based on an input voltage Vin applied to an input terminal P 1 and outputs the output voltage Vout from an output terminal P 2 .

The DC/DC converter 200 A has a primary side configuration that includes switching transistors M 11 and M 12 , a primary side controller 202 A, a resonance capacitor Cr, and a primary winding W 1 of a transformer T 1 . The DC/DC converter 200 A has a secondary side configuration that includes secondary windings W 21 and W 22 of the transformer T 1 , first and second synchronous rectification transistors M 21 and M 22 , an output capacitor C 1 , resistors R 21 and R 22 , a diode DD, a capacitor CC, and a synchronous rectification controller 300 A.

A drain of the switching transistor M 11 is connected to the input terminal P 1 to which the DC input voltage Vin is applied. A source of the switching transistor M 11 is connected to a drain of the switching transistor M 12 . A source of the switching transistor M 12 is connected to a ground application terminal. One end of the resonance capacitor Cr is connected to a connection node to which the switching transistor M 11 and the switching transistor M 12 are connected. The other end of the resonance capacitor Cr is connected to one end of the primary winding W 1 . The other end of the primary winding W 1 is connected to the source of the switching transistor M 12 .

The primary side controller 202 A controls switching of the switching transistors M 11 and M 12 by outputting a driving signal to gates of the switching transistors M 11 and M 12 .

One end of the secondary winding W 21 is connected to a drain of the first synchronous rectification transistor M 21 . The first synchronous rectification transistor M 21 has a body diode BD 1 . A source of the first synchronous rectification transistor M 21 is connected to a ground terminal P 3 . The ground terminal P 3 is connected to a ground application terminal.

The other end of the secondary winding W 21 is connected to one end of the secondary winding W 22 . The other end of the secondary winding W 22 is connected to a drain of the second synchronous rectification transistor M 22 . The second synchronous rectification transistor M 22 has a body diode BD 2 . A source of the second synchronous rectification transistor M 22 is connected to the ground terminal P 3 .

A connection node to which the secondary winding W 21 and the secondary winding W 22 are connected is connected to the output terminal P 2 . The output capacitor C 1 is connected between the output terminal P 2 and the ground terminal P 3 . The resistor R 21 and the resistor R 22 are connected in series between the output terminal P 2 and the ground terminal P 3 . A feedback (FB) circuit 206 is connected to a connection node to which the resistors R 21 and R 22 are connected.

The FB circuit 206 has, for example, a shunt regulator and the like, and drives a light emitting element of a photocoupler 204 with a current corresponding to an error between a voltage obtained by dividing the output voltage Vout by the resistors R 21 and R 22 and a predetermined target voltage. A feedback current Ifb corresponding to the error flows through a light receiving element of the photocoupler 204 . A feedback signal Vfb corresponding to the feedback current Ifb is generated at a feedback (FB) pin of the primary side controller 202 A. The primary side controller 202 A drives the switching transistors M 11 and M 12 based on the feedback signal Vfb.

The synchronous rectification controller 300 A includes a low dropout (LDO) regulator 301 , a selector 302 , a frequency divider 303 , a flip-flop 304 , a first comparator 305 , a second comparator 306 , a threshold adjusting part 307 , a first driver Dr 21 , and a second driver Dr 22 , which are received in one package.

The synchronous rectification controller 300 A further includes a first drain terminal D 21 , a first gate terminal G 21 , a second drain terminal D 22 , a second gate terminal G 22 , a power terminal VCC, a ground terminal GND, and a threshold setting terminal TH, which establish electrical connection with external devices.

The first drain terminal D 21 to which the drain of the first synchronous rectification transistor M 21 is connected is connected to one terminal of an input terminal 302 A of the selector 302 . The second drain terminal D 22 to which the drain of the second synchronous rectification transistor M 22 is connected is connected to the other terminal of the input terminal 302 A. An output terminal 302 B of the selector 302 is connected to an inverting input terminal (−) of each of the first comparator 305 and the second comparator 306 . The selector 302 switches between conduction of a path from the first drain terminal D 21 to the output terminal 302 B and conduction of a path from the second drain terminal D 22 to the output terminal 302 B. That is to say, the selector 302 selects which of a drain voltage VDS 21 of the first drain terminal D 21 and a drain voltage VDS 22 of the second drain terminal D 22 to be detected by the first comparator 305 and the second comparator 306 .

A first threshold voltage VthA is applied to a non-inverting input terminal (+) of the first comparator 305 . The first threshold voltage VthA is based on a ground potential. An output terminal of the first comparator 305 is connected to a set terminal of the flip-flop 304 . The first comparator 305 detects that the drain voltages VDS 21 and VDS 22 have dropped to a negative voltage, which is caused by turning on the switching transistors M 11 and M 12 , by detecting that the drain voltages VDS 21 and VDS 22 have become equal to or lower than the first threshold voltage VthA (e.g., −200 mV). At this time, the first comparator 305 asserts an ON signal Son. The first synchronous rectification transistor M 21 and the second synchronous rectification transistor M 22 are turned on according to the asserted ON signal Son.

A second threshold voltage VthB is applied to a non-inverting input terminal (+) of the second comparator 306 . The second threshold voltage VthB is adjusted by the threshold adjusting part 307 , as will be described later. An output terminal of the second comparator 306 is connected to a reset terminal of the flip-flop 304 . The second comparator 306 detects a zero current, i.e., detects that currents Is 21 and Is 22 flowing by the first synchronous rectification transistor M 21 and the second synchronous rectification transistor M 22 , which are turned on, become substantially zero, by detecting that the drain voltages VDS 21 and VDS 22 have become equal to or higher than the second threshold voltage VthB (e.g., −6 mV). At this time, the second comparator 306 asserts an OFF signal Soff. The first synchronous rectification transistor M 21 and the second synchronous rectification transistor M 22 are turned off according to the asserted OFF signal Soff.

A Q output terminal of the flip-flop 304 is connected to an input terminal of the frequency divider 303 . The frequency divider 303 has, for example, a configuration illustrated in FIG. 2 , and includes a D flip-flop 303 A and an inverter 303 B. A Q output signal SQ from the flip-flop 304 is input to a clock terminal of the D flip-flop 303 A. An input terminal of the inverter 303 B is connected to a Q output terminal of the D flip-flop 303 A. An output terminal of the inverter 303 B is connected to a D input terminal of the D flip-flop 303 A.

With this configuration, a frequency divider output signal Sf output from the Q output terminal of the D flip-flop 303 A is switched between High and Low at every falling timing of the Q output signal SQ from High to Low. The frequency divider 303 outputs the frequency divider output signal Sf by doubling a cycle of the Q output signal SQ input to the frequency divider 303 .

The frequency divider output signal Sf is output to the selector 302 . The selector 302 switches between the input terminal 302 A and the output terminal 302 B and between an input terminal 302 D and an output terminal 302 C according to a level of the frequency divider output signal Sf. One terminal of the output terminal 302 C is connected to an input terminal of the first driver Dr 21 . An output terminal of the first driver Dr 21 is connected to the gate of the first synchronous rectification transistor M 21 via the first gate terminal G 21 . The first driver Dr 21 outputs a gate signal SG 21 having a level switched according to a level of the input signal.

The other terminal of the output terminal 302 C is connected to an input terminal of the second driver Dr 22 . The output terminal of the second driver Dr 22 is connected to the gate of the second synchronous rectification transistor M 22 via the second gate terminal G 22 . The second driver Dr 22 outputs a gate signal SG 22 having a level switched according to the level of the input signal.

The conduction of a path from the input terminal 302 D to the first driver Dr 21 and the conduction of a path from the input terminal 302 D to the second driver Dr 22 are switched by the selector 302 . The Q output signal SQ is input to the input terminal 302 D. Thus, the selector 302 selects one of the first driver Dr 21 and the second driver Dr 22 to which the Q output signal SQ is input.

An anode of the diode DD is connected to the output terminal P 2 . A cathode of the diode DD is connected to one end of the capacitor CC and the power terminal VCC. The other end of the capacitor CC is connected to the ground terminal P 3 . The LDO regulator 301 generates and outputs an internal voltage based on the input voltage applied to the power terminal VCC. A part of the internal voltage is supplied to high potential sides of the first driver Dr 21 and the second driver Dr 22 .

The threshold adjusting part 307 is a circuit for adjusting the second threshold voltage VthB, details of which will be described later.

<Basic Operation of LLC Converter>

Next, an operation of the DC/DC converter 200 A configured as described above will be described.

Here, description will be made with reference to a timing chart illustrated in FIG. 3 . In FIG. 3 , the current Is 21 , the drain voltage VDS 21 , the gate signal SG 21 , the Q output signal SQ, the frequency divider output signal Sf, the gate signal SG 22 , the drain voltage VDS 22 , and the current Is 22 are indicated sequentially from the top side.

Before timing t 0 , the frequency divider output signal Sf is Low, and the drain voltage VDS 22 of the second drain terminal D 22 as a detection target and the second driver Dr 22 as an output destination of the Q output signal SQ are selected by the selector 302 . Then, when the switching transistor M 11 is turned on at the timing t 0 , the drain voltage VDS 22 drops to a negative voltage and the current Is 22 starts to flow through the body diode BD 2 . The current Is 22 is a resonance current, and has a sinusoidal form.

The first comparator 305 detects that the drain voltage VDS 22 has dropped to a negative voltage, and asserts the ON signal Son. Accordingly, the Q output signal SQ is switched to High, the gate signal SG 22 becomes an ON level by the second driver Dr 22 , and the second synchronous rectification transistor M 22 is turned on at timing t 1 . Thus, the current Is 22 starts to flow from the source to the drain of the second synchronous rectification transistor M 22 .

The drain voltage VDS 22 is changed to a voltage value (Is 22 ×Ron 22 ) based on the current Is 22 and an on-resistance of the synchronous rectification transistor M 22 . As will be described later, a parasitic inductor also affects the drain voltage VDS 22 .

Then, at timing t 2 , the second comparator 306 detects that the current Is 22 has become a zero current based on the drain voltage VDS 22 , and asserts the OFF signal Soff. That is to say, the drain voltage VDS 22 at this time becomes equal to or higher than the second threshold voltage VthB. Accordingly, the Q output signal SQ is switched to Low, the gate signal SG 22 becomes an OFF level, and the second synchronous rectification transistor M 22 is turned off. At this time, the frequency divider output signal Sf is switched to High. Accordingly, the drain voltage VDS 21 of the first drain terminal D 21 as the detection target and the first driver Dr 21 as the output destination of the Q output signal SQ are selected by the selector 302 .

In the second synchronous rectification transistor M 22 which is turned off, the current Is 22 continues to flow through the body diode BD 2 . The current Is 22 does not flow at timing t 3 .

Then, when the switching transistor M 12 is turned on at timing t 4 , the drain voltage VDS 21 drops to a negative voltage and the current Is 21 starts to flow through the body diode BD 1 . The current Is 21 is a resonance current, and has a sinusoidal form.

The first comparator 305 detects that the drain voltage VDS 21 has dropped to a negative voltage, and asserts the ON signal Son. Accordingly, the Q output signal SQ is switched to High, the gate signal SG 21 become an ON level by the second driver Dr 21 , and the first synchronous rectification transistor M 21 is turned on at timing t 5 . Thus, the current Is 21 starts to flow from the source to the drain of the first synchronous rectification transistor M 21 .

The drain voltage VDS 21 is changed to a voltage value (Is 21 ×Ron 21 ) based on the current Is 21 and an on-resistance of the first synchronous rectification transistor M 21 . As will be described later, a parasitic inductor also affects the drain voltage VDS 21 .

Then, at timing t 6 , the second comparator 306 detects that the current Is 21 has become a zero current based on the drain voltage VDS 21 , and asserts the OFF signal Soff. That is to say, the drain voltage VDS 21 at this time becomes equal to or higher than the second threshold VthB. Accordingly, the Q output signal SQ is switched to Low, the gate signal SG 21 becomes an OFF level, and the first synchronous rectification transistor M 21 is turned off. At this time, the frequency divider output signal Sf is switched to Low. Accordingly, the drain voltage VDS 22 of the second drain terminal D 22 as the detection target and the second driver Dr 22 as the output destination of the Q output signal SQ are selected by the selector 302 .

In the first synchronous rectification transistor M 21 which is turned off, the current Is 21 continues to flow through the body diode BD 1 . The current Is 21 does not flow at timing t 7 . Thereafter, the same repetitive operation is performed.

<About Threshold Adjusting Part>

Next, the threshold adjusting part 307 will be described in detail. The threshold adjusting part 307 has a V/I conversion circuit 307 A, a current mirror circuit 307 B, a sample hold circuit 307 C, a delay circuit 307 D, a constant voltage circuit 307 E, a current mirror circuit 307 F, and resistors R 1 and R 2 .

The output terminal 302 B of the selector 302 is connected to one input terminal of the V/I conversion circuit 307 A. That is to say, the V/I conversion circuit 307 A performs voltage-current conversion on selected one of the input drain voltages VDS 21 and VDS 22 , and outputs the conversion result. An output of the V/I conversion circuit 307 A is input to an input terminal of the current mirror circuit 307 B. An output terminal of the current mirror circuit 307 B is connected to one end of the resistor R 1 . The other end of the resistor R 1 is connected to a ground application terminal. The current mirror circuit 307 B mirrors an input current from the V/I conversion circuit 307 A at a predetermined magnification and allows an output current to flow through the resistor R 1 . Thus, a voltage corresponding to the output current is generated across the resistor R 1 .

The sample hold circuit 307 C has a sampling switch SW and a hold capacitor HC. One input terminal of the sampling switch SW is connected to a connection node to which the output terminal of the current mirror circuit 307 B and one end of the resistor R 1 are connected. One end of the hold capacitor HC is connected to an output terminal of the sampling switch SW. The other input terminal of the sampling switch SW is open.

The Q output signal SQ is input to the delay circuit 307 D. The delay circuit 307 D outputs a delayed signal SD, which is obtained by delaying the input Q output signal SQ by a predetermined time period, to the sampling switch SW. The sampling switch SW performs switching based on the delayed signal SD.

Specifically, when the delayed signal SD is Low, one input terminal of the sampling switch SW, namely the connection node between the current mirror circuit 307 B and the resistor R 1 , and the output terminal of the sampling switch SW are conducted. At this time, the sample hold circuit 307 C enters a sampling mode in which a voltage generated at the connection node is directly output from the sampling switch SW.

On the other hand, when the delayed signal SD is High, the other input terminal and the output terminal of the sampling switch SW are conducted, and the output terminal is open. At this time, the sample hold circuit 307 C enters a hold mode in which the voltage at the output terminal immediately before the sampling switch SW is switched is held by the hold capacitor HC.

The constant voltage circuit 307 E has an error amplifier EA and a transistor M 1 . A sampling voltage VS, which is an output of the sample hold circuit 307 C, is input to a non-inverting input terminal (+) of the error amplifier EA. An inverting input terminal (−) of the error amplifier EA is connected to a source of the transistor M 1 . An output terminal of the error amplifier EA is connected to a gate of the transistor M 1 . A voltage of a connection node NP 1 , to which the inverting input terminal of the error amplifier EA and the source of the transistor M 1 are connected, is controlled to be constant by the constant voltage circuit 307 E to the input sampling voltage VS.

One end of an external setting resistor Rth is connected to the connection node NP 1 via the threshold setting terminal TH. A drain of the transistor M 1 is connected to an input terminal of the current mirror circuit 307 F. A current generated by the voltage generated at the connection node NP 1 and the setting resistor Rth becomes an input current of the current mirror circuit 307 F. The current mirror circuit 307 F mirrors and outputs the input current at a predetermined magnification.

An output terminal of the current mirror circuit 307 F is connected to a connection node NP 2 to which one end of the resistor R 2 and the non-inverting input terminal (+) of the second comparator 306 are connected. A predetermined voltage Vth 1 is applied to the other end of the resistor R 2 . Since the output current from the current mirror circuit 307 F flows through the resistor R 2 , the second threshold voltage VthB is generated at the connection node NP 2 .

With this configuration, the second threshold voltage VthB may be expressed by the following equation (1):

VthB =( VS/Rth )× N×R 2+ Vth 1,  Equation (1)

wherein N is a predetermined magnification of mirroring in the current mirror circuit 307 F.

When the second synchronous rectification transistor M 22 is turned on, the drain voltage VDS 22 is influenced by a parasitic inductor L 22 existing between the drain of the second synchronous rectification transistor M 22 and the connection node NP 22 between the drain of the second synchronous rectification transistor M 22 and the second drain terminal D 22 . That is to say, the drain voltage VDS 22 becomes a value obtained by adding an induced voltage ΔVL (=L 22 ×di/dt) caused by the parasitic inductor L 22 to a drain-source voltage ΔVDS of the second synchronous rectification transistor M 22 .

Similarly, when the first synchronous rectification transistor M 21 is turned on, the drain voltage VDS 21 is influenced by a parasitic inductor L 21 existing between the drain of the first synchronous rectification transistor M 21 and a connection node NP 21 between the drain of the first synchronous rectification transistor M 21 and the first drain terminal D 21 . That is to say, the drain voltage VDS 21 becomes a value obtained by adding an induced voltage ΔVL (=L 21 ×di/dt) caused by the parasitic inductor L 21 to a drain-source voltage ΔVDS of the first synchronous rectification transistor M 21 .

The currents Is 22 and Is 21 have a sinusoidal form, and a peak of each of the currents Is 22 and Is 2 varies according to a load. Therefore, the temporal slopes (di/dt) of the currents Is 22 and Is 21 vary according to the load and affect the drain voltages VDS 22 and VDS 21 . The sampling voltage VS is obtained by sample-holding the drain voltages VDS 22 and VDS 21 , and indicates the magnitude of the load. Therefore, according to the above Equation (1), the second threshold voltage VthB is adjusted to be larger as the sampling voltage VS increases, namely as the load increases. This makes it possible to adjust turning-off timings of the synchronous rectification transistors M 22 and M 21 by the second comparator 306 according to the load, and to suppress efficiency reduction.

In addition, as can be seen from the above Equation (1), it is possible to set a correction factor corresponding to the parasitic inductor by the external setting resistor Rth.

<Specific Example of Threshold Voltage Adjustment>

Here, a specific example of adjusting the second threshold voltage VthB by the threshold adjusting part 307 will be described with reference to a timing chart illustrated in FIG. 4 . Although a case of turning on and turning off the second synchronous rectification transistor M 22 will be described herein, the same can be applied to the first synchronous rectification transistor M 21 .

In FIG. 4 , the current Is 22 , the drain-source voltage ΔVDS of the second synchronous rectification transistor M 22 , the induced voltage ΔVL by the parasitic inductor L 22 existing between the connection node NP 22 and the drain of the second synchronous rectification transistor M 22 , the drain voltage VDS 22 , the gate signal SG 22 , the Q output signal SQ, the delayed signal SD, and the sampling voltage VS are shown sequentially from the top side. The drain voltage VDS 22 is a voltage value obtained by adding the drain-source voltage ΔVDS and the induced voltage ΔVL.

At timing T 0 of FIG. 4 , when the drain-source voltage ΔVDS drops to a negative voltage, the current Is 22 starts to flow through the body diode BD 2 . Since the current Is 22 increases, the induced voltage ΔVL is generated as a negative voltage. When the first comparator 305 detects that the drain-source voltage ΔVDS has dropped to a negative voltage based on the drain voltage VDS 22 , the first comparator 305 asserts the ON signal Son. Accordingly, the Q output signal SQ rises to High, the gate signal SG 22 becomes an ON level, and the synchronous rectification transistor M 22 is turned on at timing T 1 .

Thereafter, the drain-source voltage ΔVDS is changed to a voltage value (Is 22 ×Ron) based on the current Is 22 and the on-resistance of the synchronous rectification transistor M 22 , and the induced voltage ΔVL is changed to a voltage value (L 22 ×di/dt) corresponding to the temporal slope of the current Is 22 . The drain voltage VDS 22 is a voltage obtained by adding the drain-source voltage ΔVDS and the induced voltage ΔVL.

At timing T 3 , the current Is 22 reaches a peak and the induced voltage ΔVL becomes zero. At timing T 2 delayed from the rise of the Q output signal SQ to High by a delay time td (e.g., 2 μs), the delayed signal SD rises to High. The timing T 2 is near the timing T 3 . In some embodiments, the delay time td may be set to a value (e.g., 2 μs) near half of a period (e.g., 5 μs) of the sinusoidal current Is 22 .

The sampling switch SW is switched by the rise of the delayed signal SD, and the sample hold circuit 307 C holds the sampling voltage VS. That is to say, the delay circuit 307 D can hold the drain voltage VDS 22 at a timing near the peak of the current Is 22 . In FIG. 4 , for the sake of convenience, only a voltage during the holding mode is shown for the sampling voltage VS, and illustration of the sampling voltage Vs during the sampling mode is omitted.

Based on the sampling voltage VS held at the timing T 2 , the second threshold voltage VthB is set by the above Equation (1). After the timing T 3 , since the current Is 22 decreases, the induced voltage ΔVL rises to a positive voltage. The induced voltage ΔVL is added to the drain-source voltage ΔVDS and the drain voltage VDS 22 is obtained.

At timing T 4 , the second comparator 306 detects that the drain voltage VDS 22 becomes equal to or higher than the second threshold voltage VthB, and asserts the OFF signal Soff. Accordingly, the Q output signal SQ is set to Low, the gate signal SG 22 becomes an OFF level, and the synchronous rectification transistor M 22 is turned off. At this time, the delayed signal SD becomes Low. The sampling switch SW is switched and the sample hold circuit 307 C enters a sampling mode.

Thereafter, the current Is 22 flows through the body diode BD 2 until the current Is 22 becomes zero at timing T 5 .

As described above, since the second threshold voltage VthB is appropriately set according to the held sampling voltage VS, namely the magnitude of the load, the synchronous rectification transistor M 22 can be turned off at an appropriate timing at which the current Is 22 becomes a zero current. Thus, it is possible to suppress efficiency reduction.

<Others>

While the embodiment of the present disclosure has been described above, the embodiment may be differently modified without departing from the spirit of the present disclosure.

The present disclosure can be suitably used for an LLC converter.

According to the isolated synchronous rectifying DC/DC converter of the present disclosure, it is possible to suppress efficiency reduction.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.