Transmitting device and receiving device providing relaxed impedance matching

This application claims the benefit of Korean Patent Application No. 10-2018-0062901, filed on May 31, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Example embodiments of the inventive concepts relate to an integrated circuit device. For example, at least some example embodiments relate to an integrated circuit device including a transmitting device and/or a receiving device providing adaptively relaxed impedance matching.

In high-speed interconnect, channels of various impedance and transmitters/receivers of various impedances are used. For example, a backplane channel may be configured to have various impedance values according to a standard. For example, a channel of about 40Ω to about 50Ω, and transmitters/receivers of about 25Ω to about 60Ω may be used in a high speed memory interface such as double data rate (DDR) fourth-generation (DDR4) or graphics DDR version 5 (GDDR5). In addition, various types of cables, for example, coaxial cables and biaxial cables, of about 30δ to about 100Ω, are used.

Various impedance standards of transmitters, channels, and receivers inconvenience a user in terms of compatibility. Particularly, when devices of different impedance standards are connected to each other, impedance mismatching affects signal integrity, and as a result, causes communication errors.

Example embodiments of the inventive concepts provide an integrated circuit device including a transmitting device and/or a receiving device providing adaptively relaxed impedance matching.

According to an example embodiment of the inventive concepts, there is provided a transmitting device configured to connect to a receiving device via a channel. In some example embodiments, the transmitting device may include a transmitter connected to the channel via an output node, the transmitter configured to transmit, via the channel, a transmission signal to the receiving device, the transmitter having a transmission impedance associated therewith that is variable; and a monitoring device configured to detect a channel impedance of the channel and a receiving impedance of the receiving device by monitoring a voltage level of the output node, and to set the transmission impedance based on the channel impedance and the receiving impedance.

According to another example embodiment of the inventive concepts, there is provided a receiving device configured to connect to a transmitting device via a channel. In some example embodiments, the receiving device includes a receiver connected to the channel via an input node, the receiver configured to receive, via the channel, a receiving signal from the transmitting device, the receiver having a receiving impedance associated therewith that is variable; and a monitoring device configured to detect a channel impedance of the channel and a transmission impedance of the transmitting device by monitoring a voltage level of the input node, and to set the receiving impedance based on the channel impedance and the transmission impedance.

According to another example embodiment of the inventive concepts, there is provided a transmitter configured to connect to a receiver via a channel. In some example embodiments, the transmitter may include a transmitting driver having a transmission impedance associated therewith that is adaptive to a channel impedance of the channel and a receiving impedance of the receiver; and an on-chip monitor configured to set the transmission impedance based on the channel impedance, the receiving impedance and a relaxed impedance matching constraint, wherein the on-chip monitor and the transmitting driver are integrated on a same chip.

Example embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 illustrates a system according to an example embodiment of the inventive concepts;

FIG. 2 illustrates an interconnect model for explaining a transfer function for the system of FIG. 1 ;

FIG. 3A shows transfer a transfer function under a relaxed impedance matching constraint according to an example embodiment of the inventive concepts and a transfer function under an impedance matching constraint;

FIG. 3B shows graphs of magnitudes of a transfer function at various transmission impedance constraints and various receiving impedance constraints according to an example embodiment of the inventive concepts;

FIG. 4A schematically illustrates a system according to an example embodiment of the inventive concepts;

FIG. 4B is a graph of pulse response at various transmission impedance and current conditions according to an example embodiment of the inventive concepts;

FIG. 5 is a circuit diagram illustrating in detail a first device according to an example embodiment of the inventive concepts;

FIG. 6 is a circuit diagram illustrating a first variable transmission resistor according to an example embodiment of the inventive concepts;

FIG. 7A is a circuit diagram illustrating a slicer according to an example embodiment of the inventive concepts;

FIG. 7B is a circuit diagram illustrating an amplifier current generator illustrated in FIG. 7A ;

FIG. 8 is a circuit diagram illustrating a comparator in FIG. 7A ;

FIG. 9 is a circuit diagram illustrating a first device according to an example embodiment of the inventive concepts;

FIG. 10 is a flowchart of a method of configuring transmission impedance, according to an example embodiment of the inventive concepts;

FIGS. 11A through 12B illustrate a receiving impedance detection operation according to an operation S 110 in FIG. 10 ;

FIGS. 13A through 13C illustrate a flight time detection operation according to an operation S 120 in FIG. 10 ;

FIGS. 14A through 14C illustrate a channel impedance detection operation according to an operation S 140 in FIG. 10 ;

FIG. 15 is a flowchart of a method of configuring transmission impedance, according to an example embodiment of the inventive concepts;

FIGS. 16A and 16B illustrate a channel impedance detection operation according to an operation S 230 in FIG. 15 ;

FIGS. 17A and 17B illustrate a receiving impedance detection operation according to an operation S 240 in FIG. 15 ; and

FIG. 18 illustrates a system according to an example embodiment of the inventive concepts.

Hereinafter, example embodiments of the inventive concepts swill be described in detail with reference to the accompanying drawings. Identical reference numerals are used for the same constituent elements in the drawings, and a duplicate description thereof is omitted.

FIG. 1 illustrates a system 10 according to an example embodiment.

Referring to FIG. 1 , the system 10 may include a first device 100 , a second device 200 , and a channel 300 . The first device 100 and the second device 200 may be connected to each other via the channel 300 . For example, the first device 100 may operate as a transmitting device and the second device 200 may operate as a receiving device, and thus, the system 10 may perform uni-directional communication. However, the inventive concepts are not limited thereto. The first device 100 and the second device 200 may perform both a transmission operation and a receiving operation, respectively, so that the system 10 may perform bi-directional communication.

The first device 100 may include a transmitting block (or, alternatively, a transmitter) 110 and a monitor (or, alternatively, a monitoring device) 120 . The transmitting block 110 may be connected to the channel 300 via an output node to transmit a transmission signal to the second device 200 . In an example embodiment, the transmitting block 110 may include a first output node ND 1 and a second output node ND 2 and may transmit a differential transmission signal to the second device 200 via the first output node ND 1 and the second output node ND 2 . However, the inventive concepts are not limited thereto, and the transmitting block 110 may transmit a single-ended transmission signal via a single output node.

The channel 300 may have channel impedance Z 0 . In an example embodiment, the channel 300 may include a first transmission line TL 1 and a second transmission line TL 2 . The first transmission line TL 1 may be connected to the first output node ND 1 , and the second transmission line TL 2 may be connected to the second output node ND 2 . Accordingly, the first device 100 may transmit the differential transmission signal to the second device 200 . However, the inventive concepts are not limited thereto. The channel 300 may include a single transmission line, and the first device 100 may transmit a single-ended transmission signal to the second device 200 .

The second device 200 may include a receiving block (or, alternatively, a receiver) 210 , and the receiving block 210 may have receiving impedance R RX . The first device 100 may be connected to the channel 300 , which is one of various types of channels, and may be connected to the second device 200 , which is one of various receiving devices via the channel 300 . Accordingly, the channel impedance Z 0 and the receiving impedance R RX in the system 10 may be variously changed. When the transmitting block 110 has fixed transmission impedance, impedance mismatching may affect signal integrity of the transmission signals and as a result, may cause errors in communication between the first device 100 and the second device 200 .

According to an example embodiment, the transmitting block 110 may have transmission impedance R TX that is adaptively configured to the channel impedance Z 0 and the receiving impedance R RX . Since the transmission impedance R TX and the receiving impedance R RX are usually resistance components, the transmission impedance R TX and the receiving impedance R RX are referred to herein as substantially the same as a transmission resistance and a receiving resistance, respectively.

In a training mode for configuring the transmission impedance R TX , the monitor 120 may detect the channel impedance Z 0 and the receiving impedance R RX by monitoring a first voltage level of the first output node ND 1 and a second voltage level of the second output node ND 2 , and the transmission impedance R TX may be configured based on the detected channel impedance Z 0 and the receiving impedance R RX . When configuration of the transmission impedance R TX is completed, in a normal mode, the first device 100 may provide normal data signals via the first and second output nodes ND 1 and ND 2 .

In an example embodiment, the monitor 120 may calculate the transmission impedance R TX according to relaxed impedance matching constraints, which allows a voltage level of the transmission signal arriving at the second device 200 to be increased within a range in which reflection of the transmission signal in the second device 200 is not increased, and the monitor 120 may configure the transmission impedance R TX of the transmitting block 110 according to the calculated transmission impedance R TX . The relaxed impedance matching constraints are described in detail with reference to FIG. 2 .

In an example embodiment, in the first device 100 , the transmitting block 110 and the monitor 120 may be implemented on one same chip and thus, the monitor 120 may be referred to as an on-chip monitor. For example, the monitor 120 may be a time domain reflectometer (TDR) monitor. In an example embodiment, the first device 100 may include a plurality of transmitting blocks. In this case, the monitor 120 may be connected to the plurality of transmitting blocks 110 in common, and the plurality of transmitting blocks 110 may share the monitor 120 . In addition, the plurality of transmitting blocks 110 may transmit a plurality of transmission signals to the second device 200 via a plurality of transmission lines, respectively.

FIG. 2 illustrates an interconnect model for explaining a transfer function for the system 10 of FIG. 1 .

Referring to FIG. 2 , a transmitter TX may be connected to a receiver RX via the channel CH. The transmitter TX may correspond to a modeling result of the first device 100 of FIG. 1 and the receiver RX may correspond to a modeling result of the second device 200 of FIG. 1 . Hereinafter, it is assumed that impedance Z TX (ω) of the transmitter TX, impedance Z RX (ω) of the receiver RX, and impedance Z c (ω) of the channel CH are all resistance components, and thus, it will be denoted as Z TX (ω)=R TX , Z RX (ω)=R RX , and Z c (ω)=Z 0 , where ω denotes an angular frequency. Here, the transfer function may be derived as shown in Formula 1 below.

Here, R TX may be the transmission impedance of the transmitter TX, R RX may be the receiving impedance of the receiver RX, and Z 0 may be the channel impedance of the channel CH. In addition, Γ TX may be a reflection coefficient of the transmitter TX, Γ RX may be the reflection coefficient of the receiver RX, and L is a length of the channel CH. The reflection coefficient Γ TX of the transmitter TX and the reflection coefficient Γ RX of the receiver RX may be expressed by Formula 2 and Formula 3, respectively. Here, V L(ω) denotes a voltage across the receiving impedance of the receiver RX, I S(ω) denotes current provided by the transmitter TX, and γ(ω) denotes a reflection coefficient of the channel CH.

Γ TX =( R TX −Z 0 )/( R TX +Z 0 )  [Formula 2]

Γ RX =( R RX −Z 0 )/( R RX +Z 0 )  [Formula 3]

The relaxed impedance matching constraint according to an example embodiment may be expressed by Formula 4 below.

|Γ TX Γ RX e −2Lγ(ω) |<<1  [Formula 4]

In an example embodiment, the relaxed impedance matching constraint may configure |Γ TX Γ RX e −2Lγ(ω) | to take a value of K, which is a number between 0 and 1. For example, when K is about 0.03, a range of the transmission impedance R TX may be determined such that |Γ TX Γ RX e −2Lγ(ω) | is equal to or less than about 0.03. On the other hand, when Formula 4 is satisfied, Formula 1 may be approximated by Formula 5 below.

FIG. 3A shows a transfer function under the relaxed impedance matching constraint according to an example embodiment and a transfer function under an impedance matching constraint.

Referring to FIGS. 2 and 3A , when the impedance matching constraint is satisfied, the transmission impedance R TX may be equal to the reception impedance R RX and the channel impedance Z 0 (that is, R TX =R RX =Z 0 ). In this case, Formula 5 may be expressed as Formula 6 below.

On the other hand, when the relaxed impedance matching constraint (that is, Formula 4) is satisfied, the transmission impedance R TX may not be equal to the channel impedance Z 0 and the reception impedance R RX may not be equal to the channel impedance Z 0 (that is, R TX ≠Z 0 , R RX ≠Z 0 ). In this case, the transfer function may be the same as that in Formula 5.

FIG. 3B shows graphs of magnitudes of the transfer function at various transmission impedance constraints and various receiving impedance constraints according to an example embodiment.

Referring to FIGS. 2 through 3B , the horizontal axis may represent a frequency and the vertical axis may represent a magnitude of the transfer function. A first graph 31 may represent the magnitude of the transfer function according to the frequency when the relaxed impedance matching constraint (that is, Formula 4) is satisfied, and a second graph 32 may represent the magnitude of the transfer function according to the frequency when the impedance matching constraint is satisfied. Since Formula 5 and Formula 6 both include e −Lγ(ω) , shapes of frequency spectra of the first and second graphs 31 and 32 may be almost the same. Thus, both the case where the relaxed impedance matching constraint is satisfied and the case where the impedance matching condition is satisfied may have the same influence effect of signal reflection by the receiver RX in a time domain.

On the other hand, the magnitude of the transfer function of the first graph 31 may be greater than that of the transfer function of the second graph 32 at the same frequency. In this manner, a magnitude of the transmission signal transmitted to the receiver RX, in the case when the relaxed impedance matching constraint is satisfied, may be greater than that of the transmission signal transmitted to the receiver RX in the case when the impedance matching constraint is satisfied. Thus, the voltage level of the transmission signal arriving at the receiver RX may be increased within a range in which the reflection of the transmission signal at the receiver RX is not increased, by configuring the transmission impedance R TX according to the relaxed impedance matching constraint.

FIG. 4A schematically illustrates a system 10 a according to an example embodiment.

Referring to FIG. 4A , the system 10 a may include a first device 100 a , the second device 200 , and the channel 300 . The first device 100 a may be implemented in a current mode logic (CML) structure. The first device 100 a may include a first current generator (CG) CG 1 for generating a first current I a . The first device 100 a may further include a first transistor TR 1 including a gate to which a negative data signal D n is applied and connected to the first output node ND 1 , and a second transistor TR 2 including a gate to which a positive data signal D n is applied and connected to the second output node ND 2 . At this time, the largest value among the transmission impedances satisfying the relaxed impedance matching constraint may be a good impedance in terms of performance and power efficiency of the first device 100 a.

However, the inventive concepts are not limited thereto, and in some example embodiments, a transmitting device may be implemented in a voltage mode logic structure such as a source series terminated (SST) driver. At this time, the lowest value among the transmission impedances satisfying the relaxed impedance matching constraint may be adequate impedance in terms of performance and power efficiency of a transmitting device.

For example, when the transmitting device is implemented in the voltage mode logic architecture, the transmitting device may include a p-channel metal-oxide-semiconductor (PMOS) transistor including a gate connected between a power supply voltage terminal and the output node and to which a data signal is applied, an n-channel metal-oxide-semiconductor (NMOS) transistor including a gate connected between the output node and a ground voltage terminal and to which the data signal is applied, and a variable transmission resistor connected to the output node. Here, the resistance value of the variable transmission resistor may be configured to be the lowest value in a range satisfying Formula 4.

FIG. 4B is a graph of pulse response at various transmission impedance and current conditions according to an example embodiment;

Referring to FIG. 4B , the horizontal axis may represent time and the vertical axis may represent pulse response. A first impedance R 1 may be the minimum value of the transmission impedance R TX satisfying the relaxed impedance matching constraint and a second impedance R 2 may be the maximum value of the transmission impedance R TX satisfying the relaxed impedance matching constraint. A first curve 41 may represent the case in which the transmission impedance R TX is a first impedance R 1 and the first current I a is a first current value I 1 , a second curve 42 may represent the case in which the transmission impedance R TX is a second impedance R 2 greater than the first impedance R 1 , and a third curve 43 may represent the case in which the transmission impedance R TX is a second impedance R 2 and the first current I a is a second current value I 2 less than the first current value I 1 . For example, the first impedance R 1 may be about 38Ω and the second impedance R 2 may be about 65Ω.

Comparing the first and second curves 41 and 42 , it may be understood that, when the first current I a is the same, the pulse response indicates a higher voltage level as the transmission impedance R TX increases. Comparing the first and third curves 41 and 43 , it may be understood that an amount of the first current I a required to obtain the same pulse response decreases as the transmission impedance R TX increases. In this manner, when the transmission impedance R TX is configured to the second impedance R 2 , which is the maximum value satisfying Formula 4, a magnitude of a signal transmitted to the second device 200 may be increased with low power consumption. Thus, a power efficiency may be improved by configuring the transmission impedance R TX according to the relaxed impedance matching constraint.

FIG. 5 is a circuit diagram illustrating in detail a first device 100 a according to an example embodiment.

Referring to FIG. 5 , the first device 100 a may include a transmission block 110 a and a monitor 120 a . The first device 100 a may correspond to the first device 100 a illustrated in FIG. 4A . The first device 100 a may correspond to an example of the first device 100 in FIG. 1 , and the transmission block 110 a and the monitor 120 a may correspond to examples of the transmitting block 110 and the monitor 120 in FIG. 1 , respectively. Descriptions given above with reference to FIGS. 1 through 4B may also be applied to the present example embodiment, and repeated descriptions are omitted. For example, the first device 100 a may be implemented as a 4-tap transmitter, as illustrated in FIG. 5 . However, the inventive concepts str not limited thereto, and a tap coefficient of the first device 100 a may be variously changed according to an example embodiment.

The transmission block 110 a may include a driver 111 , a data selector 112 , and a data buffer 113 . The data buffer 113 may include a first buffer 113 a for buffering even data D even and a second buffer 113 b for buffering odd data D odd . The first buffer 113 a may include first through third latches LC 1 through LC 3 . The first latch LC 1 may delay the even data D even according to an inverted signal of a clock signal CLK. The second latch LC 2 may delay an output of the first latch LC 1 according to the clock signal CLK. The third latch LC 3 may delay an output of the second latch LC 2 according to the inverted signal of the clock signal CLK. The second buffer 113 b may be implemented similarly to the first buffer 113 a.

The data selector 112 may include a first data selector 112 a generating a positive data signal D n and a second data selector 112 b generating a negative data signal D n . The first data selector 112 a may include first multiplexers (MUXs) 1121 and second MUXs 1122 . The first MUX 1121 may selectively output the even data D even and the odd data D odd according to the clock signal CLK and may operate as a data serializer. The second MUX 1122 may select 1, 0, or the output of the first MUX 1121 according to a selection signal Sel. The second data selector 112 b may be implemented similarly to the first data selector 112 a.

The driver 111 may include a first variable transmission resistor R TXL connected between a power voltage terminal V DD and the first output node ND 1 , a second variable transmission resistor R TXR connected between the power voltage terminal V DD and the second output node ND 2 , a first transistor TR 1 including a gate to which the negative data signal D n is applied and connected to the first output node ND 1 , a second transistor TR 2 including a gate to which the positive data signal D n is applied and connected to the second output node ND 2 , and the first current generator CG 1 connected to the first and second transistors TR 1 and TR 2 . The first current generator CG 1 may provide the first current I a to the first and second transistors TR 1 and TR 2 in the training mode for detecting the transmission impedance R TX .

The monitor 120 a may include a slicer 121 , a snapshot block (SNAPSHOT) 122 , and a finite state machine (FSM) 123 . The slicer 121 may receive a first voltage level V TXP of the first output node ND 1 and a second voltage level V TXN of the second output node ND 2 , and may output a digital voltage V OUTp by converting the first voltage level V TXP and the second voltage level V TXN of the second output node ND 2 into digital bits. The slicer 121 may receive a delayed clock signal CLK′ and operate according to the delayed clock signal CLK′. In an example embodiment, the delayed clock signal CLK′ and the clock signal CLK may be signals having substantially the same phase. The slicer 121 may further receive an adjustment current I th and correct an offset of the slicer 121 based on the adjustment current Ith.

The SNAPSHOT 122 may receive the digital voltage V OUTp from the slicer 121 and generate a snapshot signal SN of m bits from the digital voltage V OUTp , wherein m is an integer equal to or greater than 2. The SNAPSHOT 122 may include m delay blocks DB, and each delay block DB may include a multiplexer MX and a flip-flop FF. The flip-flop FF may receive the delayed clock signal CKL′. In addition, the SNAPSHOT 122 may further receive an enable signal EN and when the enable signal EN is activated, may generate the snapshot signal SN of m bits. For example, when the enable signal EN is activated, that is, logic high, an output of the slicer 121 may be sequentially provided to the m delay blocks DB, and accordingly, the snapshot signal SN of m bits may be generated. For example, when the enable signal EN is inactivated, that is, logic low, each delay block DB may hold data and the data held in each delay block DB may not be transmitted to the next delay block DB.

The FSM 123 may detect the channel impedance Z 0 and the receiving impedance R RX based on the snapshot signal SN of m bits and may calculate transmission impedance R TX based on the detected channel impedance Z 0 and receiving impedance R RX . In addition, the FSM 123 may configure resistance values of the first and second variable transmission resistors R TXL and R TXR according to the calculated transmission impedance R TX .

FIG. 6 is a circuit diagram illustrating the first variable transmission resistor R TXL according to an example embodiment.

Referring to FIG. 6 , the first variable transmission resistor R TXL may include a plurality of resistors R connected in common to the first output node ND 1 . The first variable transmission resistor R TXL may further include zeroth through k th switches SW 0 through SWk connected in common to the power voltage terminal VDD and in series to each other, wherein k is an arbitrary natural number. The second variable transmission resistance R TXR may be implemented substantially similar to the first variable transmission resistance R TXL .

The zeroth through k th switches SW 0 through SWk may be turned on/off in response to corresponding zeroth through k th selection signals Sel R0 through Sel Rk , respectively, so that the resistance value of the first variable transmission resistor R TXL may be determined. In an example embodiment, the FSM 123 may detect the channel impedance Z 0 and the receiving impedance R RX , calculate the transmission impedance R TX based on the detected channel impedance Z 0 and receiving impedance R RX , and generate the zeroth through k th selection signals Sel R0 through Sel Rk according to the calculated transmission impedance R TX .

FIG. 7A is a circuit diagram illustrating the slicer 121 according to an example embodiment.

Referring to FIG. 7A , the slicer 121 may include a pre-amplifier 1211 , an offset corrector 1212 , and a comparator 1213 . The pre-amplifier 1211 may include a first resistor R 11 and a second resistor R 12 , a first transistor TR 11 and a second transistor TR 12 , and an amplifier current generator CGa. The first resistor R 11 may be connected between the power voltage terminal V DD and a first node ND 11 , and the second resistor R 12 may be connected between the power voltage terminal V DD and a second node ND 12 .

The first transistor TR 11 may be connected in series to the first resistor R 11 and may include a gate to which the first voltage level V TXP of the first output node ND 1 is applied. The second transistor TR 12 may be connected in series to the second resistor R 12 and may include a gate to which the second voltage level V TXN of the second output node ND 2 is applied. The amplifier current generator CGa may be connected between the first and second transistors TR 11 and TR 12 and the ground voltage terminal and may provide an amplifier current I amp to the first and second transistors TR 11 and TR 12 . A first input voltage V Inn of the first node ND 11 may be determined according to the first voltage level V TXP of the first output node ND 1 , and a second input voltage V Inp of the second node ND 12 may be determined according to the second voltage level V TXN of the second output node ND 2 .

FIG. 7B is a circuit diagram illustrating the amplifier current generator CGa in FIG. 7A .

Referring to FIG. 7B , the amplifier current generator CGa may include a transistor TR and a switch SW. The transistor TR may be arranged between the first and second transistors TR 11 and TR 12 and the ground voltage terminal. A first terminal T 1 of the switch SW may be connected to a bias voltage terminal Vb, and a second terminal T 2 thereof may be connected to a gate of the transistor TR. The switch SW may be turned on/off according to an end signal END and accordingly, may control a voltage applied to the gate of the transistor TR.

In an example embodiment, when the end signal END is activated, the switch SW may be connected to the ground voltage terminal, and the transistor TR may be turned off. On the other hand, when the end signal END is inactivated, the switch SW may be connected to the bias voltage terminal Vb and the transistor TR may be turned on. The end signal END may be activated when configuration of the transmission impedance R TX is completed. In other words, the end signal END may be deactivated in the training mode and be activated in a normal mode. Accordingly, when the training mode is terminated, the amplifier current generator CGa may not additionally consume power.

Referring again to FIG. 7A , the offset corrector 1212 may include a third transistor TR 21 and a fourth transistor TR 22 , and an adjustment current generator CGb. The third transistor TR 21 may be connected to the first node ND 11 and may include a gate to which a first selection voltage Sel n is applied. The fourth transistor TR 22 may be connected to the second node ND 12 and may include a gate to which the second selection voltage Sel p is applied. The adjustment current generator CGb may be connected between the third and fourth transistors TR 21 and TR 22 and the ground voltage terminal and may provide the adjustment current I th to the third and fourth transistors TR 21 and TR 22 . The adjustment current generator CGb may vary the adjustment current I th so that the first input voltage V Inn and the second input voltage V Inp have the same level. The adjustment current generator CGb may be implemented similarly to the amplifier current generator CGa and may be implemented, for example, as illustrated in FIG. 7B .

The comparator 1213 may generate the digital voltage V OUTp by comparing the first input voltage V Inn with the second input voltage V Inp based on the delayed clock signal CLK′. Detailed configuration and operation of the comparator 1213 are described with reference to FIG. 8 .

FIG. 8 is a circuit diagram illustrating the comparator 1213 in FIG. 7A .

Referring to FIG. 8 , the comparator 1213 may include a sense amplifier 1213 a and a latch unit 1213 b . In addition, the comparator 1213 may further include a clock gating circuit 1213 c . The sense amplifier 1213 a may generate a first sensing voltage V SSp and a second sensing voltage V SSn from the first input voltage V Inp and the second input voltage V Inp , respectively. The latch unit 1213 b may generate the digital voltage V OUTp from the first sensing voltage V SSp and the second sensing voltage V SSn . The clock gating circuit 1213 c may be implemented with an AND gate receiving the delayed clock signal CLK′ and the end signal END. In an example embodiment, when the end signal END is activated, the delay clock signal CLK′ may not be provided to the sense amplifier 1213 a , and accordingly, the sense amplifier 1213 a may be turned off. Accordingly, when the training mode is terminated, the comparator 1213 may not additionally consume power.

FIG. 9 is a circuit diagram illustrating a first device 100 b according to an example embodiment.

Referring to FIG. 9 , the first device 100 b may include a driver 111 a , the data selector 112 , and a monitor 120 a . Some components of the first device 100 a illustrated in FIG. 5 are briefly illustrated to explain training operations of the first device 100 b in FIGS. 11 a through 17 b . Thus, descriptions given above with reference to FIGS. 5 through 8 may also be applied to the present example embodiment. For convenience of explanation, one of the plurality of drivers 111 illustrated in FIG. 5 , one of the plurality of second MUXs 1122 included in the first data selector 112 a , and one of the plurality of second MUXs 1122 included in the second data selector 112 b are illustrated.

The driver 111 a may include the first variable transmission resistor R TXL connected between the power voltage terminal V DD and the first output node ND 1 , the second variable transmission resistor R TXR connected between the power voltage terminal V DD and the second output node ND 2 , a first switch SWa 1 driven according to the negative data signal D 0 , a second switch SWa 2 driven according to the positive data signal D 0 , and the first current generator CG 1 connected to the first and second switches SWa 1 and SWa 2 and providing the first current I a . The first and second switches SWa 1 and SWa 2 may correspond to the first and second transistors TR 1 and TR 2 in FIG. 5 , respectively.

The data selector 112 may include a first MUX MX 1 and a second MUX MX 2 , a third switch SWb 1 and a fourth switch SWb 2 , and a second current generator CG 2 connected to the third and fourth switches SWb 1 and SWb 2 and providing a second current I b . The first MUX MX 1 may receive a positive previous data signal D −1 , 1 , and 0 , and may output a first selection signal in response to the selection signal Sel. The second MUX MX 2 may receive a negative previous data signal D −1 , 1 , and 0 , and may output a second selection signal in response to the selection signal Sel. The third switch SWb 1 may be driven according to the first selection signal to provide the second current I b to the first output node ND 1 . The fourth switch SWb 2 may be driven according to the second selection signal to provide the second current I b to the second output node ND 2 .

FIG. 10 is a flowchart of a method of configuring the transmission impedance R TX according to an e example embodiment.

Referring to FIG. 10 , the method of configuring the transmission impedance R TX according to the present example embodiment may be performed in a transmitter, for example, the first device 100 in FIG. 1 or the first device 100 b in FIG. 9 . Here, the channel 300 may be a direct current (DC) coupled channel. For example, the channel 300 may be a quick path interconnect (QPI) or the like. Hereinafter, descriptions are given with reference to FIGS. 9 and 10 . The first device 100 b may sequentially perform operations S 110 through S 160 in the training mode. The training mode may correspond to a time interval for configuring the transmission impedance R TX adaptively to the channel impedance Z 0 and the receiving impedance R RX . When the training mode is completed, the first device 100 b may transmit a normal data signal to the second device 200 in the normal mode.

The first device 100 b may detect the receiving impedance R RX (S 110 ). For example, the first device 100 b may configure the first current I a , the first variable transmission resistor R TXL , and the second variable transmission resistor R TXR , and may vary the second current I b to obtain the second current I b that makes the first voltage level V TXP equal to the second voltage level V TXN and to detect the receiving impedance R RX based on the obtained second current I b . Descriptions of operation S 110 will be given in detail with reference to FIGS. 11A through 12B .

The first device 100 b may detect a flight time t f (S 120 ). For example, the first device 100 b may configure the first current I a , the first variable transmission resistor R TXL , and the second variable transmission resistor R TXR , apply a single pulse signal to the positive data signal D 0 and the negative data signal D 0 , and monitor a reflection amount of the single pulse signal. Next, the first device 100 b may vary the second current I b to detect a time point at which a signal reflected from the second device 200 is input to the first device 100 b , and accordingly, may detect the flight time t f . Descriptions of operation S 120 will be given in detail with reference to FIGS. 13A through 13C .

The first device 100 b may determine whether the flight time t f has been detected (S 130 ). When it is determined that the flight time t f has not been detected, the first device 100 b may determine that the impedance matching constraint is satisfied, configure the transmission impedance R TX to the maximum value, and end the training mode. For example, when an amount of reflection in the second device 200 is little or a length of the channel 300 is short, the flight time t f may not be detected. By configuring the transmission impedance R TX to the maximum value thereof, the first device 100 b may increase a magnitude of the signal transmitted to the second device 200 .

On the other hand, when it is determined that the flight time t f has been detected, operation S 140 may be performed. The first device 100 b may detect the channel impedance Z 0 based on the flight time t f (S 140 ). For example, the first device 100 b may configure the first current I a , the first variable transmission resistor R TXL , and the second variable transmission resistor R TXR , and apply a step pulse signal to the positive data signal D 0 and the negative data signal D 0 . Subsequently, the first device 100 b may vary the second current I b to obtain a value of the second current I b which equalizes the first voltage level V TXP and the second voltage level V TXN within the time interval corresponding to twice the flight time t f , and may detect the channel impedance Z 0 based on the obtained second current I b . Descriptions of operation S 140 will be given in detail with reference to FIGS. 14A through 14C .

The first device 100 b may calculate the transmission impedance R TX by applying the detected receiving impedance R RX and channel impedance Z 0 to the relaxed impedance matching constraint (that is, Formula 4) (S 150 ). The first device 100 b may configure impedance of the transmitting block 110 to the transmission impedance R TX (S 160 ). For example, the monitor 120 may generate selected signals (for example, the zeroth through k th selection signals Sel R0 through Sel Rk in FIG. 6 ) according to the calculated transmission impedance R TX such that the first and second transmission resistors R TXL and R TXR have the value of the transmission impedance R TX .

FIGS. 11A through 12B illustrate a receiving impedance R RX detection operation according to operation S 110 in FIG. 10 .

FIG. 11A illustrates a first current path CP 1 for detecting the receiving impedance R RX in the training mode, and FIG. 11B illustrates the first voltage level V TXP , the second voltage level V TXN , and the snapshot signal SN when a system 10 b has the first current path CP 1 in FIG. 11A . In addition, FIG. 12A illustrates a second current path CP 2 for detecting the receiving impedance R RX in the training mode, and FIG. 12B illustrates the first voltage level V TXP , the second voltage level V TXN , and the snapshot signal SN when the system 10 b has the second current path CP 2 in FIG. 12A . The system 10 b may have the first current path CP 1 in FIG. 11A and the second current path CP 2 in FIG. 12A in sequence. After the snapshot signal SN in FIG. 11B has been generated, the system 10 b may have the second current path CP 2 in FIG. 12A , and accordingly, the first device 100 b may generate the snapshot signal SN in FIG. 12B . Hereinafter, descriptions are given with reference to FIGS. 9 through 12B .

Firstly, the first current I a may be configured to a fixed value, and the first and second variable transmission resistors R TXL and R TXR may be configured to have different resistance values from each other. For example, the resistance value of the first variable transmission resistance R TXL may be configured to R TXL1 , the resistance value of the second variable transmission resistance R TXR may be configured to R TXR1 , and the current amount of the first current I a may be configured to I a1 , wherein R TXL1 is not equal to R TXR1 . At this time, the first switch SWa 1 may be turned on and the first current I a may be supplied to the channel 300 via the first output node ND 1 . On the other hand, the second switch SWa 2 may be turned off, and the first current I a may not be supplied to the second output node ND 2 . Thus, the second voltage level V TXN of the second output node ND 2 may correspond to the power voltage terminal V DD , and the first voltage level V TXP of the first output node ND 1 may be less than a voltage of the power voltage terminal V DD . In this case, the snapshot signal SN captured in the SNAPSHOT 122 may be 0000 . . . , as illustrated in FIG. 11B , and accordingly, an average of bits of the snapshot signal SN may be almost 0.

Next, the fourth switch SWb 2 may be turned on, and the second current I b may be provided to the second output node ND 2 . As the second current I b is increased, the second voltage level V TXN of the second output node ND 2 may decrease. The FSM 123 may sense a time point at which the second voltage level V TXN becomes equal to the first voltage level V TXP based on the snapshot signal SN, and may detect a current amount of the second current I b . The FSM 123 may determine that the second voltage level V TXN becomes equal to the first voltage level V TXP at a time point at which the average of bits of the snapshot signal SN is about 0.5. The first voltage level V TXP and the second voltage level V TXN may be expressed by Formula 7 and Formula 8, respectively.

The receiving impedance R RX may be detected by substituting current amounts of the second current I b detected in the first variable transmission resistor R TXL , the second variable transmission resistor R TXR , the power voltage terminal V DD , the first current I a , and the FSM 123 into Formulas 7 and 8. The operations illustrated in FIGS. 11A through 12B may be repeatedly performed, wherein the resistance values of the first and second variable transmission resistors R TXL and R TXR may be changed. For example, it may be configured that the resistance value of the first variable transmission resistor R TXL is R TXL2 , the resistance value of the second variable transmission resistor R TXR is R TXR2 , the current amount of the first current I a is I a2 , wherein R TXL2 is not equal to R TXR2 . The system 10 b may again have the first and second current paths CP 1 , CP 2 illustrated in FIGS. 11A and 12A in sequence. At this time, the receiving impedance R RX may be detected by applying the current amount of the obtained second current I b to Formulas 7 and 8.

FIGS. 13A through 13C illustrate the flight time to detection operation according to operation S 120 in FIG. 10 .

Referring to FIG. 13A , in the training mode, the resistance values of the first variable transmission resistor R TXL and the second variable transmission resistor R TXR may be configured to the same value, and a single pulse signal having a pulse width of three times a unit interval UI may be applied to the positive data signal D 0 and, the negative data signal D 0 . At this time, the unit interval UI may correspond to a single time slot. The pulse width of the single pulse signal may not be limited to three times the unit interval UI, but may be configured to an arbitrary interval that is at least twice the unit interval UI. A bit of the snapshot signal SN may be 1 in an interval where the first voltage level V TXP is greater than the second voltage level V TXN , and the bit of the snapshot signal SN may be 0 in an interval where the first voltage level V TXP is less than the second voltage level V TXN .

When the receiving impedance R RX is greater than the channel impedance Z 0 , an overshooting may occur in the first voltage level V TXP at a time point at which the transmission signal reaches the first device 100 b after having been reflected at the second device 200 . On the other hand, when the receiving impedance R RX is less than the channel impedance Z 0 , an undershooting may occur in the first voltage level V TXP at the time point at which the transmission signal reaches the first device 100 b after having been reflected at the second device 200 . In addition, when the receiving impedance R RX is greater than the channel impedance Z 0 , the undershooting may occur in the second voltage level V TXN at the time at which the transmission signal reaches the first device 100 b after having been reflected at the second device 200 . On the other hand, when the receiving impedance R RX is less than the channel impedance Z 0 , the overshooting may occur in the second voltage level V TXN at the time point at which the transmission signal reaches the first device 100 b after having been reflected at the second device 200 .

Referring to FIG. 13B , the fourth switch SWb 2 may be turned on and the second current I b may be supplied to the second output node ND 2 . At this time, while the second current Ib is increased, the second voltage level V TXN may decrease. According to the present example embodiment, a 010 pattern 131 may be obtained in the snapshot signal SN while the second current Ib is increased. When the 010 pattern 131 is obtained in the snapshot signal SN, a time duration from a time point at which the signal has been transmitted in the first device 100 b to the time slot corresponding to a bit of 1 may correspond to 2*t f which is twice the flight time t f (for example, 2*t f =10). On the other hand, when the 010 pattern is not obtained in the snapshot signal SN, the second current I b may be reduced.

Referring to FIG. 13C , the fourth switch SWb 2 may be turned on and the second current I b may be supplied to the second output node ND 2 . At this time, as the second current I b is reduced, the second voltage level V TXN may increase. According to the present example embodiment, a 101 pattern 132 may be obtained in the snapshot signal SN as the second current I b is decreased. When the 101 pattern 132 is obtained in the snapshot signal SN, a time duration from a time point at which the signal has been transmitted in the first device 100 b to the time slot corresponding to a bit of 1 may correspond to 2*t f which is twice the flight time t f (for example, 2*t f =10). When both the 010 pattern and the 101 pattern are not obtained in the snapshot signal SN, it may be determined that an impedance matching has been performed (in other words, R RX is almost the same as Z 0 ). At this time, the transmission impedance R TX may be configured to the maximum value, and the training mode may be ended and an impedance adaptation process may be ended.

FIGS. 14A through 14C illustrate the channel impedance Z 0 detection operation according to operation S 140 in FIG. 11 .

Referring to FIG. 14A , in the training mode, the resistance values of the first variable transmission resistor R TXL and the second variable transmission resistor R TXR may be configured to the same value, and a unit step pulse signal may be applied to the positive data signal D 0 and the negative data signal D 0 . At this time, the snapshot signal SN may be as illustrated in FIG. 14A . The channel impedance Z 0 may be calculated by using a characteristic that a magnitude of a voltage input to the channel 300 is determined by the channel impedance Z 0 and the transmission impedance R TX . When the magnitude of the channel impedance Z 0 is greater than a value of R TX R RX /(2R TX +R RX ), the first voltage level V TXP may be greater than the second voltage level V TXN around the flight time t f , and accordingly, a bit average of the snapshot signal SN may be about 1 around the flight time t f .

When the receiving impedance R RX is greater than the channel impedance Z 0 , the first voltage level V TXP may increase at the time point at which the transmission signal reaches the first device 100 b after having been reflected at the second device 200 . On the other hand, when the receiving impedance R RX is less than the channel impedance Z 0 , the first voltage level V TXP may decrease at the time point at which the transmission signal reaches the first device 100 b after having been reflected at the second device 200 . In addition, when the receiving impedance R RX is greater than the channel impedance Z 0 , the second voltage level V TXN may decrease at the time point at which the transmission signal reaches the first device 100 b after having been reflected at the second device 200 . On the other hand, when the receiving impedance R RX is less than the channel impedance Z 0 , the second voltage level V TXN may increase at the time point at which the transmission signal reaches the first device 100 b after having been reflected at the second device 200 .

Referring to FIG. 14B , the third switch SWb 1 may be turned on and the second current I b may be provided to the first output node ND 1 . At this time, while the second current I b is increased, the first voltage level V TXP may decrease. According to the present example embodiment, the current amount of the second current I b which causes the first voltage level V TXP and the second voltage level V TXN to be equal around the flight time t f may be detected by increasing the second current I b . For example, a 1010 pattern 141 with the bit average of about 0.5 in the snapshot signal SN may be obtained while the second current Ib is increased.

The FSM 123 may sense the time point at which the second voltage level V TXN becomes equal to the first voltage level V TXP based on the snapshot signal SN, and may detect a current amount of the second current I b . When the bit average of the snapshot signal SN is about 0.5, that is, when the 1010 pattern 141 is obtained, the FSM 123 may determine that the second voltage level V TXN is equal to the first voltage level V TXP . At this time, the channel impedance Z 0 may be calculated by using Formula 9 below.

Referring to FIG. 14C , when the magnitude of the channel impedance Z 0 is less than R TX R RX /(2R TX +R RX ), the first voltage level V TXP may be less than the second voltage level V TXN around the flight time t f , and accordingly, the second current I b may not be detected. According to the present example embodiment, the fourth switch SWb 2 may be turned on and the second current I b may be provided to the second output node ND 2 . At this time, while the second current Ib is increased, the second voltage level V TXN may decrease. According to the present example embodiment, the current amount of the second current Ib which causes the first voltage level V TXP and the second voltage level V TXN to be equal around the flight time t f may be detected. For example, a 0101 pattern 142 with the bit average of about 0.5 in the snapshot signal SN may be obtained while the second current Ib is increased.

The FSM 123 may sense the time point at which the second voltage level V TXN becomes equal to the first voltage level V TXP based on the snapshot signal SN, and may find the current amount of the second current I b . When the bit average of the snapshot signal SN is about 0.5, that is, when the 0101 pattern 142 is obtained, the FSM 123 may determine that the second voltage level V TXN is equal to the first voltage level V TXP . At this time, the channel impedance Z 0 may be calculated by using Formula 10 below.

The FSM 123 may calculate the transmission impedance R TX by applying the detected receiving impedance R RX and channel impedance Z 0 to the relaxed impedance matching constraint (that is, Formula 4). Next, the FSM 123 may configure resistance values of the first and second variable transmit resistors R TXL and R TXR to the transmission impedance R TX . Thereby, the training mode may be ended and the impedance adaptation process may be ended.

FIG. 15 is a flowchart of a method of configuring the transmission impedance R TX according to an example embodiment.

Referring to FIG. 15 , the method of configuring the transmission impedance R TX according to the present example embodiment may be performed in a transmitter, for example, the first device 100 in FIG. 1 or the first device 100 b in FIG. 9 . At this time, the channel 300 may be an alternating current (AC) coupled channel. For example, the channel 300 may be universal serial bus (USB), serial advanced technology attachment (ATA) (SATA), high-definition multimedia interface (HDMI), peripheral component interconnect express (PCIe), a backplane, etc. Hereinafter, descriptions are given with reference to FIGS. 9 and 15 . The first device 100 b may sequentially perform operations S 210 through S 260 in the training mode. In the case where the channel 300 is an AC coupled channel, since a DC component is blocked, the receiving impedance R RX may not be detected in a manner illustrated in FIGS. 11A through 12B . Accordingly, when the channel 300 is the AC coupled channel, a sequence of the operations included in a transmission impedance R TX configuration method may be different from that illustrated in FIG. 10 .

The first device 100 b may detect a flight time t f (S 210 ). For example, the first device 100 b may configure the first current I a , the first variable transmission resistor R TXL , and the second variable transmission resistor R TXR , and may apply the single pulse signal to the positive data signal D 0 and the negative data signal D 0 . Next, the first device 100 b may vary the second current I b to detect a time point at which a signal reflected from the second device 200 is input to the first device 100 b , and accordingly, may detect the flight time t f . Operation S 210 may be performed similarly to an example embodiment illustrated in FIGS. 13A through 13C .

The first device 100 b may determine whether the flight time t f has been detected (S 220 ). When it is determined that the flight time t f has not been detected, the first device 100 b may determine that the impedance matching constraint is satisfied, and configure the transmission impedance R TX to the maximum value (S 260 ), and end the training mode. For example, when the amount of reflection in the second device 200 is little or the length of the channel 300 is short, the flight time t f may not be detected. By configuring the transmission impedance R TX to the maximum value thereof, the first device 100 b may increase a magnitude of the signal transmitted to the second device 200 .

On the other hand, when it is determined that the flight time t f has been detected, an operation S 230 may be performed. The first device 100 b may detect the channel impedance Z 0 based on the flight time t f (S 230 ). For example, the first device 100 b may configure the first current I a , the first variable transmission resistor R TXL , and the second variable transmission resistor R TXR , and may apply the step pulse signal to the positive data signal D 0 and the negative data signal D 0 . Subsequently, the first device 100 b may vary the second current I b to obtain the value of the second current I b which equalizes the first voltage level V TXP and the second voltage level V TXN within the time interval corresponding to twice the flight time t f , and may detect the channel impedance Z 0 based on the obtained second current I b . Descriptions of operation S 230 will be given in detail with reference to FIGS. 16A and 16B .

The first device 100 b may detect the receiving impedance R RX (S 240 ). For example, the first device 100 b may configure the first current I a , the first variable transmission resistor R TXL , and the second variable transmission resistor R TXR , and may vary the second current I b to obtain the second current I b that makes the first voltage level V TXP equal to the second voltage level V TXN , and to detect the receiving impedance R RX based on the obtained second current Ib. Descriptions of operation S 240 will be given in detail with reference to FIGS. 17A and 17B .

The first device 100 b may calculate the transmission impedance R TX by applying the detected receiving impedance R RX and channel impedance Z 0 to the relaxed impedance matching constraint (S 250 ). The first device 100 b may configure impedance of the transmitting block 110 to the transmission impedance R TX (S 260 ). For example, the monitor 120 may generate selected signals (for example, the zeroth through k th selection signals Sel R0 through Sel Rk in FIG. 6 ) according to the calculated transmission impedance R TX such that the first and second transmission resistors R TXL and R TXR have the value of the transmission impedance R TX .

FIGS. 16A and 16B illustrate the channel impedance Z 0 detection operation according to operation S 230 in FIG. 15 .

Referring to FIG. 16A , in the training mode, the resistance values of the first variable transmission resistor R TXL and the second variable transmission resistor R TXR may be configured to the same value, and the unit step pulse signal may be applied to the positive data signal D 0 and the negative data signal D 0 . When the channel impedance Z 0 is equal to or greater than the transmission impedance R TX , the first voltage level V TXP may be greater than the second voltage level V TXN around the flight time t f .

According to the present example embodiment, the third switch SWb 1 may be turned on and the second current I b may be provided to the first output node ND 1 . At this time, the time point at which the first voltage level V TXP and the second voltage level V TXN become equal to each other around the flight time t f while the second current Ib is increased may be detected, and the current amount of the second current I b at the time point may be obtained. At this time, the channel impedance Z 0 may be calculated by using Formula 11 below.

Referring to FIG. 16B , in the training mode, the resistance values of the first variable transmission resistor R TXL and the second variable transmission resistor R TXR may be configured to the same value, and the unit step pulse signal may be applied to the positive data signal D 0 and the negative data signal D 0 . When the channel impedance Z 0 is equal to or less than the transmission impedance R TX , the second voltage level V TXN may be greater than the first voltage level V TXP around the flight time t f .

According to the present example embodiment, the second current I b may be provided to the second output node ND 2 by turning on the fourth switch SWb 2 . At this time, the time point at which the first voltage level V TXP and the second voltage level V TXN become equal to each other around the flight time t f while the second current I b is increased may be detected, and the current amount of the second current I b at the time point may be obtained. At this time, the channel impedance Z 0 may be calculated by using Formula 12 below.

FIGS. 17A and 17B illustrate the receiving impedance R RX detection operation according to operation S 240 in FIG. 15 .

Referring to FIG. 17A , in the training mode, the resistance values of the first variable transmission resistor R TXL and the second variable transmission resistor R TXR may be configured to the same value, and the unit step pulse signal may be applied to the positive data signal D 0 and the negative data signal D 0 . When the receiving impedance R RX is equal to or greater than the transmission impedance R TX , the first voltage level V TXP may be greater than the second voltage level V TXN around the flight time t f .

According to the present example embodiment, the second current I b may be provided to the first output node ND 1 by turning on the third switch SWb 1 . At this time, a time point at which the first voltage level V TXP and the second voltage level V TXN become equal to each other around a time point (2N−1)t f (N is a natural number) while the second current I b is increased may be detected, and when the time point at which the first voltage level V TXP and the second voltage level V TXN become equal to each other is detected, the current amount of the second current I b at the time point above may be detected. At this time, the receiving impedance R RX may be calculated by using Formula 13 below.

Referring to FIG. 17B , in the training mode, the resistance values of the first variable transmission resistor R TXL and the second variable transmission resistor R TXR may be configured to the same value, and the unit step pulse signal may be applied to the positive data signal D 0 and the negative data signal D 0 . When the receiving impedance R RX is equal to or less than the transmission impedance R TX , the second voltage level V TXN may be greater than the first voltage level V TXP around the flight time t f .

According to the present example embodiment, the second current I b may be provided to the second output node ND 2 by turning on the fourth switch SWb 2 . At this time, the time point at which the first voltage level V TXP and the second voltage level V TXN become equal to each other around the time point (2N−1)t f (N is a natural number) while the second current I b is increased may be detected, and the current amount of the second current I b at the time point above may be obtained. At this time, the receiving impedance R RX may be calculated by using Formula 14 below.

Next, the FSM 123 may calculate the transmission impedance R TX by applying the detected receiving impedance R RX and channel impedance Z 0 to the relaxed impedance matching constraint (that is, Formula 4). Next, the FSM 123 may configure resistance values of the first and second variable transmit resistors R TXL and R TXR to the transmission impedance R TX . Thereby, the training mode may be ended and the impedance adaptation process may be ended.

FIG. 18 illustrates a system 20 according to an example embodiment.

Referring to FIG. 18 , the system 20 may include the first device 100 , a second device 200 a , and the channel 300 . The first device 100 and the second device 200 a may be connected to each other via the channel 300 . The system 20 according to the present example embodiment may correspond to a modified embodiment of the system 10 of FIG. 1 , and the descriptions given above with reference to FIGS. 1 through 17B may also be applied to the present example embodiment.

The second device 200 a may include the receiving block 210 and the monitor 220 . The monitor 220 may detect the channel impedance Z 0 and the transmission impedance R TX by monitoring a voltage level of a first input node ND 3 and a voltage level of a second input node ND 4 , and may configure the receiving impedance R RX based on the transmission impedance Z 0 and the transmission impedance R TX . The monitor 220 may calculate the receiving impedance R RX according to the relaxed impedance matching constraint and configure the receiving impedance R RX of the receiving block 210 according to the calculated receiving impedance R RX . In an example embodiment, the monitor 220 may be implemented as an eye monitoring circuit. In an example embodiment, the receiving block 210 and the monitor 220 may be implemented on the same chip.

As described above, embodiments have been disclosed in the drawings and specification. While the embodiments have been described herein with reference to specific terms, it should be understood that they have been used only for the purpose of describing the inventive concepts and not for limiting the scope of the inventive concepts as defined in the claims. Therefore, one with ordinary skill in the art will appreciate that various modifications and equivalent example embodiments are possible without departing from the scope of the inventive concepts. Therefore, the true scope of protection of the inventive concepts should be determined by the technical idea of the appended claims.