Control circuit with bypass function

This application claims priority to Taiwan Patent Application No. 107131987, filed Sep. 12, 2018, and incorporated herein by reference in its entirety.

The present invention relates to a control circuit, and more particularly, a control circuit with a bypass function and having a bypass path for bypassing a signal.

In a front-end module receiver circuit for supporting multiple frequency bands, a plurality of input terminals can be set respectively corresponding to the multiple frequency bands. For example, in a single pole multiple throw (SPMT) radio-frequency switch circuit, every input terminal can receive a signal, and the signal can be transmitted through a matching component and a set of switches, enter a node, and then be outputted. The foresaid node can be coupled to a function path and a bypass path. If a switch of the function path is turned off, the circuit can enter a bypass mode for bypassing the signal through the bypass path. Although this sort of structure is feasible, many shortcomings have been observed in practice. For example, since switches and capacitors need to be set on the function path, the size of the circuit will be enlarged and can hardly be reduced. Moreover, since each of a plurality of paths having a plurality of switches connected in series are coupled to the node, the loading effect will be excessive, and this can be disadvantageous to the efficiency of the circuit. In the bypass mode, the loading effect will be particularly significant. Furthermore, the abovementioned structure will cause higher insertion loss (IL).

An embodiment provides a control circuit with a bypass function. The control circuit comprises a first signal terminal, a second signal, an output terminal, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a first output switch unit, and a first bypass unit. The first signal terminal is configured to receive a first signal. The second signal terminal is configured to receive a second signal. The output terminal is configured to output the first signal or the second signal. The first switch unit comprises a first terminal coupled to the first signal terminal, and a second terminal. The second switch unit comprises a first terminal coupled to the second terminal of the first switch unit, and a second terminal. The third switch unit comprises a first terminal coupled to the second signal terminal, and a second terminal. The fourth switch unit comprises a first terminal coupled to the second terminal of the third switch unit, and a second terminal coupled to the second terminal of the second switch unit. The first output switch unit comprises a first terminal coupled to the second terminal of the fourth switch unit, and a second terminal. The first bypass unit comprises a first terminal coupled to the second terminal of the first switch unit, and a second terminal coupled to the output terminal and the second terminal of the first output switch unit. The first bypass unit is configured to provide a first bypass path for bypassing the first signal.

Another embodiment provides a control circuit with a bypass function. The control circuit comprises a first signal terminal, a second signal terminal, an output terminal, a first switch unit, a second switch unit, a third switch unit, an output switch unit, and a bypass unit. The first signal terminal is configured to receive a first signal. The second signal terminal is configured to receive a second signal. The output terminal is configured to output the first signal or the second signal. The first switch unit comprises a first terminal coupled to the first signal terminal, and a second terminal. The second switch unit comprises a first terminal coupled to the second terminal of the first switch unit, and a second terminal. The third switch unit comprises a first terminal coupled to the second signal terminal, and a second terminal coupled to the second terminal of the second switch. The output switch unit comprises a first terminal coupled to the second terminal of the third switch unit, and a second terminal coupled to the output terminal. The bypass unit comprises a first terminal coupled to the second terminal of the first switch unit, and a second terminal coupled to the output terminal. The bypass unit is configured to provide a bypass path for bypassing the first signal.

FIG. 1 illustrates a control circuit with a bypass function according to an embodiment.

FIG. 2 illustrates the control circuit of FIG. 1 according to an embodiment.

FIG. 3 illustrates the bypass unit of the control circuit of FIG. 1 according to another embodiment.

FIG. 4 illustrates a control circuit with a bypass function according to an embodiment.

FIG. 5 illustrates a switch unit of the control circuit of FIG. 1 according to an embodiment.

FIG. 6 illustrates an application of a control circuit with a bypass function according to embodiment.

FIG. 7 illustrates an application of the control circuit according to another embodiment.

FIG. 8 illustrates a control circuit according to an embodiment.

FIG. 9 illustrates a capacitor equivalent structure of the circuit of FIG. 8 for qualitative analysis.

FIG. 10 illustrates a control circuit with a bypass function according to an embodiment.

Below, exemplary embodiments will be described in detail with reference to accompanying drawings so as to be easily realized by a person having ordinary knowledge in the art. The inventive concept may be embodied in various forms without being limited to the exemplary embodiments set forth herein. Descriptions of well-known parts are omitted for clarity, and like reference numerals refer to like elements throughout.

FIG. 1 illustrates a control circuit 100 with a bypass function according to an embodiment. The control circuit 100 may include a first signal terminal N 1 , a second signal N 2 , an output terminal N opt , switch units 110 , 120 , 130 and 140 , an output switch unit 150 , and a bypass unit 180 . The first signal terminal N 1 may be used to receive a first signal S 1 . The second signal terminal N 2 may be used to receive a second signal S 2 . The output terminal N opt may be used to output the first signal S 1 or the second signal S 2 . The switch unit 110 may include a first terminal and a second terminal where the first terminal is coupled to the first signal terminal N 1 . The switch unit 120 may include a first terminal and a second terminal where the first terminal is coupled to the second terminal of the switch unit 110 . The switch unit 130 may include a first terminal and a second terminal where the first terminal is coupled to the second signal terminal N 2 . The switch unit 140 may include a first terminal and a second terminal where the first terminal is coupled to the second terminal of the switch unit 130 , and the second terminal is coupled to the second terminal of the switch unit 120 . The output switch unit 150 may include a first terminal and a second terminal where the first terminal is coupled to the second terminal of the switch unit 140 . The bypass unit 180 may include a first terminal and a second terminal where the first terminal is coupled to the second terminal of the switch unit 110 , and the second terminal is coupled to the output terminal N opt and the second terminal of the output switch unit 150 . The bypass unit 180 may be used to provide a bypass path Ptb 1 for bypassing the first signal S 1 .

As shown in FIG. 1 , the switch unit 110 and the switch unit 120 form a first path Pt 1 , the switch unit 130 and the switch unit 140 form a second path Pt 2 , and the bypass unit 180 forms the first bypass path Ptb 1 .

In an operation mode of turning on the bypass path Ptb 1 , the switch unit 110 and the bypass unit 180 are turned on, and the switch unit 120 , the switch unit 130 , the switch unit 140 and the output switch unit 150 are turned off. Hence, the bypass path Ptb 1 is turned on, a path passing through the switch unit 120 and the second path Pt 2 are turned off, and the first signal S 1 is transmitted through the bypass path Ptb 1 and outputted from the output terminal N opt .

In an operation mode of turning on the first path Pt 1 , the switch unit 110 , the switch unit 120 and the output switch unit 150 are turned on, and the bypass unit 180 , the switch unit 130 and the switch unit 140 are turned off. Hence, the first path Pt 1 is turned on, the bypass path Ptb 1 and the second path Pt 2 are turned off, and the first signal S 1 is transmitted through the first path Pt 1 and outputted from the output terminal N opt .

In an operation mode of turning on the second path Pt 2 , the switch unit 130 , the switch unit 140 and the output switch unit 150 are turned on, and the switch unit 110 and the switch unit 120 and the bypass unit 180 are turned off. Hence, the second path Pt 2 is turned on, the bypass path Ptb 1 and the first path Pt 1 are turned off, and the second signal S 2 is transmitted through the second path Pt 2 and outputted from the output terminal N opt .

FIG. 2 illustrates the control circuit 100 of FIG. 1 according to an embodiment. The switch unit 110 may further include a control terminal used to receive a control signal V 1 . The switch unit 120 may further include a control terminal used to receive a control signal V 2 . The switch unit 130 may further include a control terminal used to receive a control signal V 3 . The switch unit 140 may further include a control terminal used to receive a control signal V 4 . The switch unit 130 and the switch unit 140 may be synchronously turned on or turned off. According to the embodiment, the control signal V 3 is equal to the control signal V 4 . The bypass unit 180 may further include a control terminal used to receive a control signal Va. The output switch unit 150 may further include a control terminal used to receive a control signal Vc. The abovementioned control terminals may be used to turn on or turn off the switch units 110 to 140 , the bypass unit 180 and the output switch unit 150 . The abovementioned control signals V 1 to V 4 , Va and Vc may be voltage signals.

According to an embodiment, the switch units 110 to 140 , the bypass unit 180 and the output switch unit 150 may respectively include transistors M 11 to M 16 . Wherein, a size of the transistor M 13 may be substantially equal to a size of the transistor M 14 . The size of the transistor M 14 may be not larger than (≤) a size of the transistor M 16 . A size of the transistor M 15 may be smaller than the size of the transistor M 14 . The size of the transistor M 15 may not be larger than the size of the transistor M 16 . The transistors described in the text or in the figures are merely illustrative, and each transistor described herein may include one transistor or be formed with a plurality of transistors coupled to one another. The mentioned size of a transistor may be corresponding to a length and a width of a channel of the transistor, and/or the number of channels (Also known as the number of fingers).

In FIG. 2 , each of the switch units 110 to 140 , the bypass unit 180 and the output switch unit 150 may include a single transistor. However, according to embodiments, it is also allowed to use another appropriate type of switch or a switch formed with a plurality of transistors coupled to one another in a cascode structure.

As shown in FIG. 2 , the bypass unit 180 may include the transistor M 15 . A first terminal, a second terminal and a control terminal of the transistor M 15 may be respectively coupled to the first terminal, the second terminal and the control terminal of the bypass unit 180 . FIG. 3 illustrates the bypass unit 180 of FIG. 1 according to another embodiment. The bypass unit 180 may include at least one capacitor (e.g. the capacitor C 31 and the capacitor C 32 ) and a transistor M 15 . The at least one capacitor of the bypass unit 180 may be coupled in series between the first terminal of the transistor M 15 and the first terminal of the bypass unit 180 (as the capacitor C 31 ) or between the second terminal of the transistor M 15 and the second terminal of the bypass unit 180 (as the capacitor C 32 ). The transistor M 15 of FIG. 2 and FIG. 3 may be replaced with a plurality of transistors coupled in a cascode structure, and control terminals of the plurality of transistors may be coupled to the control terminal of the bypass unit 180 .

FIG. 4 illustrates a control circuit 400 with a bypass function according to an embodiment. The switch units 110 to 140 , the output switch unit 150 and the bypass unit 180 of FIG. 4 may be similar to the structure of FIG. 1 . However, as shown in FIG. 4 , the control circuit 400 may further include a bypass unit 185 . The bypass unit 185 may include a first terminal, a second terminal and a control terminal where the first terminal is coupled to the second terminal of the switch unit 130 , and the second terminal is coupled to the output terminal N opt . The bypass unit 185 may be used to provide a bypass path Ptb 2 for bypassing the second signal S 2 .

Like the bypass unit 180 of FIG. 2 and FIG. 3 , the bypass unit 185 of FIG. 4 may include a single transistor including a first terminal, a second terminal and a control terminal respectively coupled to the first terminal, the second terminal and the control terminal of the bypass unit 185 . According to another embodiment, the bypass unit 185 may include a plurality of transistors coupled to one another in a cascode structure.

Furthermore, according to another embodiment, the bypass unit 185 may include at least one transistor and at least one capacitor. When the bypass unit 185 includes two or more transistors, the transistors may be coupled to one another in a cascode structure, and control terminals of the transistors may be coupled to the control terminal of the bypass unit 185 . The capacitors of the bypass unit 185 may be coupled in series between the transistor(s) of the bypass unit 185 and the first terminal of the bypass unit 185 and/or between the transistor(s) of the bypass unit 185 and the second terminal of the bypass unit 185 . Since the circuit structure may be similar to the structure of the abovementioned bypass unit 180 , it is not described repeatedly.

FIG. 5 illustrates a switch unit 510 according to an embodiment. The switch unit 510 may be any one of the switch units 110 to 140 and the output switch unit 150 . The switch unit 510 may include a plurality of switches coupled to one another in a cascode structure. When the switch unit 510 is turned on, the plurality of the switches of the switch unit 510 are turned on. Control terminals of the plurality of the switches of the switch unit 510 are coupled to a control terminal of the switch unit 510 . A first terminal of a first switch of the plurality of the switches of the switch unit 510 may be a first terminal of the switch unit 510 . A second terminal of a last switch of the plurality of the switches of the switch unit 510 may be a second terminal of the switch unit 510 . According to embodiments, the switch unit 510 may include at least one capacitor coupled in series among the plurality of switches, at a front terminal of the plurality of switches and/or at a back terminal of the plurality of switches.

FIG. 6 illustrates an application of a control circuit 600 with a bypass function according to embodiment. The control circuit 600 may include the components of the control circuit 100 of FIG. 1 or the control circuit 400 of FIG. 4 . The similar components are not described repeatedly. For example, compared with FIG. 4 , the control circuit 600 may further include a third signal terminal N 3 , a fourth signal terminal N 4 , switch units 210 , 220 , 230 and 240 , an output switch unit 250 and bypass units 280 and 285 . The third signal terminal N 3 may be used to receive a third signal S 3 . The fourth signal terminal N 4 may be used to receive a fourth signal S 4 . The switch unit 210 may include a first terminal and a second terminal where the first terminal is coupled to the third signal terminal N 3 . The switch unit 220 may include a first terminal and a second terminal where the first terminal is coupled to the second terminal of the switch unit 210 . The switch unit 230 may include a first terminal and a second terminal where the first terminal is coupled to the fourth signal terminal N 4 . The switch unit 240 may include a first terminal and a second terminal where the first terminal is coupled to the second terminal of the switch unit 230 , and the second terminal is coupled to the second terminal of the switch unit 220 . The output switch unit 250 may include a first terminal and a second terminal where the first terminal is coupled to the second terminal of the switch unit 240 , and the second terminal is coupled to the output terminal N opt . The bypass unit 280 may include a first terminal and a second terminal where the first terminal is coupled to the second terminal of the switch unit 210 , and the second terminal is coupled to the output terminal N opt . The switch units 210 and 220 may form a third path Pt 3 for transmitting the third signal S 3 . The bypass unit 280 is used to provide a bypass path Ptb 3 for bypassing the third signal S 3 . The switch units 230 and 240 may form a fourth path Pt 4 for transmitting the fourth signal S 4 . The bypass unit 285 is used to provide a bypass path Ptb 4 for bypassing the fourth signal S 4 . The output terminal N opt may be used to output the first signal S 1 , the second signal S 2 , the third signal S 3 or the fourth signal S 4 .

In FIG. 6 , the switch units 110 to 140 , the output switch unit 150 and the bypass units 180 and 185 used for receiving and transmitting the first signal S 1 and the second signal S 2 may be of a first set of components. The switch units 210 to 240 , the output switch unit 250 and the bypass units 280 and 285 used for receiving and transmitting the third signal S 3 and the fourth signal S 4 may be of a second set of components. In FIG. 6 , merely two sets of components are shown. However, according to embodiments, the output terminal N opt may further coupled to a third set of components and more sets of components for receiving and transmitting more signals.

As shown in FIG. 6 , the output terminal N opt may be coupled to an amplification path unit 610 and a bypass path unit 620 . The amplification path unit 610 may be further coupled to an amplifier circuit 615 , and the amplifier circuit 615 may be used to amplify a signal outputted by the output terminal N opt . The amplifier circuit 615 may include a low-noise amplifier or a power amplifier. In FIG. 6 , the amplifier circuit 615 is an amplifier with a transistor cascode structure as an example. The amplifier circuit 615 of FIG. 6 may include transistors M 61 and M 62 , inductors L 61 and L 62 , and a capacitor C 61 . The amplifier circuit 615 may be coupled to a power terminal Vdd through an inductor L 61 and to a reference voltage terminal Vss through an inductor L 62 . The circuit structure of the amplifier circuit 615 in FIG. 6 is merely an example instead of a limitation of the structure of the amplifier circuit 615 . The amplification path unit 610 may include an amplification path switch used to turn on or turn off the amplification path unit 610 . Furthermore, the amplification path unit 610 may include a capacitor coupled in a series structure and used for direct-current (DC) blocking. Furthermore, as shown in FIG. 6 , a first terminal of the transistor M 61 of the amplifier circuit 615 may be coupled to a first terminal of the transistor M 65 through a capacitor C 699 . A second terminal of the transistor M 65 may be coupled to an output terminal N out .

As shown in FIG. 6 , the bypass path unit 620 may be further coupled to the amplifier circuit 615 and a bypass circuit 625 . The bypass circuit 625 may be used to bypass a signal outputted by the output terminal N opt . The bypass path unit 620 may include at least one capacitor, be coupled to a control terminal of the transistor M 61 , and be used to adjust the input impedance matching of the amplifier circuit 615 . For example, the bypass path unit 620 may include (but is not limited to) a capacitor, and the capacitor has a first terminal coupled to the output terminal N opt and a second terminal coupled to the control terminal of the transistor M 61 and the bypass circuit 625 . Furthermore, the bypass circuit 625 may include a single switch or a plurality of switches coupled to one another in a cascode structure, and at least one capacitor coupled to the switch of the bypass circuit 625 in a series structure. For example, the bypass circuit 625 of FIG. 6 may include transistors M 63 and M 64 and capacitors C 62 and C 63 where the transistors M 63 and M 64 may be switches. As shown in FIG. 6 , the bypass circuit 625 may be coupled to the output terminal N out .

As shown in FIG. 6 , when a signal outputted by the output terminal N opt is amplified, the amplification path unit 610 may be turned on, the amplifier circuit 615 may be enabled, and the bypass circuit 625 may be turned off. Taking the circuit of FIG. 6 as an example, when a signal outputted by the output terminal N opt is amplified, a bias voltage Vbb 1 may be adjusted at the control terminal of the transistor M 61 to turn on the transistor M 61 . Furthermore, a bias voltage Vbb 2 may be adjusted and inputted to the amplification path unit 610 to turn on an amplification path switch of the amplification path unit 610 . In this condition, the output terminal N out may output a signal amplified by the amplifier circuit 615 . The described bias voltages Vbb 1 and Vbb 2 may be provided by a bias voltage circuit.

Taking the circuit of FIG. 6 as an example, when a signal outputted by the output terminal N opt is bypassed, the bias voltage Vbb 1 at the control terminal of the transistor M 61 may be adjusted to turn off the transistor M 61 and turn off the amplifier circuit 615 . Furthermore, the bias voltage Vbb 2 may be adjusted and inputted to the amplification path unit 610 to turnoff the amplification path switch of the amplification path unit 610 . In this condition, the output terminal N out may output a signal transmitted through the bypass circuit 625 .

FIG. 7 illustrates an application of the control circuit 600 according to another embodiment. As shown in FIG. 7 , the control circuit 600 , the amplifier circuit 615 and a bypass circuit 625 may be similar to what is illustrated in FIG. 6 , so these circuits are not described repeatedly. FIG. 7 is different from FIG. 6 in that the output terminal N opt may be coupled to a common path unit 710 , and the common path unit 710 may be further coupled to the amplifier circuit 615 and the bypass circuit 625 . As shown in FIG. 7 , the common path unit 710 may include a capacitor CB which may be a direct-current blocking capacitor. According to embodiments, the capacitor CB may be optionally used or not used. When a signal outputted by the output terminal N opt is amplified, a bias voltage Vbb provided by a bias voltage circuit may be adjusted to turn on the transistor M 61 and turn off the transistors M 63 and M 64 of the bypass circuit 625 . When a signal outputted by the output terminal N opt is bypassed, the bias voltage Vbb may be adjusted to turn off the transistor M 61 and turn on the transistors M 63 and M 64 of the bypass circuit 625 . According to an embodiment, the control terminals of the transistors M 63 , M 64 and M 65 shown in FIG. 6 and FIG. 7 may be respectively coupled to suitable resistors.

FIG. 8 illustrates a control circuit 800 according to an embodiment. The output terminal N opt of FIG. 8 may be corresponding to the output terminal N opt of FIG. 7 . In other words, the common path unit 710 of FIG. 7 may be coupled to the output terminal N opt of FIG. 8 . The control circuit 600 of FIG. 7 may be used to receive and transmit the first signal S 1 to the fourth signal S 4 . The control circuit 800 of FIG. 8 may be used to receive and transmit the first signal S 1 to the sixth signal S 6 , and the control circuits 600 and 800 may be operated on similar principle. Compared with FIG. 6 and FIG. 7 , the control circuit 800 of FIG. 8 illustrates more details of the circuit. FIG. 8 is merely an example instead of limiting the scope of embodiments. The control circuit 800 may include three sets of components. The first set of components may include the switch units 110 to 140 , the bypass units 180 and 185 , the output switch unit 150 , shunt units 171 and 172 , matching units 111 and 112 , the first signal terminal N 1 and the second signal terminal N 2 . Like FIG. 2 , the switch units 110 to 140 , the output switch unit 150 and the bypass units 180 and 185 may respectively include the transistors M 11 to M 14 , M 16 , M 15 and M 17 . The control terminals of the transistors M 11 to M 14 , M 16 , M 15 and M 17 may be respectively coupled to suitable resistors for receiving control signals. Each of the shunt units 171 and 172 may include a set of transistors coupled to one another in a cascode structure, where each transistor may include a control terminal coupled to a suitable resistor to receive a control signal. A resistor coupled to a control terminal of a transistor may be a choking resistor. The matching units 111 and 112 of FIG. 8 are not depicted in the above description and figures for simplicity. According to an embodiment, a matching unit may be coupled to a signal terminal. A suitable matching component may be selected to be a matching unit according to a frequency band of a received signal. For example, the matching units 111 and 112 may be two inductors having inductance values respectively corresponding to the frequency bands of the first signal S 1 and the second signal S 2 . The bypass unit 180 may include a capacitor Cby 1 , and the capacitor Cby 1 may have a capacitance value corresponding to the frequency band of the first signal S 1 . The bypass unit 185 may include a capacitor Cby 2 , and the capacitor Cby 2 may have a capacitance value corresponding to the frequency band of the second signal S 2 .

The second set of components of FIG. 8 may include the switch units 210 to 240 , the bypass units 280 and 285 , the output switch unit 250 , shunt units 271 and 272 , matching units 211 and 212 , the third signal terminal N 3 and the fourth signal terminal N 4 , and be used to receive the third signal S 3 and the fourth signal S 4 . The bypass units 280 and 285 may respectively include capacitors Cby 3 and Cby 4 . The capacitor Cby 3 and the matching unit 211 may be corresponding to a frequency band of the third signal S 3 . The capacitor Cby 4 and the matching unit 212 may be corresponding to a frequency band of the fourth signal S 4 .

The third set of components of FIG. 8 may include the switch units 310 to 340 , the bypass units 380 and 385 , the output switch unit 350 , shunt units 371 and 372 , matching units 311 and 312 , the fifth signal terminal N 5 and the sixth signal terminal N 6 , and be used to receive the fifth signal S 5 and the sixth signal S 6 . The bypass units 380 and 385 may respectively include capacitors Cby 5 and Cby 6 . The capacitor Cby 5 and the matching unit 311 may be corresponding to a frequency band of the fifth signal S 5 . The capacitor Cby 6 and the matching unit 312 may be corresponding to a frequency band of the sixth signal S 6 .

In FIG. 8 , each of the second set of components and the third set of components may have a structure and an operation principle similar to that of the first set of components. The circuit of FIG. 8 may be corresponding to a single pole six throw (SP6T) switch. However, FIG. 8 merely provides an example instead of limiting the scope of embodiments. For example, the structure of FIG. 8 may be expanded to be used for a single pole multiple throw (SPMT) switch.

According to the embodiments of FIG. 7 and FIG. 8 , the voltage at the control terminal of the transistor M 62 of the amplifier circuit 615 may be 2.8 volts. A voltage at the second terminal of the transistor M 62 which is a terminal coupled to the inductor L 62 may be 0 volts. The transistors M 61 and M 62 of the amplifier circuit 615 may be a pair of bipolar transistors or a pair of metal-oxide-semiconductor field-effect transistors (MOSFETs). According to another embodiment, one of the transistors M 61 and M 62 may be a bipolar transistor, and another may be a MOSFET.

FIG. 9 illustrates a capacitor equivalent structure of the circuits of FIG. 7 and FIG. 8 for qualitative analysis. By observing the first set of components of FIG. 7 at the output terminal N opt of FIG. 7 and FIG. 8 along a direction toward the first signal terminal N 1 and the second signal terminal N 2 , the switch units 110 to 140 , the output switch unit 150 , the transistors M 15 and the transistor M 17 may be respectively expressed as equivalent capacitors C 910 to C 940 , C 950 , C 980 and C 985 . The capacitors Cby 1 and Cby 2 of FIG. 9 may be coupled at the positions shown in FIG. 8 to obtain the equivalent circuit of FIG. 9 . An equivalent capacitor of a transistor may be a drain-source capacitor. After entering a bypass mode, the transistors M 12 , M 14 and M 16 may be turned off. According to an embodiment, sizes of the capacitor Cby 1 , the capacitor Cby 2 and the transistors may be adjusted to adjust the equivalent capacitances. For example, capacitance value of each of the capacitors Cby 1 and Cby 2 may be 1 picofarad (10 −12 farad). Each of the equivalent capacitors C 980 and C 985 may have a capacitance value of 32 femtofarads, where 1 femtofarad is 10 −15 farads. Each of the equivalent capacitors C 910 , C 920 , C 930 and C 940 may have a capacitance value of 1300 femtofarads. The equivalent capacitor C 950 may have a capacitance value of 2600 femtofarads. The first signal terminal N 1 and the second signal terminal N 2 may be regarded as equivalent reference voltage terminals. Hence, by means of calculations regarding the capacitors coupled in series and in parallel, an equivalent capacitance value of 1300 femtofarads observed from the output terminal N opt into the circuit may be obtained, and this equivalent capacitance value may be approximately an equivalent capacitance value of a single transistor. Hence, by means of the circuit structure provided by an embodiment, loading effect may be reduced. The effect of reducing loading effect may be more significant when bypassing a signal. According to calculation, an equivalent load is hardly influenced by components of a bypass path. Furthermore, because a functional path can be omitted from the output terminal N opt to the bypass circuit 625 and the amplifier circuit 615 , it may be avoided to set switches and capacitors on a functional path, and the layout of the circuit may be more compact so as to occupy a smaller area. Furthermore, the insertion loss may be reduced according to an embodiment. The abovementioned capacitance values are merely used as examples rather than limiting the specifications of the components, and the specifications of the components may be adjusted according to requirements.

FIG. 10 illustrates a control circuit 1000 with a bypass function according to an embodiment. The components, the terminals and the couplings of the control circuit 1000 may be similar to what of the control circuit 100 of FIG. 1 , and the similarities are not described repeatedly. A difference from FIG. 1 to FIG. 10 is that the switch unit 140 may be omitted in FIG. 10 . As shown in FIG. 10 , the switch unit 130 may include a first terminal and a second terminal where the first terminal may be coupled to the second signal terminal N 2 and the second terminal may be coupled to the first terminal of the output switch unit 150 . In other words, the control circuit 1000 may merely provide the bypass path Ptb 1 for bypassing the first signal, and this simpler structure is also of the scope of embodiments.

In summary, by means of a control circuit provided by an embodiment, it is allowed to switch paths to amplify an inputted signal using an amplifier or bypass the signal. It is also allowed to omit unnecessary switches and capacitors. Hence, the layout may be more compact, and loading effect and insertion loss may be decreased. As a result, the invention is useful for alleviating engineering problems in the field.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.