Electroluminescent display device

This application claims the benefit of the Korean Patent Application No. 10-2017-0184839 filed on Dec. 29, 2017, which is hereby incorporated by reference in its entirety as if fully set forth herein.

The present disclosure relates to a display device, and more particularly, to an electroluminescent display device. Although the present disclosure is suitable for a wide scope of applications, it is particularly suitable for overcoming a problem related with a resistance of a low level voltage line in the electroluminescent display device without sacrificing an aperture ratio.

Description of the Background

An electroluminescent display device is provided in such way that an emission layer is formed between two electrodes. As the emission layer emits light by an electric field generated between the two electrodes, an image is displayed on the electroluminescent display device.

The emission layer may be formed of an organic material which emits light when the exciton is produced by a bond of electron and hole, and the exciton falls to a ground state from an excited state. Otherwise the emission layer may be formed of an inorganic material such as quantum dot.

Recently, a top emission type is applied to the electroluminescent display device. Most cases of the top emission type of the electroluminescent display device, a cathode electrode is provided with a thin thickness and formed of a transparent metal material. Accordingly, the low level voltage line connected with the cathode electrode is increased in its resistance so that it may cause a problem related with non-uniformity of luminance over all pixels.

The present disclosure has been made in view of the above problems, and the present disclosure is to provide an electroluminescent display device which is capable of overcoming a problem related with a resistance of the low level voltage line without any loss of an aperture ratio.

In accordance with an aspect of the present disclosure, the above and other objects can be accomplished by the provision of an electroluminescent display device comprising a substrate, a first electrode provided on the substrate, a bank configured to cover an end of the first electrode and to define an emission area, an emission layer provided on the first electrode in the emission area defined by the bank, a second electrode provided on the emission layer and the bank, a conductive layer provided on the second electrode, and the low level voltage line provided on the substrate and electrically connected to the second electrode or the conductive layer.

In another aspect of the present disclosure, an electroluminescent display device includes a substrate where an active area and a non-active area are defined; a first electrode disposed on the substrate; a bank covering both lateral ends of the first electrode and defining an emission area which corresponds to an aperture portion of the active area; a second electrode disposed on the emission layer and the bank; an emission layer disposed between the first and second electrodes in the emission area defined by the bank; a low level voltage line disposed at a low level voltage line contact portion of the non-active area and electrically connected to the second electrode; and a conductive layer disposed on the second electrode and positioned at the bank portion and the low level voltage line contact portion.

In a further aspect of the present disclosure, an electroluminescent display device includes a substrate where an active area and a non-active area are defined, wherein the active area includes an aperture portion and a bank portion, and the non-active area includes a gate driver, a pad portion and a low level voltage line contact portion; a thin film transistor disposed at the aperture portion of the active area; a passivation layer covering the thin film transistor and having first and second contact holes; a first electrode disposed at the aperture portion and electrically connected to the thin film transistor through the first contact hole; a bank covering both lateral ends of the first electrode and defining an emission area which corresponds to the aperture portion of the active area; a second electrode disposed on the emission layer and the bank; an emission layer disposed between the first and second electrodes in the emission area defined by the bank; a low level voltage line disposed at a low level voltage line contact portion of the non-active area and electrically connected to the second electrode through the first contact hole; and a conductive layer disposed on the second electrode and positioned at the bank portion and the low level voltage line contact portion.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed.

The above and features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a plane view illustrating an electroluminescent display device according to an aspect of the present disclosure;

FIG. 2 is an enlarged plane view showing rectangular portion ‘A’ of FIG. 1 ;

FIG. 3 is a cross sectional view along I-I′ of FIG. 2 according to an aspect of the present disclosure; and

FIG. 4 is a cross sectional view along I-I′ of FIG. 2 according to another aspect of the present disclosure.

Advantages and features of the present disclosure, and implementation methods thereof will be clarified through the following aspects, described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as being limited to the aspects set forth herein. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Further, the present disclosure is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, and numbers disclosed in the drawings for describing aspects of the present disclosure are merely examples, and thus the present disclosure is not limited to the illustrated details. Like reference numerals refer to like elements throughout. In the following description, when the detailed description of the relevant known function or configuration is determined to unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted.

In the case in which “comprise,” “have,” and “include” described in the present specification are used, another part may also be present unless “only” is used. The terms in a singular form may include plural forms unless noted to the contrary.

In construing an element, the element is construed as including the margins of error although there is no explicit description thereof.

In describing a positional relationship, for example, when the positional order is described as “on,” “above,” “below,” and “next,” the case of no contact therebetween may be included, unless “just” or “direct” is used. If it is mentioned that a first element is positioned “on” a second element, it does not mean that the first element is essentially positioned above the second element in the figure. The upper part and the lower part of an object concerned may be changed depending on the orientation of the object. Consequently, the case in which a first element is positioned “on” a second element includes the case in which the first element is positioned “below” the second element as well as the case in which the first element is positioned “above” the second element in the figure or in an actual configuration.

In describing a temporal relationship, for example, when the temporal order is described as “after,” “subsequent,” “next,” and “before,” a case which is not continuous may be included, unless “just” or “direct” is used.

It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

The terms “first horizontal axis direction,” “second horizontal axis direction,” and “vertical axis direction” should not be interpreted only based on a geometrical relationship in which the respective directions are perpendicular to each other, and may be meant as directions having wider directivities within the range within which the components of the present disclosure can operate functionally.

It should be understood that the term “at least one” includes all combinations related with any one item. For example, “at least one among a first element, a second element and a third element” may include all combinations of two or more elements selected from the first, second and third elements as well as each element of the first, second and third elements.

Features of various aspects of the present disclosure may be partially or overall coupled to or combined with each other, and may be variously inter-operated with each other and driven technically as those skilled in the art can sufficiently understand. The aspects of the present disclosure may be carried out independently from each other, or may be carried out together in a co-dependent relationship.

Hereinafter, an electroluminescent display device according to an aspect of the present disclosure will be described in detail with reference to the accompanying drawings.

FIG. 1 is a plane view illustrating an electroluminescent display device according to an aspect of the present disclosure. As shown in FIG. 1 , the X-axis indicates a direction which is parallel to a gate line, the Y-axis indicates a direction which is parallel to a data line, and the Z-axis indicates a height (or thickness) direction of the electroluminescent display device.

Referring to FIG. 1 , the electroluminescent display device according to an aspect of the present disclosure may include a substrate 100 , a source drive integrated circuit 410 , a flexible film 430 , a circuit board 450 and a timing controller 500 .

The substrate 100 may be a flexible substrate. For example, the substrate 100 may include a transparent polyimide material. The substrate 100 of the polyimide material may be obtained by curing polyimide resin coated with a uniform thickness onto the front surface of a release layer prepared in a carrier glass substrate. The carrier glass substrate is separated from the substrate 100 by the elimination of the release layer for a laser release process. On one surface of the substrate 100 , there are pluralities of gate lines, data lines, and pixels. The pixels may include a plurality of sub pixels, and the plurality of sub pixels are provided adjacent to crossing areas of the gate lines and the data lines.

The substrate 100 according to an aspect of the present disclosure may include an active area AA and a non-active area NA.

The active area AA corresponds to an area for displaying an image thereon, which may be defined in the middle of the substrate 100 . The active area AA may be provided with the gate lines, the data lines and the pixels.

The non-active area NA corresponds to an area on which an image is not displayed, wherein the non-active area NA may be defined in the periphery of the substrate 100 so as to surround the active area AA. The non-active area NA may be provided with a gate driver GP, a pad portion DP and a low level voltage line contact portion CP.

The gate driver GP supplies the gate signals to the gate lines in accordance with a gate control signal which is provided from the timing controller 500 . The gate driver GP may be provided in the non-active area NA at an outer side of the active area AA of the substrate 100 by a GIP (i.e., gate driver in panel) method.

The pad portion DP supplies the data signals to the data lines in accordance with a data control signal which is provided from the timing controller 500 . The pad portion DP may be manufactured in a driving chip, mounted on the flexible film 430 , and attached to the non-active area NA at an outer area from the active area AA of the substrate 100 by a TAB (i.e., tape automated bonding) method.

The low level voltage line contact portion CP may connect a low level voltage line and a second electrode included in the pixel of the active area AA. For example, the low level voltage line contact portion CP is provided in an area which overlaps the edge of the second electrode, so that the low level voltage line contact portion CP can be electrically connected to the edge of the second electrode via a contact hole.

The source drive integrated circuit 410 receives the digital video data and the source control signal from the timing controller 500 . The source drive integrated circuit 410 converts the digital video data into the analog data voltages in accordance with the source control signal, and provides the analog data voltages to the data lines. If the source drive integrated circuit 410 is manufactured in a driving chip, the source drive integrated circuit 410 may be mounted on the flexible film 430 by a COF (i.e., chip on film) method or a COP (i.e., chip on plastic) method.

The flexible film 430 may be provided with lines for connecting the pad portion DP and the source drive integrated circuit 410 with each other, and lines for connecting the pad portion DP and the circuit board 450 with each other. The flexible film 430 is attached onto the pad portion DP by the use of an anisotropic conducting film, so that the pad portion DP can be connected to the lines of the flexible film 430 .

The circuit board 450 may be attached to the flexible films 430 . A plurality of circuits, which is implemented as driving chips, may be mounted on the circuit board 450 . For example, the timing controller 500 may be mounted on the circuit board 450 . The circuit board 450 may be a printed circuit board or a flexible printed circuit board.

The timing controller 500 receives the digital video data and the timing signal from an external system board via a cable of the circuit board 450 . The timing controller 500 generates a gate control signal for controlling an operation timing of the gate driver GP, and a source control signal for controlling the source drive integrated circuits 410 on the basis of timing signal. The timing controller 500 supplies the gate control signal to the gate driver GP, and supplies the source control signal to the source drive integrated circuits 410 .

FIG. 2 is an enlarged plane view showing rectangular portion ‘A’ of FIG. 1 . FIG. 3 is a cross sectional view along I-I′ of FIG. 2 according to an aspect of the present disclosure.

Referring to FIGS. 2 and 3 , the electroluminescent display device according to an aspect of the present disclosure may include a substrate 100 , a light shielding layer 110 , a buffer layer 120 , a thin film transistor T, an insulating interlayer 130 , a passivation layer 140 , a planarization layer 150 , a first electrode E 1 , a bank 160 , an emission layer EL, a second electrode E 2 , a conductive layer 170 , a low level voltage line (VSS) 200 , a signal pad 300 and a pad electrode 310 .

The substrate 100 may be a flexible substrate, as described above, but not limited to this type.

As described above, the substrate 100 according to an aspect of the present disclosure may include an active area AA and a non-active area NA, wherein the active area AA may include an aperture portion AP and a bank portion BP, and the non-active area NA may include a gate driver GP, a pad portion DP and a low level voltage line contact portion CP.

The aperture portion AP may be an emission portion which is not provided with a bank, and the bank portion BP may be a non-emission portion which is provided with a bank. As described above, the gate driver GP, the pad portion DP and the low level voltage line contact portion CP correspond to the predetermined portions of the non-active area NA. However, elements for the non-active area NA are not limited to the above portions such as the gate driver GP, the pad portion DP and the low level voltage line contact portion CP, that is, the non-active area NA is not realized by combining only the above portions such as the gate driver GP, the pad portion DP and the low level voltage line contact portion CP.

The light shielding layer 110 is provided on the aperture portion AP of the substrate 100 . The light shielding layer 110 prevents light from being advanced to an active layer ACT to be explained later.

The buffer layer 120 is provided on the light shielding layer 110 . The buffer layer 120 extends from the active area AA to the non-active area NA. The buffer layer 120 may be formed of an inorganic insulating material, for example, formed in a single-layered structure or a multi-layered structure of a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, but not limited to these structures.

The thin film transistor T is provided at the aperture portion AP of the substrate 100 . More specifically, the thin film transistor T is provided on the buffer layer 120 . The thin film transistor T may include the aforementioned active layer ACT, a gate electrode G, and source/drain electrodes S/D.

The active layer ACT is provided on the buffer layer 120 . A gate insulating film GI is provided on the active layer ACT, and a gate electrode G is provided on the gate insulating film GI. Further, an intermediate insulating interlayer 130 is provided on the gate electrode G, and the source/drain electrodes S/D are provided on the insulating interlayer 130 .

The active layer ACT according to an aspect of the present disclosure may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material.

The gate insulating film GI insulates the active layer ACT and the gate electrode G from each other, wherein a pattern of the gate insulating film GI may be identical to a pattern of the gate electrode G. The gate insulating film GI may be formed of an inorganic insulating material, for example, formed in a singular-layered structure or a multi-layered structure of a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, but not limited to these structures.

The gate electrode G is provided on the gate insulating film GI.

The intermediate insulating interlayer 130 may be formed of an inorganic insulating material, for example, formed in a single-layered structure or a multi-layered structure of a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, but not limited to these structures. The intermediate insulating interlayer 130 extends from the active area AA to the non-active area NA.

The source/drain electrodes S/D facing each other are provided on the insulating interlayer 130 . Herein, contact holes for exposing one end and the other end of the active layer ACT are provided in the intermediate insulating interlayer 130 , and the source/drain electrodes S/D are respectively connected with one end and the other end of the active layer ACT via the contact holes.

In addition, a contact hole for exposing the light shielding layer 110 is provided in the buffer layer 120 and the intermediate insulating interlayer 130 , and the source/drain electrodes S/D are connected with the light shielding layer 110 via the contact hole. The light shielding layer 110 according to an aspect of the present disclosure is formed of a conductive material. When the light shielding layer 110 is in the floating state, the active layer ACT may be negatively influenced by the floating light shielding layer 110 . In this reason, the light shielding layer 110 is connected with the source/drain electrodes S/D, so that an adverse influence or effect on the active layer ACT can be prevented.

The passivation layer 140 is provided on the source/drain electrodes S/D. The passivation layer 140 protects the thin film transistor T, and the passivation layer 140 extends from the active area AA to the non-active area NA. The passivation layer 140 may be formed of an inorganic insulating material, for example, a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, but not limited to these materials.

The planarization layer 150 is provided on the passivation layer 140 . The planarization layer 150 may planarize an upper surface of the substrate 100 including the thin film transistor T. The planarization layer 150 may be formed of an organic insulating material, for example, acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and etc., but not limited to these materials.

The first electrode E 1 is provided within the aperture portion AP of the substrate 100 . The first electrode E 1 is provided on the planarization layer 150 .

The first electrode E 1 according to an aspect of the present disclosure may be connected to the source electrode S or the drain electrodes D via the contact hole provided in the passivation layer 140 and the planarization layer 150 .

The first electrode E 1 according to an aspect of the present disclosure is patterned as corresponding to each pixel, and the first electrode E 1 according to an aspect of the present disclosure may serve as an anode of the electroluminescent display device. When the electroluminescent display device according to an aspect of the present disclosure is applied to a top emission type, the first electrode E 1 may include a reflective material for upwardly reflecting light emitted from the emission layer EL. In this case, the first electrode E 1 may be formed in a stacked structure including the reflective material and a transparent conductive material.

The bank 160 is provided on the bank portion BP of the substrate 100 . The bank 160 covers an end of the first electrode E 1 and defines an emission area. An upper surface of the first electrode E 1 is exposed in the emission area between each of the banks 160 according to an aspect of the present disclosure, and light is emitted through the exposed upper surface of the first electrode E 1 , to thereby display an image.

The bank 160 according to an aspect of the present disclosure may be formed of an organic insulating material, for example, polyimide resin, acryl resin, benzocyclobutene (BCB), and etc., but not limited to these materials.

The emission layer EL is provided on the aperture portion AP of the substrate 100 . The emission layer EL is provided on the first electrode E 1 in the emission area defined by the bank 160 . The emission layer EL according to an aspect of the present disclosure may include a hole injecting layer, a hole transporting layer, an organic emitting layer, an electron transporting layer, and an electron injecting layer. The structure of the emission layer EL may be changed in various types generally known to those in the art.

The emission layer EL according to an aspect of the present disclosure may include a red emitting material layer, a green emitting material layer and a blue emitting material layer. Accordingly, the aperture portion AP may include a red sub pixel, a green sub pixel and a blue sub pixel, wherein the above red, green and blue sub pixels constitute one unit pixel.

The second electrode E 2 is provided on the emission layer EL and the bank 160 . In the case of the top emission type, as the second electrode E 2 is provided on a light emission surface, the second electrode E 2 may be formed of a transparent conductive material. However, as the transparent conductive material has a high resistance, the conductive layer 170 may be additionally provided so as to reduce the resistance of the second electrode E 2 .

The second electrode E 2 according to an aspect of the present disclosure may be provided on the active area AA and the low level voltage line contact portion CP of the substrate 100 . In detail, the second electrode E 2 may be provided to cover the active area AA and the low level voltage line contact portion CP of the substrate 100 as one body. Accordingly, the second electrode E 2 is provided as one body without being patterned by each pixel, and the second electrode E 2 is thinly formed of a transparent conductive material, for example, metal material such as MgAg, whereby the low level voltage line 200 electrically connected with the second electrode E 2 may have a high resistance, and it may cause non-uniformity of luminance over all of the pixels. Thus, the electroluminescent display device according to the first aspect of the present disclosure may include the conductive layer 170 , additionally.

The conductive layer 170 is provided on the second electrode E 2 . The conductive layer 170 is in contact with the second electrode E 2 so that it is possible to reduce the resistance of the second electrode E 2 . The conductive layer 170 is provided on the bank portion BP and the low level voltage line contact portion CP of the substrate 100 .

The conductive layer 170 according to an aspect of the present disclosure may be formed of a metal material having high conductivity, for example, aluminum (Al). The conductive layer 170 is formed in a pattern shape on the bank portion BP and the low level voltage line contact portion CP so that deterioration in transmittance of the aperture portion AP can be prevented. As the conductive layer 170 is formed of the material having high conductivity, the resistance of the second electrode E 2 through the surface contact between the conductive layer 170 and the second electrode (E 2 ) can be reduced.

The conductive layer 170 according to an aspect of the present disclosure may be formed of a reflective material. In this case, light emitted from the emission layer EL may be reflected on the conductive layer 170 , so that a light emission efficiency can be improved.

Meanwhile, although not shown in figures, an encapsulation layer may be additionally provided on the conductive layer 170 so as to prevent external moisture or oxygen from being permeated into the emission layer EL. The encapsulation layer may be formed of an inorganic insulating material, or may be formed in a stacked structure obtained by alternately depositing an inorganic insulating material and an organic insulating material, but not limited to these structures.

The low level voltage line 200 is provided on the low level voltage line contact portion CP of the substrate 100 . The low level voltage line 200 is provided on the buffer layer 120 . The low level voltage line 200 according to an aspect of the present disclosure may apply a low level voltage to the second electrode E 2 . For example, the low level voltage line 200 may be electrically connected with the second electrode E 2 via connection electrodes 210 and 220 .

Also, a contact hole for exposing the low level voltage line 200 is provided in the buffer layer 120 and the intermediate insulating interlayer 130 according to an aspect of the present disclosure, and the second electrode E 2 may be connected with the low level voltage line 200 via the connection electrodes 210 and 220 provided in the contact hole. The connection electrodes 210 and 220 may include the first connection electrode 210 being in contact with the low level voltage line 200 , and the second connection electrode 220 being in contact with the second electrode E 2 .

The first connection electrode 210 is provided on the same layer as the source/drain electrodes S/D is disposed, and is formed of the same material as that of the source/drain electrodes S/D. In this case, the source/drain electrodes S/D and the first connection electrode 210 may be manufactured at the same time by the same process, to thereby improve a manufacturing efficiency.

The second connection electrode 220 is provided on the same layer as the first electrode E 1 is disposed, and is formed of the same material as that of the first electrode E 1 . In this case, the first electrode E 1 and the second connection electrode 220 may be manufactured at the same time by the same process, to thereby improve a manufacturing efficiency.

The low level voltage line 200 according to an aspect of the present disclosure is electrically connected with the second electrode E 2 , and the second electrode E 2 is electrically connected with the conductive layer 170 , so that a resistance of the low level voltage line 200 can be reduced. That is, as described above, the conductive layer 170 is formed in a pattern shape of a material having high conductivity, and then in contact with the second electrode E 2 , so that the resistance of the second electrode E 2 can be lowered, and thus, a resistance of the low level voltage line 200 connected with the second electrode E 2 can be also lowered. Even though there is an additional auxiliary line in the electroluminescent display device according to an aspect of the present disclosure, the resistance of the low level voltage line 200 can be reduced. Thus, an area of the aperture portion AP may be increased by eliminating an occupied area required for the auxiliary line, so that an aperture ratio can be improved.

In case of the electroluminescent display device according to an aspect of the present disclosure, the resistance of the low level voltage line (VSS) 200 can be maintained in a low state, and also uniformity of luminance can be improved by preventing non-uniformity of luminance over all of the pixels. Also, the auxiliary line is not required in the electroluminescent display device according to an aspect of the present disclosure, so that an aperture ratio can be improved, and also a long lifespan of the electroluminescent display device can be achieved according to an aspect of the present disclosure.

The signal pad 300 is provided on the pad portion DP of the substrate 100 . The signal pad 300 is provided on the buffer layer 120 . The signal pad 300 according to an aspect of the present disclosure may be formed of the same material as that of the gate electrode G of the active area AA. In this case, the signal pad 300 and the gate electrode G may be manufactured at the same time by the same process.

The pad electrode 310 is provided on the pad portion DP of the substrate 100 . The pad electrode 310 is provided on the insulating interlayer 130 , and is connected with the signal pad 300 via the contact hole.

The pad electrode 310 according to an aspect of the present disclosure may be formed of the same material as those of the first connection electrode 210 and the source/drain electrodes S/D of the active area AA. In this case, the pad electrode 310 , the source/drain electrodes S/D and the first connection electrode 210 may be manufactured at the same time by the same process.

Additionally, a corrosion-resistant cover pad electrode may be provided on an upper surface of the pad electrode 310 according to an aspect of the present disclosure. Thus, a lateral surface of the pad electrode 310 is covered by the passivation layer 140 , so that the lateral surface of the pad electrode 310 can be prevented from being corroded, and the upper surface of the pad electrode 310 can be prevented from being corroded by the use of corrosion-resistant cover pad electrode.

FIG. 4 is a cross-sectional view along I-I′ of FIG. 2 according to another aspect of the present disclosure. The electroluminescent display device of FIG. 4 can be implemented by changing a structure of a second electrode E 2 , and a detailed description for the same parts will be omitted, and only the different structures will be described in detail as follows.

Referring to FIG. 4 the electroluminescent display device according to another aspect of the present disclosure includes the second electrode E 2 .

The second electrode E 2 is provided on an emission layer EL and a bank 160 . As the second electrode E 2 is provided on a light emission surface, the second electrode E 2 is formed of a transparent conductive material. However, the transparent conductive material has a relatively higher resistance than a metal material, a conductive layer 170 may be additionally provided to reduce the resistance of the second electrode E 2 .

The second electrode E 2 according to another aspect of the present disclosure may be provided on an aperture portion AP of a substrate 100 . In detail, the second electrode E 2 may be formed in a pattern shape on the aperture portion AP of the substrate 100 . The second electrode E 2 is patterned by each pixel, whereby the second electrode E 2 is not directly connected with a low level voltage line 200 . The second electrode E 2 is in contact with the conductive layer 170 , and is electrically connected with the conductive layer 170 , and the conductive layer 170 is electrically connected with the low level voltage line 200 via a contact hole, whereby the second electrode E 2 and the low level voltage line 200 may be electrically connected with each other.

The low level voltage line 200 according to another aspect of the present disclosure is provided on a low level voltage line contact portion CP of the substrate 100 . The low level voltage line 200 according to another aspect of the present disclosure may be electrically connected to the conductive layer 170 via connection electrodes 210 and 220 .

Also, a contact hole for exposing the low level voltage line 200 is provided in a buffer layer 120 and an intermediate insulating interlayer 130 according to another aspect of the present disclosure, and the conductive layer 170 may be connected with the low level voltage line 200 via the connection electrodes 210 and 220 provided in the contact hole.

The low level voltage line 200 according to another aspect of the present disclosure is electrically connected to the conductive layer 170 , and the conductive layer 170 is electrically connected to the second electrode E 2 , so that a resistance of the low level voltage line 200 can be reduced. That is, when the conductive layer 170 is formed in a pattern shape of a material having high conductivity, and is then electrically connected to the low level voltage line 200 , the resistance of the low level voltage line 200 may have relatively lowered resistance as compared to the resistance of the low level voltage line 200 on the direct contact between the low level voltage line 200 and the second electrode E 2 . That is, according as the conductive layer 170 formed in the plurality of pattern shapes is in contact with the second electrode E 2 , the resistance in the conductive layer 170 and the second electrode E 2 is lowered. Thus, even though an additional auxiliary line is not provided in the electroluminescent display device according to another aspect of the present disclosure, it is possible to reduce the resistance of the low level voltage line 200 . Thus, an area of the aperture portion AP may be increased by eliminating an occupied area for the auxiliary line, so that an aperture ratio can be improved.

In case of the electroluminescent display device according to another aspect of the present disclosure, the resistance of the low level voltage line 200 can be maintained in relatively a low state, and uniformity of luminance can be improved by preventing non-uniformity of luminance over all of the pixels. Also, the auxiliary line is not provided in the electroluminescent display device according to another aspect of the present disclosure so that it is possible to improve the aperture ratio, and also to ensure a long lifespan of the electroluminescent display device according to another aspect of the present disclosure.

According to the aspects of the present disclosure, the resistance of the low level voltage line can be reduced by the use of conductive layer formed in the pattern shape on the second electrode, thereby improving an aperture ratio and ensuring a long lifespan of an electroluminescent display device.

It will be apparent to those skilled in the art that the present disclosure described above is not limited by the above-described aspects and the accompanying drawings and that various substitutions, modifications, and variations can be made in the present disclosure without departing from the spirit or scope of the disclosures. Consequently, the scope of the present disclosure is defined by the accompanying claims, and it is intended that all variations or modifications derived from the meaning, scope, and equivalent concept of the claims fall within the scope of the present disclosure.

The aspects of the present disclosure can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further aspects.

These and other changes can be made to the aspects of the present disclosure in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific aspects disclosed in the specification and the claims, but should be construed to include all possible aspects along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.