Low leakage low dropout regulator with high bandwidth and power supply rejection, and associated methods

This application is a divisional of U.S. application Ser. No. 15/475,266, entitled “LOW LEAKAGE LOW DROPOUT REGULATOR WITH HIGH BANDWIDTH AND POWER SUPPLY REJECTION”, filed Mar. 31, 2017, the contents of which are incorporated by reference in their entirety.

This disclosure is related to the field of low dropout regulators, and more particularly, to a low dropout regulator that utilizes a low voltage ballast transistor for high bandwidth and power supply rejection, and that protects the low voltage ballast transistor from electrical overstresses.

Handheld battery powered electronic devices such as tablets and smartphones have been in wide use in recent years, with usage rates that are ever increasing, and with additional functionality being added on a regular basis.

A common type of voltage regulator used in such electronic devices is known as a low dropout (LDO) regulator, which can operate with a small input to output voltage difference, and which provides a high degree of efficiency and heat dissipation. A typical LDO regulator includes an error amplifier that controls a field effect transistor (FET) or bipolar junction transistor (BJT) to cause that transistor to sink or source current from or to an output node. One input of the error amplifier receives a feedback signal, while the other receives a reference voltage. The error amplifier controls the power FET or BJT so as to maintain a constant output voltage.

The power FET or BJT is typically tolerant of 5V, meaning that the FET or BJT therefore has a large area and a low transconductance, however to source or sink a high current, a large transconductance would be required, leading to a very large sized transistor. This in turn leads to high leakage current when the LDO is powered down. In addition, the bandwidth of the LDO is limited by a high input gate to base capacitance to the power FET or BJT. Another drawback of this design is that the power FET or BJT has a large gate to drain or base to emitter capacitance and total gate or drain capacitance due to its size, which results in degradation in high frequency power source noise rejection.

In an attempt to address these drawbacks, additional designs have been devised. For example, a LDO 100 is shown in FIG. 1 . In this LDO, amplifier 102 has its inverting input terminal coupled to a reference voltage Vref, its non-inverting input terminal coupled to receive a feedback voltage Vfb, and its output coupled to the gate of p-channel transistor T 1 . P-channel transistor T 1 has its source coupled to a supply voltage Vdd and its drain coupled to node N 1 . P-channel transistor T 2 has its source coupled to node N 1 , its drain coupled to provide the output of the LDO Vout at node N 3 , and its gate coupled to the output of amplifier 104 . Amplifier 104 has its inverting terminal coupled to node N 1 and its non-inverting terminal coupled to receive comparison voltage Vc. A resistive divider formed from series coupled resistances R 1 and R 2 is coupled between node N 3 and ground. A center tap N 2 of the resistive divider formed by R 1 and R 2 is coupled to the non-inverting terminal of amplifier 102 to provide the feedback voltage Vfb thereto.

The transistors T 1 and T 2 are low voltage devices, and are to be protected from electrical overstresses. When the LDO 100 is operating in a normal power on mode, T 2 is biased by amplifier 104 such that it acts as a switch. When the LDO 100 is powered down, node N 1 is biased such that neither T 1 nor T 2 experiences overstresses. However, during the transition between the powered on mode and the powered down mode, or between the powered down mode and the powered on mode, node N 1 can intermittently go to supply or ground at a different time constant than node N 3 , which can also go to ground. Transistor T 1 can be stressed because it has no protections against such overstresses, and transistor T 2 can be stressed because it is within the feedback loop.

Further development of LDO regulators is necessary to address the aforementioned drawbacks.

This summary is provided to introduce a selection of concepts that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter.

Disclosed herein is a method of operating an electronic device including a low dropout regulator having an output coupled to a first conduction terminal of a transistor, with a second conduction terminal of the transistor being coupled to an output node of the electronic device. The method includes placing the electronic device into a power on mode by: turning on the low dropout regulator, removing a DC bias from the second conduction terminal of the transistor, and turning on the transistor. The method also includes placing the electronic device into a power down mode by: turning off the transistor, forming the DC bias at the second conduction terminal of the transistor, and turning off the low dropout regulator.

When placing the electronic device into the power on mode, the transistor may be turned on before the DC bias is removed from the second conduction terminal of the transistor.

When placing the electronic device into the power on mode, the transistor may be turned on after the DC bias is removed from the second conduction terminal of the transistor.

When placing the electronic device into the power on mode, the transistor may be turned on substantially simultaneously with removal of the DC bias from the second conduction terminal of the transistor.

When placing the electronic device into the power down mode, the transistor may be turned off before the DC bias is formed at the second conduction terminal of the transistor.

When placing the electronic device into the power down mode, the transistor may be turned off after the DC bias is formed at the second conduction terminal of the transistor.

When placing the electronic device into the power down mode, the transistor may be turned off substantially simultaneously with forming of the DC bias at the second conduction terminal of the transistor.

Also disclosed herein is an electronic device including an intermediate node, a resistive divider directly electrically connected between the intermediate node and a divider control node, and a low dropout amplifier. The low dropout amplifier includes an amplifier having an inverting terminal receiving a reference voltage, a non-inverting terminal directly electrically connected to a tap node of the resistive divider, and an output, and a ballast transistor having a first conduction terminal coupled to a supply node, a second conduction terminal coupled to the intermediate node, and a control terminal coupled to the output of the amplifier. A transistor has a first conduction terminal coupled to the intermediate node, a second conduction terminal coupled to an output node, and a control terminal. A first impedance is coupled to the output node. A second impedance is coupled to the output node. A first switch is configured to selectively couple the first impedance to the supply node. A second switch is configured to selectively couple the second impedance to the ground node. A third switch is coupled between the intermediate node and the supply node. A fourth switch is coupled between the output of the amplifier and the supply node. A fifth switch that is a three position switch is for selectively coupling the control terminal of the transistor to the supply node or to ground. A sixth switch is coupled between the divider control node and ground.

The first switch may be a PMOS transistor having a source coupled to the supply node, a drain coupled to the first impedance, and a gate biased by the control circuitry.

The second switch may be an NMOS transistor having a drain coupled to the output node, a source coupled to ground, and a gate biased by the control circuitry.

The third switch may be a PMOS transistor having a source coupled to the supply node, a drain coupled to the intermediate node, and a gate biased by the control circuitry.

The fourth switch may be a PMOS transistor having a source coupled to the supply node, a drain coupled to the output of the amplitude, and a gate biased by the control circuitry.

The sixth switch may be an NMOS transistor having a drain coupled to the divider control node, a source coupled to ground, and a gate coupled to an output of an inverter, the inverter having its input coupled to the control circuitry.

The supply node may be at a voltage in a range of 1 to 5 volts.

The supply node may be at a voltage of 1.8V, 2.5V, or 5V.

The ballast transistor may be a low voltage p-channel transistor.

The transistor may be a PMOS transistor.

FIG. 1 is a schematic block diagram of a prior art low dropout regulator.

FIG. 2 is a schematic block diagram of an electronic device in accordance with this disclosure.

FIG. 3 is a more detailed schematic block diagram of the electronic device of FIG. 2 .

One or more embodiments of the present disclosure will be described below. These described embodiments are only examples of the presently disclosed techniques. Additionally, in an effort to provide a concise description, some features of an actual implementation may not be described in the specification. When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements.

With reference to FIG. 2 , a circuit 50 including a low dropout regulator and its control and bias circuitry is now described. The circuit 50 includes a low dropout regulator 60 receiving a reference signal Vref as input, and providing output to an intermediate node N 3 .

The low dropout regulator 60 itself is comprised of an error amplifier 52 receiving the reference signal at a first input (non-inverting input terminal), and a feedback signal Vfb at a second input (inverting input terminal), and providing an output to node N 4 . The error amplifier 52 is powered between a supply voltage Vdd and ground. The supply voltage Vdd may be 5 V, 2.5 V, 1.8 V, 1V a voltage between 1 V and 5 V, or another suitable voltage.

The low dropout regulator 60 includes a low voltage p-channel transistor M 1 , which may be a PMOS transistor in some cases, and in some cases, may be a low voltage thin gate oxide transistor. The low-voltage p-channel transistor M 1 serves as the ballast for the low dropout regulator 60 . The p-channel transistor M 1 has its source coupled to the supply voltage Vdd, its drain coupled to intermediate node N 3 , and its gate coupled to node N 4 at the output of the error amplifier 52 . A switch SW 4 selectively couples node N 4 (and thus the gate of the p-channel transistor M 1 ) to the supply voltage Vdd. A switch SW 3 selectively couples intermediate node N 3 (and thus the drain of the p-channel transistor M 1 ) to the supply voltage Vdd.

A first resistance R 1 is coupled between the intermediate node N 3 and node N 2 , while a second resistance R 2 is coupled between the node N 2 and switch SW 6 . Switch SW 6 is coupled between resistance R 2 and ground. The first resistance R 1 and second resistance R 2 may have the same resistance values or may have different resistance values, and in some cases one or both of these resistances R 1 , R 2 may be programmable. R 1 and R 2 form a resistive voltage divider receiving the voltage at node N 3 and outputting a feedback voltage Vfb.

Another low-voltage p-channel transistor M 2 has its source coupled to the intermediate node N 3 , its drain coupled to the output node N 1 , and its gate selectively coupled to either the supply voltage Vdd or ground by the switch SW 5 . This p-channel transistor M 2 may also be a PMOS transistor in some cases.

A first impedance ZB 1 is coupled to the output node N 1 , and is selectively coupled to the supply voltage Vdd by switch SW 1 . A second impedance ZB 2 is also coupled to the output node N 1 , and is selectively coupled to ground by switch SW 2 . The first impedance ZB 1 and second impedance ZB 2 may have a same impedance value, or may have different impedance values.

The switches SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , and SW 6 are coupled to control circuitry 62 , which serves to control actuation and deactuation of those switches via the generation of appropriate control signals.

The circuit 50 may operate in a powered down mode or a powered on mode. To switch into the powered on mode from a power off condition, the control circuitry 62 first turns on the error amplifier 52 , and then opens switches SW 6 , SW 4 , and SW 3 . This serves to activate the low dropout regulator 60 .

Then, the control circuitry 62 opens switches SW 2 and SW 1 , removing any DC bias present at the drain of the p-channel transistor M 2 at node N 1 . Thereafter, the control circuitry 62 sets the switch SW 5 to couple the gate of transistor M 2 to ground, turning the transistor M 2 on.

In some cases when switching into the powered on mode, the control circuitry 62 may open switches SW 2 and SW 1 , as well as set the switch SW 5 to couple the gate of transistor M 2 to ground, substantially simultaneously. In others, the control circuitry 62 may set the switch SW 5 to couple the gate of transistor M 2 to ground before opening the switches SW 2 and SW 1 .

To switch into the powered down mode, the control circuitry 62 first sets the switch SW 5 to couple the gate of the p-channel transistor M 2 to the supply voltage Vdd to thereby turn off the p-channel transistor M 2 . Then, the control circuitry 62 closes the switches SW 2 and SW 1 , forming a DC bias at the drain of the p-channel transistor M 2 . Thereafter, the control circuitry 62 closes switches SW 6 , SW 4 , and SW 3 , coupling the drain and gate of the p-channel transistor M 1 to the supply voltage Vdd, thereby turning the p-channel transistor M 1 off. Lastly, the error amplifier 52 is turned off.

In powered down mode, the closing of switches SW 6 , SW 4 , and SW 3 protects the p-channel transistor M 1 , as its source, drain, and gate are all coupled to the same supply voltage Vdd. Similarly, the DC bias formed at the drain of the p-channel transistor M 2 by the impedances ZB 1 and ZB 2 helps serve to protect the p-channel transistor M 2 .

In some cases when switching into the powered down mode, the control circuitry 62 may close switches SW 2 and SW 1 , as well as set the switch SW 5 to couple the gate of transistor M 2 to the power supply node Vdd, substantially simultaneously. In others, the control circuitry 62 may set the switch SW 5 to couple the gate of transistor M 2 to the power supply node Vdd before closing the switches SW 2 and SW 1 .

The voltage drop across p-channel transistor M 2 is minimal, and neither of the p-channel transistors M 1 or M 2 are overstressed. However, the p-channel transistor M 1 has a higher transconductance than the ballast transistor in prior art designs, and the size of the p-channel transistor M 1 can be smaller than in prior art designs. Due to the smaller size of the p-channel transistor M 1 , the gate to drain capacitance is less than in prior designs. As a result, the p-channel transistor M 1 can be fabricated such that the bandwidth of the circuit 50 can be high, and the power supply rejection can be high. Alternatively, the p-channel transistor M 1 can be fabricated such that the quiescent current therethrough is substantially lowered, but with the bandwidth and power supply rejection of the circuit 50 remaining the same as prior art devices.

With additional reference to FIG. 3 , additional details of an additional embodiment are now given. The circuit 50 ′ shown in FIG. 3 operates the same as the circuit 50 shown in FIG. 2 , therefore operation details need not be given. Here, the resistances R 1 ′ and R 2 ′ are resistors, and the impedances ZB 1 ′ and ZB 2 ′ are each pairs of diode coupled n-channel transistors (such as a NMOS transistors), M 3 and M 4 , and M 5 and M 6 . Switch SW 1 ′ is a p-channel transistor (such as a PMOS transistor) having a source coupled to the supply voltage Vdd, a drain coupled to the impedance ZB 1 ′, and a gate coupled to the control circuitry 62 . Switch SW 2 ′ is a n-channel transistor (such as a NMOS transistor) having a drain coupled to the impedance ZB 2 ′, a source coupled to ground, and a gate coupled to the control circuitry 62 . Switch SW 3 ′ is a p-channel transistor (such as a PMOS transistor) having a source coupled to the supply voltage Vdd, a drain coupled to the intermediate node N 3 , and a gate coupled to the control circuitry 62 . Switch SW 4 ′ is a p-channel transistor (such as a PMOS transistor) having a source coupled to the supply voltage Vdd, a drain coupled to the gate of p-channel transistor M 1 , and a gate coupled to the control circuitry 62 . Switch SW 6 ′ is an n-channel transistor (such as an NMOS transistor) having a drain coupled to resistance R 2 ′, a source coupled to ground, and a gate coupled to the control circuitry 62 through an inverter 61 .

While the disclosure has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be envisioned that do not depart from the scope of the disclosure as disclosed herein. Accordingly, the scope of the disclosure shall be limited only by the attached claims.