Backlight drive circuit, driving method thereof, and display device

The present application is a continuation-application of International (PCT) Patent Application No. PCT/CN2018/101637, field on Aug. 22, 2018, which claims foreign priority of Chinese Patent Application No. 201810538863.2, field on May 30, 2018 in the State Intellectual Property Office of China, the entire contents of which are hereby incorporated by reference.

The present disclosure relates to the field of display technologies, and more particularly, to a backlight drive circuit, driving method thereof, and display device.

With the recent advantages in improved display uniformity, regional display, improvement on the contrast, narrow frames and the like, direct-type backlight has been gradually applied to mobile phone modules. The number of drive chip pins of a traditional area light is the sum of the row number and the column number of a light-emitting unit matrix in the area light; however, in order to obtain a better display effect, the row number and column number of the area light are being increased all the time, which results in more and more drive chip pins, and consequentially, the reliability of products is reduced.

The technical issue mainly to be settled by the present disclosure is to provide a backlight drive circuit, a driving method thereof, and a display device. The backlight drive circuit can reduce the number of drive chip pins of an area light, thereby improving the reliability of products.

To solve the above technical problem, the present disclosure adopts a technical solution as below. There is provided a backlight drive circuit includes a plurality of light-emitting units arrayed in a matrix manner and at least first transistors and second transistors, wherein the light-emitting units in each row are connected to a scan line, the light-emitting units in each column are connected to a data line, at least part of the scan lines and/or the data lines are connected to first terminals of the first transistors, at least part of the scan lines and/or the data lines are connected to first terminals of the second transistors, second terminals of the first transistors and the second transistors are respectively connected to drive chip pins, control terminals of the first transistors and the second transistors are connected to a first control line.

To solve the above technical problem, the present disclosure adopts another technical solution as below. There is provided a display device, the display device includes a backlight drive circuit, the backlight drive circuit includes a plurality of light-emitting units arrayed in a matrix manner and at least first transistors and second transistors, wherein the light-emitting units in each row are connected to a scan line, the light-emitting units in each column are connected to a data line, at least part of the scan lines and/or the data lines are connected to first terminals of the first transistors, at least part of the scan lines and/or the data lines are connected to first terminals of the second transistors, second terminals of the first transistors and the second transistors are respectively connected to drive chip pins, control terminals of the first transistors and the second transistors are connected to a first control line.

To solve the above technical problem, the present disclosure adopts still another technical solution as below. There is provided a driving method of a backlight drive circuit, the backlight drive circuit comprises a plurality of light-emitting units arrayed in a matrix manner and at least first transistors and second transistors, the light-emitting units in each row are connected to a scan line, the light-emitting units in each column are connected to a data line, at least part of the scan lines and/or the data lines are connected to first terminals of the first transistors, at least part of the scan lines and/or the data lines are connected to first terminals of the second transistors, second terminals of the first transistors and the second transistors are respectively connected to drive chip pins, and control terminals of the first transistors and the second transistors are connected to a first control line; the driving method comprises:

inputting a scanning signal to the light-emitting units in a first row via the first transistor and inputting a data signal to the data lines so as to turn on the light-emitting units in the first row;

repeating the step to sequentially turn on the light emitting units in other rows.

The present disclosure has the following beneficial effects: different from the prior art, the backlight drive circuit of the present disclosure comprises a plurality of light-emitting units arrayed in a matrix manner and at least first transistors and second transistors, control terminals of each first transistor and the corresponding second transistor are connected to the same control line, at least part of scan lines and/or data lines are connected to first terminals of the first transistors, and at least part of the scan lines and/or data lines are connected to first terminals of the second transistors, so that the number of drive chip pins connected to second terminals of the first transistors and the second transistors is reduced, and accordingly, the reliability of products is improved.

FIG. 1 is a principle diagram of a backlight drive circuit in the prior art.

FIG. 2 is a structural view of a first embodiment of a backlight drive circuit of the present disclosure.

FIG. 3 is a principle diagram of a first embodiment of the backlight drive circuit of the present disclosure.

FIG. 4 is a principle diagram of a second embodiment of the backlight drive circuit of the present disclosure.

FIG. 5 is a principle diagram of a third embodiment of the backlight drive circuit of the present disclosure.

FIG. 6 is a principle diagram of a fourth embodiment of the backlight drive circuit of the present disclosure.

FIG. 7 is a principle diagram of a fifth embodiment of the backlight drive circuit of the present disclosure.

FIG. 8 is an operating time sequence diagram of the backlight drive circuit of FIG. 7 .

FIG. 9 is a flow diagram of a driving method of a backlight drive circuit of the present disclosure.

FIG. 10 is a structural view of a display device of the present disclosure.

A clear and complete description of the technical schemes in the embodiments of the present disclosure will be made below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the embodiments as recited herein are merely a part of embodiments of the present disclosure instead of all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

Please refer to FIG. 1 which is a principle diagram of a backlight drive circuit in the prior art. As shown in FIG. 1 , an area light of the direct-type backlight drive circuit comprises 34*9 zones, which means that the area light comprises 34*9 light-emitting units. The grayscale of the direct-type backlight can be locally regulated and controlled, which means that instead of being turned on at the same time, the whole area backlight is partitioned into a plurality of zones, and the brightness of each zone can be independently controlled to be matched with a liquid crystal display to display an image. Particularly, when the grayscale of the displayed image in a certain area of the liquid crystal display is low, the brightness of the corresponding zone of the direct-type backlight is decreased accordingly; and when the grayscale of the displayed image in a certain area of the liquid crystal display is high, the brightness of the corresponding zone of the direct-type backlight is increased accordingly. The brightness of the zones of the direct-type backlight dynamically changes along with grayscale changes of the image displayed by the liquid crystal display, and thus, the liquid crystal display can achieve a more excellent display effect.

A row-column scanning driving method of the backlight drive circuit in FIG. 1 comprises the following blocks: current data are input from SW 1 , and current data are input from CS 1 -CS 34 at the same time, so that the 34 light-emitting units in the first column are turned on; SW 1 is turned off, current data are input from SW 2 , current data are input from CS 1 -CS 34 at the same time, so that the 34 light-emitting units in the second column are turned on; and the light-emitting units in other columns are turned on in the same way till the light-emitting units in the whole area are turned on. After the light-emitting units in the last column are turned on, SW 1 in the first column is turned on again to repeat scanning, human eyes cannot be aware of the flickering process of the light-emitting units under the condition where the scanning speed is cover 60 HZ, and thus, it seems that the light-emitting units in the whole area are turned on. SW 1 -SW 9 are respectively connected to nine drive chip pins and are electrically connected to the positive pole of a driving electrode through the drive chip pins, CS 1 -CS 34 are respectively connected to 34 drive chip pins and are electrically connected to the negative pole of the driving electrode through the drive chip pins. Thus, 34+9=43 drive chip pins are needed for the backlight drive circuit in FIG. 1 .

As for a backlight drive circuit including m rows and n columns, m+n drive chip pins are needed in the prior art. With the increasingly higher and higher requirement for the display effect, backlight drive circuits are partitioned into more and more zones, which increases the number of drive chip pins, and consequentially, the reliability of products is reduced. As for the backlight drive circuit in the present disclosure, the number of drive chip pins is reduced by adding transistors.

Please refer to FIG. 2 which is a structural view of a first embodiment of a backlight drive circuit of the present disclosure. As shown in FIG. 2 , the backlight drive circuit comprises a plurality of light-emitting units 201 arrayed in a matrix manner and at least first transistors 202 and second transistors 203 . The light-emitting units 201 in each row are connected to a scan line 204 . The light-emitting units 201 in each column are connected to a data line 205 . At least part of the scan lines 204 and/or data lines 205 are connected to first terminals of the first transistors 202 , and at least part of the scan lines 204 and/or data lines 205 are connected to first terminals of the second transistors 203 . Second terminals of the first transistors 202 and second terminals of the second transistors 203 are respectively connected to pins of a drive chip 206 . Control terminals of each first transistor 202 and the corresponding second transistor 203 are connected to a first control line. According to the backlight drive circuit of the present disclosure, at least the first transistors and the second transistors are arranged to reduce the number of the pins of the drive chip. A detailed description is given below with reference to FIGS. 3 to 10 .

Please refer to FIG. 3 which is a principle diagram of the first embodiment of the backlight drive circuit of the present disclosure. As shown in FIG. 3 , the backlight drive circuit adopts an arrangement mode of a 9*9 matrix and comprises nine scan lines A 1 -A 9 and nine data lines K 1 -K 9 . N 1 -N 5 are five drive chip pins, and S 1 -S 9 are another nine drive chip pins. The light-emitting units in each row are connected to one scan line. The light-emitting units in each column are connected to one data line. The scan lines A 1 , A 2 , and A 3 are respectively connected to first terminals of first transistors Q 10 , Q 11 , and Q 12 . The scan lines A 4 , A 5 , and A 6 are respectively connected to first terminals of second transistors Q 13 , Q 14 , and Q 15 . The scan lines A 7 , A 8 , and A 9 are respectively and directly connected to the drive chip pins N 3 , N 4 , and N 5 instead of being connected to transistors. M 4 , M 5 and M 6 are three different first control lines.

Second terminals of the first transistor Q 10 and the second transistor Q 13 are respectively connected to the drive chip pins N 1 and N 2 . Control terminals of the first transistor Q 10 and the second transistor Q 13 are both connected to the first control line M 4 . Second terminals of the first transistor Q 11 and the second transistor Q 14 are respectively connected to the drive chip pins N 1 and N 2 . Control terminals of the first transistor Q 11 and the second transistor Q 14 are both connected to the first control line M 5 . Second terminals of the first transistor Q 12 and the second transistor Q 15 are respectively connected to the drive chip pins N 1 and N 2 . Control terminals of the first transistor Q 12 and the second transistor Q 15 are both connected to the control line M 6 . The second terminals of the two different adjacent first transistors Q 10 and Q 11 are connected to the drive chip pin N 1 , and the control terminals of the two different adjacent first transistors Q 10 and Q 11 are respectively connected to the different adjacent control lines M 4 and M 5 . The second terminals of the two different adjacent first transistors Q 11 and Q 12 are connected to the drive chip pin N 1 , and the control terminals of the two different adjacent first transistors Q 11 and Q 12 are connected to the different adjacent control lines M 5 and M 6 . The second terminals of the two different adjacent second transistors Q 13 and Q 14 are connected to the drive chip pin N 2 , and the control terminals of the two different adjacent second transistors Q 13 and Q 14 are connected to the different adjacent first control lines M 4 and M 5 . The second terminals of the two different adjacent second transistors Q 14 and Q 15 are connected to the drive chip pin N 2 , and the control terminals of the two different adjacent second transistors Q 14 and Q 15 are connected to the different adjacent first control lines M 5 and M 6 .

The nine data lines K 1 -K 9 are respectively and directly connected to the drive chip pins S 1 -S 9 , and the first control lines M 4 , M 5 , and M 6 are respectively connected to three drive chip pins. In FIG. 2 , totally 17 drive chip pins are used by the backlight drive circuit, but 18 drive chip pins are needed in the prior art, which means that compared with the prior art, the backlight drive circuit of the present disclosure omits one drive chip pin.

The operating process of the backlight drive circuit in FIG. 3 is as follows: a first control signal is input from the first control line M 4 , a scanning signal is input via the drive chip pin N 1 and is transmitted to the light-emitting units in the first row, and a data signal is input to the data lines K 1 -K 9 respectively via the drive chip pins S 1 -S 9 , so that the light-emitting units in the first row are turned on. The above step is repeated to sequentially turn on the light-emitting units in the second row, the light-emitting units in the third row, the light-emitting units in the fourth row, the light-emitting units in the fifth row, and the light-emitting units in the sixth row. Afterwards, the scanning signal is transmitted to the light-emitting units in the seventh row via the drive chip pin N 3 , and at the same time, the data signal is transmitted to the data lines K 1 -K 9 respectively via the drive chip pins S 1 -S 9 to turn on the light-emitting units in the seventh row. The step of turning on the light-emitting units in the seventh row is repeated to sequentially turn on the light-emitting units in the eighth row and the light-emitting units in the ninth row.

In this embodiment, the first terminals of the first transistors Q 10 , Q 11 , and Q 12 are respectively connected to the scan lines A 1 , A 2 and A 3 , the first terminals of the second transistors Q 13 , Q 14 , and Q 15 are respectively connected to the scan lines A 4 , A 5 , and A 6 , the second terminals of the first transistors Q 10 , Q 11 , and Q 12 are all connected to the drive chip pin N 1 , the second terminals of the second transistors Q 13 , Q 14 , and Q 15 are all connected to the drive chip pin N 2 , and thus, one drive chip pin is omitted.

Please refer to FIG. 4 which is a principle diagram of the second embodiment of the backlight drive circuit of the present disclosure. This embodiment differs from the above embodiment in the following aspects: in this embodiment, part of the scan lines are connected to first terminals of first transistors, another part of the scan lines are connected to first terminals of second transistors, part of the data lines are connected to first terminals of third transistors, and another part of the data lines are connected to first terminals of fourth transistors. Particularly, the scan lines A 1 , A 2 , and A 3 are respectively connected to first terminals of first transistors Q 10 , Q 11 , and Q 12 , the scan lines A 4 , A 5 and A 6 are respectively connected to first terminals of second transistors Q 13 , Q 14 , and Q 15 , and the scan lines A 7 , A 8 , and A 9 are respectively and directly connected to the drive chip pins N 3 , N 4 , and N 5 ; the data lines K 1 , K 2 , and K 3 are respectively connected to first terminals of third transistors Q 1 , Q 2 , and Q 3 , the data lines K 4 , K 5 , and K 6 are respectively connected to first terminals of fourth transistors Q 4 , Q 5 , and Q 6 , and the data lines K 7 , K 8 , and K 9 are respectively and directly connected to the drive chip pins S 3 , S 4 , and S 5 . Control terminals of the first transistors Q 10 and the second transistors Q 13 are connected to the first control line M 4 , the control terminals of the first transistors Q 11 and the second transistors Q 14 are connected to the first control line M 5 , and the control terminals of the first transistors Q 12 and the second transistors Q 15 are connected to the control line M 6 ; the control terminals of the third transistors Q 1 and the fourth transistors Q 4 are connected to the second control line M 1 , the control terminals of the third transistors Q 2 and the fourth transistors Q 5 are connected to the second control line M 2 , and the control terminals of the third transistors Q 3 and the fourth transistors Q 6 are connected to the second control line M 3 .

In this embodiment, 16 drive chip pins are used. Compared with the prior art, the backlight drive circuit in this embodiment can omit two drive chip pins.

Please refer to FIG. 5 which is a principle diagram of a third embodiment of the backlight drive circuit of the present disclosure. Different from the two embodiments mentioned above, in this embodiment, each scan line is connected to a first terminal of a first transistor or a second transistor, and each data line is connected to a first terminal of a third transistor or a fourth transistor. Q 10 , Q 11 , and Q 12 are first transistors, Q 13 , Q 14 , and Q 15 are second transistors, and Q 16 , Q 17 , and Q 18 are first transistors. When more rows of scan lines are included, the scan lines are configured in the same way. Every three adjacent rows of scan lines are sequentially and alternately connected to the first terminals of the first transistors and the first terminals of the second transistors, particularly, the scan lines A 1 -A 3 are connected to the first terminals of the first transistors Q 10 , Q 11 , and Q 12 , the scan lines A 4 -A 6 are connected to the first terminals of the second transistors Q 13 , Q 14 , and Q 15 , and the scan lines A 7 -A 9 are connected to the first terminals of the first transistors Q 16 , Q 17 , and Q 18 . Second terminals of the three different first transistors connected to the every three adjacent rows of scan lines are connected to the same drive chip pin, particularly, the second terminals of the first transistors Q 10 , Q 11 , and Q 12 are connected to the drive chip pin N 1 , and the second terminals of the first transistors Q 16 , Q 17 , and Q 18 are connected to the drive chip pin N 3 . Control terminals of the three different first transistors connected to every three adjacent rows of scan lines are connected to three different adjacent first control lines, particularly, the control terminals of the first transistors Q 10 , Q 11 , and Q 12 are respectively connected to the first control lines M 4 , M 5 , and M 6 , and the control terminals of the first transistors Q 16 , Q 17 , and Q 18 are respectively connected to the first control lines M 4 , M 5 , and M 6 . Second terminals of the three different second transistors connected to every three adjacent rows of scan lines are connected to the same drive chip pin, particularly, the second terminals of the second transistors Q 13 , Q 14 , and Q 15 are connected to the drive chip pin N 2 . Control terminals of the three different second transistors connected to every three adjacent rows of scan lines are connected to three different adjacent first control lines, particularly, the control terminals of the second transistors Q 13 , Q 14 , and Q 15 are respectively connected to the first control lines M 4 , M 5 , and M 6 .

Meanwhile, every three adjacent columns of data lines are sequentially and alternately connected to first terminals of the third transistors and first terminals of the fourth transistors, particularly, the data lines K 1 , K 2 , and K 3 are connected to the first terminals of the third transistors Q 1 , Q 2 , and Q 3 , the data lines K 4 , K 5 , and K 6 are connected to the first terminals of the fourth transistors Q 4 , Q 5 , and Q 6 , and the data lines K 7 , K 8 , and K 9 are connected to the first terminals of the third transistors Q 7 , Q 8 , and Q 9 . Second terminals of the three different third transistors connected to every three adjacent columns of data lines are connected to the same drive chip pin, particularly, the second terminals of the third transistors Q 1 , Q 2 , and Q 3 are connected to the drive chip pin S 1 , and the second terminals of the third transistors Q 7 , Q 8 , and Q 9 are connected to the drive chip pin S 2 . Control terminals of the three different third transistors connected to every three adjacent columns of data lines are connected to three different adjacent second control lines, particularly, the control terminals of the third transistors Q 1 , Q 2 , and Q 3 are respectively connected to the second control lines M 1 , M 2 , and M 3 , and the control terminals of the third transistors Q 7 , Q 8 , and Q 9 are respectively connected to the second control lines M 1 , M 2 , and M 3 . Second terminals of the three different fourth transistors connected to every three adjacent columns of data lines are connected to the same drive chip pin, particularly, the second terminals of the fourth transistors Q 4 , Q 5 , and Q 6 are connected to the drive chip pin S 2 . Control terminals of the three different fourth transistors connected to every three adjacent columns of data lines are connected to three different adjacent second control lines, particularly, the control terminals of the fourth transistors Q 4 , Q 5 , and Q 6 are respectively connected to the second control lines M 1 , M 2 , and M 3 .

The operating process of the backlight drive circuit in FIG. 5 is as follows: a first control signal is input from the first control line M 4 , a scanning signal is input via the drive chip pin N 1 and is transmitted to the light-emitting units in the first row, a second control signal is input via the second control line M 1 at the same time, and a data signal is input to the data lines K 1 -K 9 respectively via the drive chip pins S 1 -S 3 , so that the first light-emitting unit, the fourth light-emitting unit, and the seventh light-emitting unit in the first row are turned on; M 1 is turned off, the second control signal is input via the second control line M 2 , and the data signal is input to the data lines K 1 -K 9 respectively via the drive chip pins S 1 -S 3 , so that the second light-emitting unit, the fifth light-emitting unit, and the eighth light-emitting unit in the first row are turned on; M 2 is turned off, the second control signal is input via the second control line M 3 , the data signal is input to the data lines K 1 -K 9 respectively via the drive chip pins S 1 -S 3 , so that the third light-emitting unit, the sixth light-emitting unit, and the ninth light-emitting unit in the first row are turned on. In this way, all the light-emitting units in the first row are turned on. The above steps are repeated to sequentially turn on the light-emitting units in the second, third, fourth, fifth, sixth, seventh, eighth, and ninth rows.

In this embodiment, 12 drive chip pins are used. Compared with the prior art, the backlight drive circuit in this embodiment can omit six drive chip pins.

In this embodiment, every three adjacent rows of scan lines are sequentially and alternately connected to the first terminals of the first transistors and the first terminals of the second transistors, the second terminals of every three adjacent rows of first transistors or second transistors are connected to the same drive chip pin, every three adjacent columns of data lines are sequentially and alternately connected to the first terminals of the third transistors and the first terminals of the fourth transistors, the second terminals of every three adjacent columns of third transistors or fourth transistors are connected to the same drive chip pin, and thus, the number of the drive chip pins is reduced.

Please refer to FIG. 6 which is a principle diagram of a fourth embodiment of the backlight drive circuit of the present disclosure. As shown in FIG. 6 , in the backlight drive circuit, the number of first transistors is four, and the number of second transistors is also four; every two adjacent rows of scan lines are sequentially and alternately connected to first terminals of the first transistors and the second transistors, particularly, the scan lines A 1 and A 2 are connected to the first terminals of the first transistors Q 9 and Q 10 , the scan lines A 3 and A 4 are connected to the first terminals of the second transistors Q 11 and Q 12 , the scan lines A 5 and A 6 are connected to the first terminals of the first transistors Q 13 and Q 14 , and the scan lines A 7 and A 8 are connected to the first terminals of the second transistors Q 15 and Q 16 . When more rows of scan lines are included, the scan lines are configured in the same way. Second terminals of every two different adjacent first transistors are connected to the same drive chip pin, particularly, the second terminals of the first transistors Q 9 and Q 10 are connected to the drive chip pin N 1 , and the second terminals of the first transistors Q 13 and Q 14 are connected to the drive chip pin N 3 . Control terminals of every two different adjacent first transistors are connected to different adjacent first control lines, particularly, the control terminals of the first transistors Q 9 and Q 10 are respectively connected to the first control lines M 3 and M 4 , and the control terminals of the first transistors Q 13 and Q 14 are respectively connected to the first control lines M 3 and M 4 . Second terminals of every two different adjacent second transistors are connected to the same drive chip pin, particularly, the second terminals of the second transistors Q 11 and Q 12 are connected to the drive chip pin N 2 , and the second terminals of the second transistors Q 15 and Q 16 are connected to the drive chip pin N 4 . Control terminals of every two different adjacent second transistors are connected to different adjacent first control lines, particularly, the control terminals of the second transistors Q 11 and Q 12 are respectively connected to the first control lines M 3 and M 4 , and the control terminals of the second transistors Q 15 and Q 16 are respectively connected to the first control lines M 3 and M 4 .

Every two adjacent columns of data lines are sequentially and alternately connected to first terminals of third transistors and first terminals of fourth transistors, particularly, the data lines K 1 and K 2 are connected to the first terminals of the third transistors Q 1 and Q 2 , the data lines K 3 and K 4 are connected to the first terminals of the fourth transistors Q 3 and Q 4 , the data lines K 5 and K 6 are connected to the first terminals of the third transistors Q 5 and Q 6 , and the data lines K 7 and K 8 are connected to the first terminals of the fourth transistors Q 7 and Q 8 . When more columns of data lines are included, the data lines are configured in the same way. Second terminals of every two different adjacent third transistors are connected to the same drive chip pin, particularly, the second terminals of the third transistors Q 1 and Q 2 are connected to the drive chip pin S 1 , and the second terminals of the third transistors Q 5 and Q 6 are connected to the drive chip pin S 3 . Control terminals of every two different adjacent third transistors are connected to different adjacent second control lines, particularly, the control terminals of the third transistors Q 1 and Q 2 are respectively connected to the second control lines M 3 and M 4 , and the control terminals of the third transistors Q 13 and Q 14 are respectively connected to the second control lines M 1 and M 2 . Second terminals of every two different adjacent fourth transistors are connected to the same drive chip pin, particularly, the second terminals of the fourth transistors Q 3 and Q 4 are connected to the drive chip pin S 2 , and the second terminals of the fourth transistors Q 7 and Q 8 are connected to the drive chip pin S 4 . Control terminals of every two different adjacent fourth transistors are connected to different adjacent second control lines, particularly, the control terminals of the fourth transistors Q 3 and Q 4 are respectively connected to the second control lines M 1 and M 2 , and the control terminals of the fourth transistors Q 7 and Q 8 are respectively connected to the second control lines M 1 and M 2 .

The operating process of the backlight drive circuit in FIG. 6 is as follows: a first control signal is input from the first control line M 4 , a scanning signal is input via the drive chip pin N 1 and is transmitted to the light-emitting units in the first row, a second control signal is input via the second control line M 1 at the same time, and a data signal is input to the data lines K 1 -K 8 respectively via the drive chip pins S 1 -S 4 , so that the first light-emitting unit, the third light-emitting unit, the fifth light-emitting unit, and the seventh light-emitting unit in the first row are turned on; M 1 is turned off, the second control signal is input via the second control line M 2 , and the data signal is input to the data lines K 1 -K 8 respectively via the drive chip pins S 1 -S 4 , so that the second light-emitting unit, the fourth light-emitting unit, the sixth light-emitting unit, and the eighth light-emitting unit in the first row are turned on. In this way, all the light-emitting units in the first row are turned on. The above steps are repeated to sequentially turn on the light-emitting units in the second, third, fourth, fifth, sixth, seventh, and eighth rows.

In this embodiment, 12 drive chip pins are used. Compared with the prior art, the backlight drive circuit in this embodiment can omit four drive chip pins.

In this embodiment, every two adjacent rows of scan lines are sequentially and alternately connected to the first terminals of the first transistors and the first terminals of the second transistors, the second terminals of every two adjacent rows of first transistors or second transistors are connected to the same drive chip pin, every two adjacent columns of data lines are sequentially and alternately connected to the first terminals of the third transistors and the first terminals of the fourth transistors, the second terminals of every two adjacent columns of third transistors or fourth transistors are connected to the same drive chip pin, and thus, the number of the drive chip pins is reduced.

In FIG. 5 , every three adjacent rows of scan lines are sequentially and alternately connected to the first terminals of the first transistors and the first terminals of the second transistors, and every three adjacent columns of data lines are sequentially and alternately connected to the first terminals of the third transistors and the first terminals of the fourth transistors. In FIG. 6 , every two adjacent rows of scan lines are sequentially and alternately connected to the first terminals of the first transistors and the first terminals of the second transistors, and every two adjacent columns of data lines are sequentially and alternately connected to the first terminals of the third transistors and the first terminals of the fourth transistors. In other embodiments, the configuration that every four, five, or more adjacent rows of scan lines are sequentially and alternately connected to the first terminals of the first transistors and the first terminals of the second transistors, and every four, five, or more adjacent columns of data lines are sequentially and alternately connected to the first terminals of the third transistors and the first terminals of the fourth transistors can also be adopted, and the present disclosure has no specific limitation in this regard.

Please refer to FIG. 7 and FIG. 8 , wherein FIG. 7 is a principle diagram of a fifth embodiment of the backlight drive circuit of the present disclosure, and FIG. 8 is an operating time sequence diagram of the backlight drive circuit in FIG. 7 . In FIG. 7 , the scan lines A 1 -A 4 are respectively and directly connected to the drive chip pins N 1 -N 4 , and the data lines K 1 -K 8 are respectively and directly connected to the first terminals of the transistors Q 1 -Q 8 . In FIG. 8 , the scan line A 1 is at a high level in a time period t 3 , which corresponds to the process of inputting a high-level scanning signal to the scan line A 1 via the drive chip pin N 1 in FIG. 7 . A first high-level control signal is input to the first control line M 1 (namely the first control signal of the first control line M 1 in FIG. 8 is at a high level in a time period t 1 ), and a data signal is input via the drive chip pins S 1 -S 4 , so that the first light-emitting unit, the third light-emitting unit, the fifth light-emitting unit, and the seventh light-emitting unit in the first row are turned on; M 1 is turned off, the first control signal of M 1 is at a low level, the first high-level control signal is input to the first control line M 2 (namely the first control signal of the first control line M 2 is at a high level in a time period t 2 ), and the data signal is input via the drive chip pins S 1 -S 4 , so that the second light-emitting unit, the fourth light-emitting unit, the sixth light-emitting unit, and the eighth light-emitting unit in the first row are turned on. In this way, the eight light-emitting units in the first row are all turned on. Afterwards, A 1 is turned off, the high-level scanning signal is input to the second scan line A 2 via the drive chip pin N 2 (namely the scan line A 2 in FIG. 8 is at a high level in a time period t 6 ). The first high-level control signal is input to the first control line M 1 (namely the first control signal of the first control line M 1 in FIG. 8 is at a high level in a time period t 4 ), and the data signal is input via the drive chip pins S 1 -S 4 , so that the first light-emitting unit, the third light-emitting unit, the fifth light-emitting unit, and the seventh light-emitting unit in the first row are turned on; M 1 is turned off, the first control signal of M 1 is at a low level, the first high-level control signal is input to the first control line M 2 (namely the first control signal of the first control line M 2 is at a high level in a time period t 5 ), and the data signal is input via the drive chip pins S 1 -S 4 , so that the second light-emitting unit, the fourth light-emitting unit, the sixth light-emitting unit, and the eighth light-emitting unit in the first row are turned on. In this way, the eight light-emitting units in the second row are all turned on.

The light-emitting units in the third row and the fourth row are sequentially turned on in the same way. The light-emitting units in the four rows in FIG. 7 are all turned on in a time T, namely a cycle, and the above steps can be repeated in the next cycle.

The present disclosure has the following beneficial effects: different from the prior art, the backlight drive circuit of the present disclosure comprises a plurality of light-emitting units arrayed in a matrix manner and at least first transistors and second transistors, control terminals of each first transistor and the corresponding second transistor are connected to the same control line, at least part of scan lines and/or data lines are connected to first terminals of the first transistors, and at least part of the scan lines and/or data lines are connected to first terminals of the second transistors, so that the number of drive chip pins connected to second terminals of the first transistors and the second transistors is reduced, and accordingly, the reliability of products is improved.

Please refer to FIG. 9 which is a flow diagram of a driving method of a backlight drive circuit of the present disclosure. The driving method comprises the following steps:

Step 901 , a scanning signal is input to light-emitting units in the first row via a first transistor and a second transistor, and a data signal is input to data lines, so that the light-emitting units in the first row are turned on.

In one embodiment, referring to FIG. 6 again, a scanning signals is input via the second terminals of the first transistors Q 9 and Q 10 connected to the first and second rows scan lines A 1 and A 2 , and a first control signal is input to the first control line M 3 connected to the control terminal of the first transistor Q 9 in the first row to transmit the scanning signal to the light-emitting units in the first row; a data signal is input to the second terminals of the third transistors and the fourth transistors via the drive chip pins S 1 -S 4 , and a second control signal is input to the second control line M 1 , so that part of the light-emitting units in the first row are turned on, namely, the first light-emitting unit, the third light-emitting unit, the fifth light-emitting unit, and the seventh light-emitting unit in the first row are turned on; the second control line M 1 is turned off, and the second control signal is input to the second control line M 2 , so that the other part of the light-emitting units in the first row are turned on, namely the second light-emitting unit, the fourth light-emitting unit, the sixth light-emitting unit, and the eighth light-emitting unit in the first row are turned on. In this way, all the light-emitting units in the first row are turned on.

The step in other embodiments is similar to the above step and will no longer be described herein.

Step 902 , the above step is repeated to sequentially turn on the light-emitting units in other rows.

The present disclosure further provides a display device. The display device comprises the backlight drive circuit in any one of the embodiments mentioned above.

Please refer to FIG. 10 which is a structural view of the display device of the present disclosure. As shown in FIG. 10 , the display device 101 comprises a backlight drive circuit 1011 . The backlight drive circuit 1011 can be the backlight drive circuit in any one of the embodiments mentioned above.

The present disclosure has the following beneficial effects: different from the prior art, the backlight drive circuit of the present disclosure comprises a plurality of light-emitting units arrayed in a matrix manner and at least first transistors and second transistors, control terminals of each first transistor and the corresponding second transistor are connected to the same control line, at least part of scan lines and/or data lines are connected to first terminals of the first transistors, and at least part of the scan lines and/or data lines are connected to first terminals of the second transistors, so that the number of drive chip pins connected to second terminals of the first transistors and the second transistors is reduced, and accordingly, the reliability of products is improved.

The above are merely embodiments of the present disclosure and are not intended to limit the patent scope of the present disclosure. Any modifications of equivalent structure or equivalent process made on the basis of the contents of the description and accompanying drawings of the present disclosure or directly or indirectly applied to other related technical fields shall similarly fall within the scope of patent protection of the present disclosure.