Semiconductor devices

The present application claims priority under 35 U.S.C. 119(a) to Korean Application No. 10-2018-0077231, filed on Jul. 3, 2018, which is incorporated herein by reference in its entirety.

1. Technical Field

Embodiments of the present disclosure relate to semiconductor devices performing a self-refresh operation according to an address while a bank selection signal is generated in a power-down mode.

2. Related Art

In general, two or more semiconductor devices may be packaged to provide a package product. Each of the semiconductor devices may receive various signals from an external device through input pads and input circuits or may output internal signals through output pads and output circuits.

Delay times of the transmission paths through which the signals are transmitted may be set to be different according to characteristics of the transmission paths. In addition, synchronous semiconductor devices such as synchronous dynamic random access memory (SDRAM) devices may be synchronized with a clock signal to receive or output the signals, and delay times of the signals may be set to be different according to variations of processes, voltages, and/or temperatures (PVT). Thus, it may be necessary to appropriately adjust the delay times of the signals inputted to or outputted from the semiconductor devices.

In accordance with the present teachings, a semiconductor device includes a delay time adjustment circuit and an address input circuit. The delay time adjustment circuit adjusts a point in time when charges are supplied to internal nodes according to a voltage level of a back-bias voltage in response to a test mode signal. The delay time adjustment circuit also delays an active signal by a first delay time varying according to amounts of charge of the internal nodes to generate a bank selection signal. The address input circuit is driven by the back-bias voltage. The address input circuit receives an address in response to the bank selection signal to generate an internal address. The address input circuit delays the address by a second delay time varying according to a voltage level of the back-bias voltage.

Also in accordance with the present teachings, a semiconductor device includes a delay time adjustment circuit and an address input circuit. The delay time adjustment circuit delays a point in time when charges are supplied to internal nodes in response to the back-bias voltage whose voltage level increases in a power-down mode. The delay time adjustment circuit also delays an active signal by a first delay time varying according to amounts of charge of the internal nodes to generate a bank selection signal. The address input circuit is driven by the back-bias voltage. The address input circuit receives an address in response to the bank selection signal to generate an internal address. Moreover, the address input circuit delays the address by a second delay time varying according to a voltage level of the back-bias voltage.

FIG. 1 shows a block diagram illustrating a configuration of a semiconductor device according to an embodiment of the present disclosure.

FIG. 2 shows a circuit diagram illustrating a configuration of a test mode control circuit included in the semiconductor device of FIG. 1 .

FIG. 3 shows a circuit diagram illustrating a configuration of a delay time adjustment circuit included in the semiconductor device of FIG. 1 .

FIG. 4 shows a circuit diagram illustrating a configuration of a first delay circuit included in the delay time adjustment circuit of FIG. 3 .

FIG. 5 shows a circuit diagram illustrating a configuration of a second delay circuit included in the delay time adjustment circuit of FIG. 3 .

FIG. 6 shows a block diagram illustrating a configuration of an address input circuit included in the semiconductor device of FIG. 1 .

FIGS. 7 and 8 show timing diagrams illustrating operations of a semiconductor device according to an embodiment of the present disclosure.

FIG. 9 shows a block diagram illustrating an electronic system including the semiconductor device shown in FIGS. 1 to 8 .

Various embodiments of the present disclosure are described hereinafter with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

As illustrated in FIG. 1 , a semiconductor device 100 according to an embodiment may include a voltage adjustment circuit 10 , a test mode control circuit 20 , a delay time adjustment circuit 30 , an address input circuit 40 , and a core circuit 50 .

The voltage adjustment circuit 10 may adjust a voltage level of a back-bias voltage VBB in response to a power-down signal PD. The voltage adjustment circuit 10 may adjust a voltage level of the back-bias voltage VBB if the power-down signal PD is enabled to have a logic “high” level. The voltage adjustment circuit 10 may generate the back-bias voltage VBB whose voltage level increases if the power-down signal PD is enabled to have a logic “high” level. The power-down signal PD may be enabled to put the semiconductor device 100 in a power-down mode. A logic level of the enabled power-down signal PD may be set as a logic “high” level or a logic “low” level according to embodiment.

As used herein, a signal, such as the power-down signal PD, having a logic “low” level distinguishes from the signal when it has a logic “high” level. For example, the high level may correspond to the signal having a first voltage, and the low level may correspond to the signal having a second voltage. For some embodiments, the first voltage is greater than the second voltage. In other embodiments, different characteristics of a signal, such as frequency or amplitude, determine whether the signal has a high level or a low level. For some cases, the high and low levels of a signal represent logical binary states.

The test mode control circuit 20 may generate a test mode signal TM in response to the power-down signal PD and a test enablement signal TMEN. The test mode control circuit 20 may generate the test mode signal TM which is enabled to have a logic “high” level if the power-down signal PD is enabled to have a logic “high” level and the test enablement signal TMEN is enabled to have a logic “high” level. The test enablement signal TMEN may be enabled to put the semiconductor device 100 in a test mode for controlling a point in time when a bank selection signal BKSEL is generated to latch addresses in the power-down mode. A logic level of the enabled test mode signal TM may be set as a logic “high” level or a logic “low” level according to embodiment.

The delay time adjustment circuit 30 may adjust a point in time when charges are supplied to internal nodes (nd 31 and nd 32 of FIG. 5 ) according to a voltage level of the back-bias voltage VBB in response to the test mode signal TM. The delay time adjustment circuit 30 may delay a point in time when charges are supplied to the internal nodes (nd 31 and nd 32 of FIG. 5 ) in response to the back-bias voltage VBB whose voltage level increases in the power-down mode. The delay time adjustment circuit 30 may delay an active signal BKACT by a first delay time varying according to amounts of charge of the internal nodes (nd 31 and nd 32 of FIG. 5 ), thereby generating the bank selection signal BKSEL. The first delay time increase in proportion to a voltage level of the back-bias voltage VBB.

The address input circuit 40 may be driven by the back-bias voltage VBB. The address input circuit 40 may receive an address ADD<1:N> in response to the bank selection signal BKSEL to generate an internal address IADD<1:N>. The address input circuit 40 may vary a second delay time by which the address ADD<1:N> is delayed according to a voltage level of the back-bias voltage VBB. The address input circuit 40 may delay the address ADD<1:N> by the second delay time to generate the internal address IADD<1:N>. The address ADD<1:N> may be set as a signal that is counted (also referred to as sequentially counted) to sequentially activate a plurality of word lines (not shown) included in the core circuit 50 during a self-refresh operation in the power-down mode. The address ADD<1:N> may be set as a signal provided by an external device to activate the plurality of word lines (not shown) included in the core circuit 50 . The second delay time increase in proportion to a voltage level of the back-bias voltage VBB.

The core circuit 50 may include the plurality of word lines (not shown) and a plurality of memory cells (not shown) connected to the plurality of word lines. The core circuit 50 may sequentially activate the plurality of word lines in response to the internal address IADD<1:N> that is counted during the self-refresh operation in the power-down mode. The core circuit 50 may activate the memory cells in response to the internal address IADD<1:N>. The core circuit 50 may store data into the activated memory cells or may output data stored in the activated memory cells.

Referring to FIG. 2 , the test mode control circuit 20 may include a NAND gate NAND 21 and an inverter IV 21 .

The test mode control circuit 20 may generate the test mode signal TM which is enabled in response to the power-down signal PD and the test enablement signal TMEN. The test mode control circuit 20 may perform a logical AND operation of the power-down signal PD and the test enablement signal TMEN to generate the test mode signal TM. The test mode control circuit 20 may generate the test mode signal TM which is enabled to have a logic “high level if the power-down signal PD has a logic “high” level and the test enablement signal TMEN has a logic “high” level.

Referring to FIG. 3 , the delay time adjustment circuit 30 may include a transmission signal generation circuit 31 , a delay circuit 32 , and a logic circuit 33 .

The transmission signal generation circuit 31 may output the active signal BKACT as a first transmission signal TS 1 or a second transmission signal TS 2 in response to the test mode signal TM. The transmission signal generation circuit 31 may output the active signal BKACT as the first transmission signal TS 1 if the test mode signal TM is disabled to have a logic “low” level. The transmission signal generation circuit 31 may output the active signal BKACT as the second transmission signal TS 2 if the test mode signal TM is enabled to have a logic “high” level.

The delay circuit 32 may include a first delay circuit 310 and a second delay circuit 320 .

The first delay circuit 310 may buffer the first transmission signal TS 1 to generate a first delayed signal DS 1 . The first delay circuit 310 may delay the first transmission signal TS 1 by a predetermined delay time to generate the first delayed signal DS 1 . The predetermined delay time of the first delay circuit 310 may be set differently for different embodiments. The word “predetermined” as used herein with respect to a parameter, such as a delay time, means that a value for the parameter is determined prior to the parameter being used in a process or algorithm. For some embodiments, the value for the parameter is determined before the process or algorithm begins. In other embodiments, the value for the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

The second delay circuit 320 may buffer the second transmission signal TS 2 to generate a second delayed signal DS 2 . A delay time of the second delay circuit 320 may be set according to a voltage level of the back-bias voltage VBB. The second delay circuit 320 may delay the second transmission signal TS 2 by the first delay time to generate the second delayed signal DS 2 .

As described above, the delay circuit 32 may delay the first transmission signal TS 1 by the predetermined delay time to generate the first delayed signal DS 1 . In addition, the delay circuit 32 may delay the second transmission signal TS 2 by the first delay time, which is set according to a voltage level of the back-bias voltage VBB, to generate the second delayed signal DS 2 .

The logic circuit 33 may generate the bank selection signal BKSEL, which is enabled to have a logic “high” level if any one or both of the first and second delay signals DS 1 and DS 2 has a logic “high” level. The logic circuit 33 may perform a logical OR operation of the first and second delay signals DS 1 and DS 2 to generate the bank selection signal BKSEL.

Referring to FIG. 4 , the first delay circuit 310 may include inverters IV 31 and IV 32 and resistors R 31 and R 32 .

The first delay circuit 310 may be realized using the inverter IV 31 , the resistor R 31 , the inverter IV 32 , and the resistor R 32 , which are sequentially cascaded. The first delay circuit 310 may delay the first transmission signal TS 1 by a delay time set by the inverters IV 31 and IV 32 and the resistors R 31 and R 32 to generate the first delayed signal DS 1 . In some other embodiments, the first delay circuit 310 may be realized using an inverter chain comprised of a plurality of inverters that are cascaded.

Referring to FIG. 5 , the second delay circuit 320 may include a first buffer 321 , a first charge supply circuit 322 , a second buffer 323 , and a second charge supply circuit 324 .

The first buffer 321 may include an inverter IV 33 and a resistor R 33 . The first buffer 321 may be realized using the inverter IV 33 and the resistor R 33 , which are cascaded. The first buffer 321 may inversely buffer the second transmission signal TS 2 to output the inversely buffered signal of the second transmission signal TS 2 to the internal node nd 31 .

The first charge supply circuit 322 may include switching elements N 31 and N 32 , a first capacitor MC 1 , and a second capacitor MC 2 . The switching element N 31 may be coupled between the internal node nd 31 and the first capacitor MC 1 and may be turned on in response to the back-bias voltage VBB. The switching element N 32 may be coupled between the internal node nd 31 and the second capacitor MC 2 and may be turned on in response to the back-bias voltage VBB. The first capacitor MC 1 may be realized using a MOS-type capacitor. In such a case, a gate of the first capacitor MC 1 may be connected to the switching element N 31 , and the back-bias voltage VBB may be used as a body voltage of the first capacitor MC 1 . The first capacitor MC 1 may be realized using a PMOS transistor-type capacitor to control an amount of charge of the internal node nd 31 . In such a case, if the body voltage of the first capacitor MC 1 positively increases, then a turn-on voltage of the first capacitor MC 1 may negatively increase. The first capacitor MC 1 may be turned on if a voltage level of the internal node nd 31 increases to reach the turn-on voltage of the first capacitor MC 1 . If the turn-on voltage of the first capacitor MC 1 negatively increases, then a turn-on time of the first capacitor MC 1 may increase. The turn-on voltage of the first capacitor MC 1 may correspond to a threshold voltage of a PMOS transistor having substantially the same configuration as the first capacitor MC 1 . The second capacitor MC 2 may be realized using a MOS-type capacitor. In such a case, a gate of the second capacitor MC 2 may be connected to the switching element N 32 , and a ground voltage VSS may be used as a body voltage of the second capacitor MC 2 . The second capacitor MC 2 may be realized using an NMOS transistor-type capacitor to control an amount of charge of the internal node nd 31 .

As described above, the first charge supply circuit 322 may be connected to the internal node nd 31 to control a charging time of the internal node nd 31 according to the back-bias voltage VBB. The first charge supply circuit 322 may increase a charging time of the internal node nd 31 if the back-bias voltage VBB positively increases.

The second buffer 323 may include an inverter IV 34 and a resistor R 34 . The second buffer 323 may be realized using the inverter IV 34 and the resistor R 34 , which are cascaded. The second buffer 323 may inversely buffer a signal of the internal node nd 31 to output the inversely buffered signal of the signal of the internal node nd 31 to the internal node nd 32 . The internal node nd 32 may be a node through which the second delayed signal DS 2 is outputted.

The second charge supply circuit 324 may include switching elements N 33 and N 34 , a third capacitor MC 3 , and a fourth capacitor MC 4 . The switching element N 33 may be coupled between the internal node nd 32 and the third capacitor MC 3 and may be turned on in response to the back-bias voltage VBB. The switching element N 34 may be coupled between the internal node nd 32 and the fourth capacitor MC 4 and may be turned on in response to the back-bias voltage VBB. The third capacitor MC 3 may be realized using a MOS-type capacitor. In such a case, a gate of the third capacitor MC 3 may be connected to the switching element N 33 , and the back-bias voltage VBB may be used as a body voltage of the third capacitor MC 3 . The third capacitor MC 3 may be realized using a PMOS transistor-type capacitor to control an amount of charge of the internal node nd 32 . In such a case, if the body voltage of the third capacitor MC 3 positively increases, then a turn-on voltage of the third capacitor MC 3 may negatively increase. The third capacitor MC 3 may be turned on if a voltage level of the internal node nd 32 increases to reach the turn-on voltage of the third capacitor MC 3 . If the turn-on voltage of the third capacitor MC 3 negatively increases, then a turn-on time of the third capacitor MC 3 may increase. The turn-on voltage of the third capacitor MC 3 may correspond to a threshold voltage of a PMOS transistor having substantially the same configuration as the third capacitor MC 3 . The fourth capacitor MC 4 may be realized using a MOS-type capacitor. In such a case, a gate of the fourth capacitor MC 4 may be connected to the switching element N 34 , and the ground voltage VSS may be used as a body voltage of the fourth capacitor MC 4 . The fourth capacitor MC 4 may be realized using an NMOS transistor-type capacitor to control an amount of charge of the internal node nd 32 .

As described above, the second charge supply circuit 324 may be connected to the internal node nd 32 to control a charging time of the internal node nd 32 according to the back-bias voltage VBB. The second charge supply circuit 324 may increase a charging time of the internal node nd 32 if the back-bias voltage VBB positively increases.

Referring to FIG. 6 , the address input circuit 40 may include a latch circuit 41 and a transmission circuit 42 .

The latch circuit 41 may latch the address ADD<1:N>. The latch circuit 41 may delay the latched signal of the address ADD<1:N> by a second delay time, which is set according to a voltage level of the back-bias voltage VBB, to output the delayed signal of the latched signal of the address ADD<1:N> as a latched address LADD<1:N>. The latch circuit 41 may be realized using a general latch circuit, and a delay time of the latch circuit 41 may increase if the back-bias voltage VBB positively increases.

The transmission circuit 42 may output the latched address LADD<1:N> as the internal address IADD<1:N> in response to the bank selection signal BKSEL. The transmission circuit 42 may output the latched address LADD<1:N> as the internal address IADD<1:N> if the bank selection signal BKSEL is enabled to have a logic “high” level. The transmission circuit 42 may output the latched address LADD<1:N> as the internal address IADD<1:N> during a period that the bank selection signal BKSEL is enabled to have a logic “high” level.

Generation moments of the latched address LADD<1:N> and the bank selection signal BKSEL for the self-refresh operation without entering a test mode in the power-down mode of the semiconductor device 100 according to an embodiment are described hereinafter with reference to FIG. 7 .

First, the self-refresh operation performed when the back-bias voltage VBB of 0.9 volts is generated is described.

The voltage adjustment circuit 10 may generate the back-bias voltage VBB of 0.9 volts in response to the power-down signal PD, which is enabled to have a logic “high” level in order to put the semiconductor device 100 into the power-down mode.

The test mode control circuit 20 may generate the test mode signal TM, which is disabled to have a logic “low” level in response to the power-down signal PD having a logic “high” level and the test enablement signal TMEN having a logic “low” level.

The transmission signal generation circuit 31 of the delay time adjustment circuit 30 may output the active signal BKACT as the first transmission signal TS 1 if the test mode signal TM is disabled to have a logic “low” level.

The delay circuit 32 of the delay time adjustment circuit 30 may buffer the first transmission signal TS 1 to generate the first delayed signal DS 1 .

The logic circuit 33 of the delay time adjustment circuit 30 may perform a logical OR operation of the first delayed signal DS 1 and the second delayed signal DS 2 to generate the bank selection signal BKSEL which is enabled to have a logic “high” level at a point in time “X 2 .”

The latch circuit 41 of the address input circuit 40 may delay a latched signal of the address ADD<1:N> by a second delay time, which is set according to a voltage level of the back-bias voltage VBB, to output the delayed signal of the latched signal of the address ADD<1:N> as the latched address LADD<1:N>. In such a case, the latched address LADD<1:N> may be generated at a point in time “X 1 .”

The transmission circuit 42 of the address input circuit 40 may output the latched address LADD<1:N> as the internal address IADD<1:N> in response to the bank selection signal BKSEL at the point in time “X 2 .”

The core circuit 50 may activate one of a plurality of word lines (not shown) according to the internal address IADD<1:N> to perform the self-refresh operation of memory cells coupled to the activated word line.

Next, the self-refresh operation performed when the back-bias voltage VBB increases to have 1.2 volts is described.

The voltage adjustment circuit 10 may generate the back-bias voltage VBB of 1.2 volts in response to the power-down signal PD which is enabled to have a logic “high” level in order to put the semiconductor device 100 into the power-down mode.

The test mode control circuit 20 may generate the test mode signal TM which is disabled to have a logic “low” level in response to the power-down signal PD having a logic “high” level and the test enablement signal TMEN having a logic “low” level.

The transmission signal generation circuit 31 of the delay time adjustment circuit 30 may output the active signal BKACT as the first transmission signal TS 1 if the test mode signal TM is disabled to have a logic “low” level.

The delay circuit 32 of the delay time adjustment circuit 30 may buffer the first transmission signal TS 1 to generate the first delayed signal DS 1 .

The logic circuit 33 of the delay time adjustment circuit 30 may perform a logical OR operation of the first delayed signal DS 1 and the second delayed signal DS 2 to generate the bank selection signal BKSEL which is enabled to have a logic “high” level at the point in time “X 2 .”

The latch circuit 41 of the address input circuit 40 may delay a latched signal of the address ADD<1:N> by a second delay time, which is greater than the second delay time set when the back-bias voltage VBB is 0.9 volts, to output the delayed signal of the latched signal of the address ADD<1:N> as the latched address LADD<1:N>. In such a case, the latched address LADD<1:N> may be generated at the point in time “X 2 .”

The transmission circuit 42 of the address input circuit 40 may output the latched address LADD<1:N> as the internal address IADD<1:N> in response to the bank selection signal BKSEL at the point in time “X 2 .” In such a case, because the point in time “X 2 ” is a moment when the latched address LADD<1:N> is generated, the internal address IADD<1:N> may be generated from the latched address LADD<1:N> before or after the point in time “X 2 .”

The core circuit 50 may activate one of a plurality of word lines (not shown) according to the internal address IADD<1:N> to perform the self-refresh operation. However, the activated word line may be an undesired word line.

Next, the self-refresh operation performed when the back-bias voltage VBB increases to have 1.5 volts is described.

The voltage adjustment circuit 10 may generate the back-bias voltage VBB of 1.5 volts in response to the power-down signal PD which is enabled to have a logic “high” level in order to put the semiconductor device 100 into the power-down mode.

The test mode control circuit 20 may generate the test mode signal TM which is disabled to have a logic “low” level in response to the power-down signal PD having a logic “high” level and the test enablement signal TMEN having a logic “low” level.

The transmission signal generation circuit 31 of the delay time adjustment circuit 30 may output the active signal BKACT as the first transmission signal TS 1 if the test mode signal TM is disabled to have a logic “low” level.

The delay circuit 32 of the delay time adjustment circuit 30 may buffer the first transmission signal TS 1 to generate the first delayed signal DS 1 .

The logic circuit 33 of the delay time adjustment circuit 30 may perform a logical OR operation of the first delayed signal DS 1 and the second delayed signal DS 2 to generate the bank selection signal BKSEL which is enabled to have a logic “high” level at the point in time “X 2 .”

The latch circuit 41 of the address input circuit 40 may delay a latched signal of the address ADD<1:N> by a second delay time, which is greater than the second delay time set when the back-bias voltage VBB is 1.2 volts, to output the delayed signal of the latched signal of the address ADD<1:N> as the latched address LADD<1:N>. In such a case, the latched address LADD<1:N> may be generated at a point in time “X 3 .”

The transmission circuit 42 of the address input circuit 40 may output the latched address LADD<1:N> as the internal address IADD<1:N> in response to the bank selection signal BKSEL at the point in time “X 2 .” In such a case, because the point in time “X 2 ” is a moment before the latched address LADD<1:N> is generated, the internal address IADD<1:N> may be generated from the latched address LADD<1:N> before the point in time “X 3 .”

The core circuit 50 may activate one of a plurality of word lines (not shown) according to the internal address IADD<1:N> to perform the self-refresh operation. However, the activated word line corresponds to an undesired word line.

As described above, if a voltage level of the back-bias voltage VBB increases out of the test mode during the power-down mode, then the self-refresh operation may be unstably performed due to the delay mismatch between the latched address LADD<1:N> and the bank selection signal BKSEL.

Generation moments of the latched address LADD<1:N> and the bank selection signal BKSEL for the self-refresh operation in a test mode during the power-down mode of the semiconductor device 100 according to an embodiment are described hereinafter with reference to FIG. 8 .

First, the self-refresh operation performed when the back-bias voltage VBB of 0.9 volts is generated is described.

The voltage adjustment circuit 10 may generate the back-bias voltage VBB of 0.9 volts in response to the power-down signal PD which is enabled to have a logic “high” level in order to put the semiconductor device 100 into the power-down mode.

The test mode control circuit 20 may generate the test mode signal TM which is enabled to have a logic “high” level in response to the power-down signal PD having a logic “high” level and the test enablement signal TMEN having a logic “high” level.

The transmission signal generation circuit 31 of the delay time adjustment circuit 30 may output the active signal BKACT as the second transmission signal TS 2 if the test mode signal TM is enabled to have a logic “high” level.

The delay circuit 32 of the delay time adjustment circuit 30 may delay the second transmission signal TS 2 by a first delay time, which is set according to a voltage level of the back-bias voltage VBB, to generate the second delayed signal DS 2 .

The logic circuit 33 of the delay time adjustment circuit 30 may perform a logical OR operation of the first delayed signal DS 1 and the second delayed signal DS 2 to generate the bank selection signal BKSEL which is enabled to have a logic “high” level at a point in time “Y 2 .”

The latch circuit 41 of the address input circuit 40 may delay a latched signal of the address ADD<1:N> by a second delay time, which is set according to a voltage level of the back-bias voltage VBB, to output the delayed signal of the latched signal of the address ADD<1:N> as the latched address LADD<1:N>. In such a case, the latched address LADD<1:N> may be generated at a point in time “Y 1 .”

The transmission circuit 42 of the address input circuit 40 may output the latched address LADD<1:N> as the internal address IADD<1:N> in response to the bank selection signal BKSEL at the point in time “Y 2 .”

The core circuit 50 may activate one of a plurality of word lines (not shown) according to the internal address IADD<1:N> to perform the self-refresh operation of memory cells coupled to the activated word line.

Next, the self-refresh operation performed when the back-bias voltage VBB increases to have 1.2 volts is described.

The voltage adjustment circuit 10 may generate the back-bias voltage VBB of 1.2 volts in response to the power-down signal PD which is enabled to have a logic “high” level in order to put the semiconductor device 100 into the power-down mode.

The test mode control circuit 20 may generate the test mode signal TM which is enabled to have a logic “high” level in response to the power-down signal PD having a logic “high” level and the test enablement signal TMEN having a logic “high” level.

The transmission signal generation circuit 31 of the delay time adjustment circuit 30 may output the active signal BKACT as the second transmission signal TS 2 if the test mode signal TM is enabled to have a logic “high” level.

The delay circuit 32 of the delay time adjustment circuit 30 may delay the second transmission signal TS 2 by a first delay time, which is greater than the first delay time set when the back-bias voltage VBB is 0.9 volts, to generate the second delayed signal DS 2 .

The logic circuit 33 of the delay time adjustment circuit 30 may perform a logical OR operation of the first delayed signal DS 1 and the second delayed signal DS 2 to generate the bank selection signal BKSEL which is enabled to have a logic “high” level at a point in time “Y 4 .”

The latch circuit 41 of the address input circuit 40 may delay a latched signal of the address ADD<1:N> by a second delay time, which is greater than the second delay time set when the back-bias voltage VBB is 0.9 volts, to output the delayed signal of the latched signal of the address ADD<1:N> as the latched address LADD<1:N>. In such a case, the latched address LADD<1:N> may be generated at a point in time “Y 3 .”

The transmission circuit 42 of the address input circuit 40 may output the latched address LADD<1:N> as the internal address IADD<1:N> in response to the bank selection signal BKSEL at the point in time “Y 4 .” In such a case, the internal address IADD<1:N> may be generated from the latched address LADD<1:N> after the point in time “Y 3 .”

The core circuit 50 may activate one of a plurality of word lines (not shown) according to the internal address IADD<1:N> to perform the self-refresh operation of memory cells coupled to the activated word line.

Next, the self-refresh operation performed when the back-bias voltage VBB increases to have 1.5 volts is described.

The voltage adjustment circuit 10 may generate the back-bias voltage VBB of 1.5 volts in response to the power-down signal PD which is enabled to have a logic “high” level in order to put the semiconductor device 100 into the power-down mode.

The test mode control circuit 20 may generate the test mode signal TM which is enabled to have a logic “high” level in response to the power-down signal PD having a logic “high” level and the test enablement signal TMEN having a logic “high” level.

The transmission signal generation circuit 31 of the delay time adjustment circuit 30 may output the active signal BKACT as the second transmission signal TS 2 if the test mode signal TM is enabled to have a logic “high” level.

The delay circuit 32 of the delay time adjustment circuit 30 may delay the second transmission signal TS 2 by a first delay time, which is greater than the first delay time set when the back-bias voltage VBB is 1.2 volts, to generate the second delayed signal DS 2 .

The logic circuit 33 of the delay time adjustment circuit 30 may perform a logical OR operation of the first delayed signal DS 1 and the second delayed signal DS 2 to generate the bank selection signal BKSEL which is enabled to have a logic “high” level at a point in time “Y 6 .”

The latch circuit 41 of the address input circuit 40 may delay a latched signal of the address ADD<1:N> by a second delay time, which is greater than the second delay time set when the back-bias voltage VBB is 1.2 volts, to output the delayed signal of the latched signal of the address ADD<1:N> as the latched address LADD<1:N>. In such a case, the latched address LADD<1:N> may be generated at a point in time “Y 5 .”

The transmission circuit 42 of the address input circuit 40 may output the latched address LADD<1:N> as the internal address IADD<1:N> in response to the bank selection signal BKSEL at the point in time “Y 6 .” In such a case, the internal address IADD<1:N> may be generated from the latched address LADD<1:N> after the point in time “Y 5 .”

The core circuit 50 may activate one of a plurality of word lines (not shown) according to the internal address IADD<1:N> to perform the self-refresh operation of memory cells coupled to the activated word line.

As described above, if a voltage level of the back-bias voltage VBB increases in the test mode during the power-down mode, then the self-refresh operation may be stably performed because the delay times of the latched address LADD<1:N> and the bank selection signal BKSEL are appropriately matched.

The semiconductor device 100 described with reference to FIGS. 1 to 8 may be applied to an electronic system which includes a memory system, a graphic system, a computing system, a mobile system, or the like. For example, as illustrated in FIG. 9 , an electronic system 1000 according an embodiment may include a data storage unit 1001 , a memory controller 1002 , a buffer memory 1003 , and an input/output (I/O) interface 1004 .

The data storage unit 1001 may store data which are outputted from the memory controller 1002 or may read and output the stored data to the memory controller 1002 , according to a control signal generated from the memory controller 1002 . The data storage unit 1001 may include a nonvolatile memory that can retain their stored data even when its power supply is interrupted. The nonvolatile memory may be a flash memory such as a NOR-type flash memory or a NAND-type flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), or the like.

The memory controller 1002 may receive a command outputted from an external device (e.g., a host device) through the I/O interface 1004 and may decode the command outputted from the host device to control an operation for inputting data into the data storage unit 1001 or the buffer memory 1003 or for outputting the data stored in the data storage unit 1001 or the buffer memory 1003 . Although FIG. 9 illustrates the memory controller 1002 with a single block, the memory controller 1002 may include one controller for controlling the data storage unit 1001 , which includes nonvolatile memory, and another controller for controlling the buffer memory 1003 , which includes volatile memory.

The buffer memory 1003 may temporarily store the data to be processed by the memory controller 1002 . That is, the buffer memory 1003 may temporarily store the data which are outputted from or to be inputted to the data storage unit 1001 . The buffer memory 1003 may store the data, which are outputted from the memory controller 1002 , according to a control signal. The buffer memory 1003 may read and output the stored data to the memory controller 1002 . The buffer memory 1003 may include a volatile memory such as a dynamic random access memory (DRAM), a mobile DRAM, or a static random access memory (SRAM). The buffer memory 1003 may include the semiconductor device 100 illustrated in FIG. 1 .

The I/O interface 1004 may physically and electrically connect the memory controller 1002 to an external device (i.e., the host). Thus, the memory controller 1002 may receive control signals and data supplied from the external device (i.e., the host) through the I/O interface 1004 and may output the data generated from the memory controller 1002 to the external device (i.e., the host) through the I/O interface 1004 . That is, the electronic system 1000 may communicate with the host through the I/O interface 1004 . For some embodiments, the I/O interface 1004 may include any one of various interface protocols such as a universal serial bus (USB), a multi-media card (MMC), a peripheral component interconnect-express (PCI-E), a serial attached SCSI (SAS), a serial AT attachment (SATA), a parallel AT attachment (PATA), a small computer system interface (SCSI), an enhanced small device interface (ESDI), and an integrated drive electronics (IDE).

The electronic system 1000 may be used as an auxiliary storage device of the host or an external storage device. For some embodiments, the electronic system 1000 may include a solid state disk (SSD), a USB memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDRC) card, a memory stick card, a smart media (SM) card, a multi-media card (MMC), an embedded multi-media card (eMMC), a compact flash (CF) card, or the like.