Pixel circuit and display device

The present application claims priority to Chinese Patent Application No. 201810385565.4, titled “PIXEL CIRCUIT AND DISPLAY DEVICE”, filed on Apr. 26, 2018 with the Chinese Patent Office, which is incorporated herein by reference in its entirety.

The present disclosure relates to the field of organic light emitting display technology, and in particular to a pixel circuit and a display device.

With the continuous development of multimedia, the organic light emitting diode (OLED) display attracts great attention in the display market owing to its advantages such as a simple structure, an excellent operating temperature, a good contrast and a good view angle. The OLED displays are classified into passive matrix OLED displays and active matrix OLED displays. The active matrix OLED display is widely used because of its low power consumption. Reference is made to FIG. 1 , which is a circuit diagram of a conventional pixel circuit in an organic light emitting diode display. The conventional pixel circuit has a 3T1C structure, that is, the conventional pixel circuit includes three P-type transistors and one capacitor. When the conventional pixel circuit operates, the transistor T 3 transmits a reset voltage Vinit to an anode of the light emitting diode OLED under the control of a control signal S 1 , to reset the anode of the light emitting diode OLED. Then, the transistor T 1 is turned on under the control of a signal supplied by a scan line, and a data voltage Vdata is supplied by a data line connected to the transistor T 1 . The data voltage Vdata is stored in the capacitor C, to ensuring the stability of the current to the light emitting diode OLED in one cycle. The transistor T 2 , which serves as a current driving transistor, is used to provide a current for the light emitting diode OLED to emit light.

However, since a threshold voltage of one transistor for driving the light emitting diode to emit light in a pixel circuit of a display device is different from that of transistors in other pixel circuits of the same display device depending on a manufacturing process, the light emitting diodes in the multiple pixel circuits may have different currents flowing therethrough when the multiple pixel circuits are supplied with the same data voltage, resulting in uneven light emission of the display device.

In view of the above, a pixel circuit and a display device are provided according to the present disclosure, to solve the influence of a threshold voltage of a driving transistor on a driving current.

A pixel circuit for driving a light emitting element is provided according to the present disclosure, which includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a driving transistor, a first capacitor and a second capacitor.

A gate of the first transistor is supplied with a first driving signal, a first electrode of the first transistor is supplied with an anode voltage, and a second electrode of the first transistor is connected to a source of the driving transistor.

A gate of the second transistor is supplied with a second driving signal, a first electrode of the second transistor is supplied with a data voltage, and a second electrode of the second transistor is connected to the source of the driving transistor.

A gate of the third transistor is supplied with a third driving signal, a first electrode of the third transistor is connected to a second plate of the first capacitor, a second electrode of the third transistor is connected to a second plate of the second capacitor and a gate of the driving transistor, and a first plate of the first capacitor is supplied with a high level voltage.

A gate of the fourth transistor is supplied with a fourth driving signal, a first electrode of the fourth transistor is connected to the source of the driving transistor, and a second electrode of the fourth transistor is connected to a first plate of the second capacitor.

A gate of the fifth transistor is supplied with a fifth driving signal, a first electrode of the fifth transistor is supplied with a first low level voltage, and a second electrode of the fifth transistor is connected to the second plate of the second capacitor and the gate of the driving transistor.

A gate of the sixth transistor is supplied with a sixth driving signal, a first electrode of the sixth transistor is supplied with a second low level voltage, a second electrode of the sixth transistor is connected to a drain of the driving transistor and an anode of the light emitting element, and a cathode of the light emitting element is supplied with a cathode voltage.

A display device is further provided according to the present disclosure, which includes the above-described pixel circuit.

A pixel circuit and a display device are provided according to the present disclosure. The pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a driving transistor, a first capacitor and a second capacitor. A threshold voltage of the driving transistor is compensated through a cooperation of the transistors and the capacitors in a source following manner, such that a driving current generated by the driving transistor for driving a light emitting element to emit light is independent from the threshold voltage of the driving transistor itself, thereby compensating for a threshold drift caused by a process problem and eliminating uneven light emission of the display device, thus improving the uniformity of the light emission of the display device. In addition, the driving transistor and the anode of the light emitting element are reset through the cooperation of the transistors, thereby avoiding from grabbing a different threshold voltage after a gray scale transition, thus avoiding afterimages and insufficient brightness of the first frame after the gray scale transition.

The drawings to be used in the description of the embodiments are described briefly as follows. It is apparent that the drawings in the following description only illustrate some embodiments of the present disclosure.

FIG. 1 is a schematic structural diagram of a pixel circuit according to the conventional technology;

FIG. 2 is a schematic structural diagram of a pixel circuit according to Embodiment 1 of the present disclosure;

FIG. 3 is a diagram showing time sequences of driving signals of the pixel circuit shown in FIG. 2 ;

FIG. 4 is a schematic diagram of a current path in a phase T 1 shown in FIG. 3 ;

FIG. 5 is a schematic diagram of a current path in a phase T 2 shown in FIG. 3 ;

FIG. 6 is a schematic diagram of a current path in a phase T 3 shown in FIG. 3 ;

FIG. 7 is a schematic diagram of a current path in a phase T 4 shown in FIG. 3 ;

FIG. 8 is a schematic structural diagram of another pixel circuit according to Embodiment 1 of the present disclosure.

FIG. 9 is a schematic structural diagram of a pixel circuit according to Embodiment 2 of the present disclosure; and

FIG. 10 is a diagram showing time sequences of driving signals of the pixel circuit shown in FIG. 9 .

Embodiments of the present disclosure are described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present disclosure hereinafter. It is apparent that the described embodiments are merely some rather than all of embodiments of the present disclosure.

As described in the background part, since a threshold voltage of one transistor for driving the light emitting diode to emit light in a pixel circuit of a display device is different from that of transistors in other pixel circuits of the same display device depending on a manufacturing process, the light emitting diodes in the multiple pixel circuits may have different currents flowing therethrough when the multiple pixel circuits are supplied with the same data voltage, resulting in uneven light emission of the display device.

Based on the above, a pixel circuit and a display device are provided according to the embodiments of the present disclosure, to eliminate an influence of a threshold voltage of a driving transistor on a driving current. The embodiments of the present disclosure, which are described in detail in conjunction with FIG. 2 to FIG. 10 .

A pixel circuit according to Embodiment 1 of the present disclosure is described in detail in conjunction with FIG. 2 to FIG. 7 . Reference is made to FIG. 2 , which is a schematic structural diagram of a pixel circuit according to Embodiment 1 of the present disclosure. The pixel circuit is used for driving a light emitting element OLED, the light emitting element OLED is a light emitting diode. The pixel circuit includes a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4 , a fifth transistor M 5 , a sixth transistor M 6 , a driving transistor M 0 , a first capacitor C 1 and a second capacitor C 2 .

A gate of the first transistor M 1 is supplied with a first driving signal S 1 , a first electrode of the first transistor M 1 is supplied with an anode voltage Vpvdd, and a second electrode of the first transistor M 1 is connected to a source of the driving transistor M 0 .

A gate of the second transistor M 2 is supplied with a second driving signal S 2 , a first electrode of the second transistor M 2 is supplied with a data voltage Vdata, and a second electrode of the second transistor M 2 is connected to the source of the driving transistor M 0 .

A gate of the third transistor M 3 is supplied with a third driving signal S 3 , a first electrode of the third transistor M 3 is connected to a second plate of the first capacitor C 1 , a second electrode of the third transistor M 3 is connected to a second plate of the second capacitor C 2 and a gate of the driving transistor M 0 , and a first plate of the first capacitor C 1 is supplied with a high level voltage Vgh.

A gate of the fourth transistor M 4 is supplied with a fourth driving signal S 4 , a first electrode of the fourth transistor M 4 is connected to the source of the driving transistor M 0 , and a second electrode of the fourth transistor M 4 is connected to a first plate of the second capacitor C 2 .

A gate of the fifth transistor M 5 is supplied with a fifth driving signal S 5 , a first electrode of the fifth transistor M 5 is supplied with a first low level voltage Vgl 1 , and a second electrode of the fifth transistor M 5 is connected to the second plate of the second capacitor C 2 and the gate of the driving transistor M 0 .

A gate of the sixth transistor M 6 is supplied with a sixth driving signal S 6 , a first electrode of the sixth transistor M 6 is supplied with a second low level voltage Vgl 2 , a second electrode of the sixth transistor M 6 is connected to a drain of the driving transistor M 0 and an anode of the light emitting element OLED, and a cathode of the light emitting element is supplied with a cathode voltage Vpvee.

According to the embodiment of the present disclosure, the first capacitor C 1 is mainly used for voltage maintaining after the third transistor M 3 is turned on. The second capacitor C 2 is mainly used for voltage coupling after the fourth transistor M 4 is turned on. The first capacitor C 1 and the second capacitor C 2 are connected with each other in parallel and are independent from each other, such that the pixel circuit operates more stably.

According to the embodiment of the present disclosure, it is required to simultaneously turn on or simultaneously turn off the first transistor M 1 and the third transistor M 3 during a driving process of the pixel circuit. Therefore, in the embodiment of the present disclosure, an effective level of the first driving signal S 1 and an effective level of the third driving signal S 3 have the same time sequence. The effective level refers to a level for controlling a transistor to be turned on. By setting the effective level of the first driving signal S 1 and the effective level of the third driving signal S 3 to have the same time sequence, it is possible to control the first transistor M 1 and third transistor M 3 to be simultaneously turned on, and it is also possible to control the first transistor M 1 and the third transistor M 3 to be simultaneously turned off in a case of an ineffective level, to achieve the driving requirement that it is required to simultaneously turn on or simultaneously turn off the first transistor M 1 and the third transistor M 3 during the driving process of the pixel circuit.

According to the embodiment of the present disclosure, the first transistor M 1 and the third transistor M 3 may have the same turned-on condition or different turned-on conditions. In the embodiment of the present disclosure, in a case that the first transistor M 1 and the third transistor M 3 have the same turned-on condition, the first driving signal S 1 is the same as the third driving signal S 3 . The first driving signal S 1 and the third driving signal S 3 may be supplied from different voltage terminals via different wires. In one embodiment, the first driving signal S 1 and third driving signal S 3 may be supplied from the same voltage terminal via the same wire, thereby saving wiring ports and facilitating circuit wiring.

According to the embodiment of the present disclosure, the fifth transistor M 5 and the sixth transistor M 6 may also be configured to be simultaneously turned on or simultaneously turned off during the driving process of the pixel circuit. Therefore, in the embodiment of the present disclosure, an effective level of the fifth driving signal S 5 and an effective level of the sixth driving signal S 6 have the same time sequence. The effective level refers to a level for controlling a transistor to be turned on. By setting the effective level of the fifth driving signal S 5 and the effective level of the sixth driving signal S 6 to have the same time sequence, it is possible to control the fifth transistor M 5 and the sixth transistor M 6 to be simultaneously turned on, and it is also possible to control the fifth transistor M 5 and the sixth transistor M 6 to be simultaneously turned off in a case of an ineffective level, to achieve the driving requirement that it is required to simultaneously turn on or simultaneously turn off the fifth transistor M 5 and the sixth transistor M 6 during the driving process of the pixel circuit.

According to the embodiment of the present disclosure, the fifth transistor M 5 and the sixth transistor M 6 may have the same turned-on condition or different turned-on conditions. In the embodiment of the present disclosure, in a case that the fifth transistor M 5 and the sixth transistor M 6 have the same turned-on condition, the fifth driving signal S 5 is the same as the sixth driving signal S 6 . The fifth driving signal S 5 and the sixth driving signal S 6 may be supplied from different voltage terminals via different wires. In one embodiment, the fifth driving signal S 5 and the sixth driving signal S 6 may be supplied from the same voltage terminal via the same wire, thereby saving wiring ports and facilitating circuit wiring.

The driving process of the pixel circuit shown in FIG. 2 of the present disclosure is described in detail hereinafter. Reference is made to FIG. 3 , which is a diagram showing time sequences of the driving signals of the pixel circuit shown in FIG. 2 . Description is made by taking a case that the transistors in the embodiment of the present disclosure are P-type transistors as an example, and the fifth driving signal S 5 and the sixth driving signal S 6 are supplied from the same voltage terminal via the same wire.

Referring to FIG. 3 , according to the embodiment of the present disclosure, the driving process of the pixel circuit includes an initialization phase T 1 , a threshold grabbing phase T 2 , a data writing phase T 3 and a light emitting phase T 4 . FIG. 4 is a schematic diagram of a current path in the phase T 1 shown in FIG. 3 . FIG. 5 is a schematic diagram of a current path in the phase T 2 shown in FIG. 3 . FIG. 6 is a schematic diagram of a current path in the phase T 3 shown in FIG. 3 . FIG. 7 is a schematic diagram of a current path in the phase T 4 shown in FIG. 3 .

In the initialization phase T 1 , the first transistor M 1 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 and the sixth transistor M 6 are driven to be turned on, and the second transistor M 2 is driven to be turned off, to drive the driving transistor M 0 to be turned on.

As shown in FIG. 3 and FIG. 4 , in the initialization phase T 1 , the first driving signal S 1 , the third driving signal S 3 , the fourth driving signal S 4 , the fifth driving signal S 5 and the sixth driving signal S 6 have low levels, to respectively control the first transistor M 1 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 and the sixth transistor M 6 to be turned on. The second driving signal S 2 has a high level, to control the second transistor M 2 to be turned off.

In the initialization phase T 1 , a voltage at a first node N 1 (that is, a node at which the second electrode of the third transistor M 3 , the second electrode of the fifth transistor M 5 , the second plate of the second capacitor C 2 and the gate of the driving transistor M 0 are connected with each other) is the first low level voltage Vgl 1 , and a voltage at a second node N 2 (that is, a node at which the second electrode of the first transistor M 1 , the second electrode of the second transistor M 2 , the first electrode of the fourth transistor M 4 and the source of the driving transistor M 0 are connected with each other) is the anode voltage Vpvdd, such that the driving transistor M 0 is controlled to be turned on under the control of the first low level voltage Vgh 1 . Since a voltage at a third node N 3 (that is, a node at which the drain of the driving transistor M 0 , the second electrode of the sixth transistor M 6 and the anode of the light emitting element OLED are connected with each other) is the second low level voltage Vgl 2 , after the driving transistor M 0 is turned on, the current of the driving transistor M 0 is transmitted to the second low level voltage Vgh 2 through the third node N 3 , such that the light emitting element OLED does not emit light. In this case, the gate, the source and the drain of the driving transistor M 0 and the anode of the light emitting element OLED are all reset, thereby avoiding from grabbing a different threshold voltage after a gray scale transition, thus avoiding afterimages and insufficient brightness of the first frame after the gray scale transition.

According to the embodiment of the present disclosure, the first low level voltage Vgl 1 may be the same as the second low level voltage Vgl 2 . For the above, the first low level voltage Vgl 1 and the second low level voltage Vgl 2 may be supplied from the same voltage terminal via the same wire, to save wires. For convenience of description, description is made in assuming that the first low level voltage Vgl 1 is the same as the second low level voltage Vgl 2 , that is, both the first low level voltage Vgl 1 and the second low level voltage Vgl 2 equal to the low level voltage Vgl.

In the threshold grabbing phase T 2 , the fourth transistor M 4 , the fifth transistor M 5 and the sixth transistor M 6 are driven to be turned on, the first transistor M 1 , the second transistor M 2 and the third transistor M 3 are driven to be turned off, and the driving transistor M 0 remains in the on state.

As shown in FIG. 3 and FIG. 5 , in the threshold grabbing phase T 2 , the fourth driving signal S 4 , the fifth driving signal S 5 and the sixth driving signal S 6 have low levels, to respectively control the fourth transistors M 4 , the fifth transistor M 5 and the sixth transistor M 6 to be turned on. The first driving signal S 1 , the second driving signal S 2 and the third driving signal S 3 have high levels to respectively control the first transistor M 1 , the second transistor M 2 and the third transistor M 3 to be turned off.

In the threshold grabbing phase T 2 , the voltage at the first node N 1 and the voltage at the third node N 3 are low level voltages, and a potential at the second node N 2 is pulled down by the driving transistor M 0 which is in the on state. The driving transistor M 0 is turned off when the potential of the second node N 2 is decreased to be the sum of the low level voltage Vgl and the threshold voltage Vth of the driving transistor M 0 . In this case, the voltage at the second node N 2 is expressed by Vgl+|Vth|. Moreover, in the threshold grabbing phase T 2 , the threshold voltage of the driving transistor M 0 is compensated in the source following manner, thereby avoiding the hysteresis effect. That is, the source voltage of the driving transistor M 0 changes as the change of the gate voltage, and the driving transistor M 0 is turned off when the difference between the gate voltage and the source voltage of the driving transistor M 0 equals to the threshold voltage Vth.

In the data writing phase T 3 , the second transistor M 2 and the fourth transistor M 4 are driven to be turned on, and the first transistor M 1 , the third transistor M 3 , the fifth transistor M 5 and the sixth transistor M 6 are driven to be turned off, to drive the driving transistor M 0 to be turned off.

As shown in FIG. 3 and FIG. 6 , in the data writing phase T 3 , the second driving signal S 2 and the fourth driving signal S 4 have low levels, to respectively control the second transistor M 2 and the fourth transistor M 4 to be turned on. The first driving signal S 1 , the third driving signal S 3 , the fifth driving signal S 5 and the sixth driving signal S 6 have high levels, to respectively control the first transistor M 1 , third transistor M 3 , the fifth transistor M 5 and the sixth transistor M 6 to be turned off.

In the data writing phase T 3 , the voltage at the second node N 2 is changed to be the data voltage Vdata. Since the second capacitor C 2 performs voltage coupling after the second capacitor M 2 is turned on, such that the voltage at the first node N 1 is expressed by Vgl+Vdata−Vgl−|Vth|=Vdata−|Vth|. In this case, the data voltage is written to the gate of the driving transistor M 0 .

In the light emitting phase T 4 , the first transistor M 1 and the third transistor M 3 are driven to be turned on, and the second transistor M 2 , the fourth transistor M 4 , the fifth transistor M 5 and the sixth transistor M 6 are driven to be turned off, to drive the driving transistor M 0 to be turned on.

As shown in FIG. 3 and FIG. 7 , in the light emitting phase T 4 , the first driving signal S 1 and the third driving signal S 3 have low levels, to respectively control the first transistor M 1 and the third transistor M 3 to be turned on. The second driving signal S 2 , the fourth driving signal S 4 , the fifth driving signal S 5 and the sixth driving signal S 6 have high levels, to respectively control the second transistor M 2 , the fourth transistor M 4 , the fifth transistor M 5 and the sixth transistor M 6 to be turned off.

In the light emitting phase T 4 , since the third transistor M 3 is turned on, the voltage at the first node N 1 remains in Vdata−|Vth| by the first capacitor C 1 , and the voltage at the second node N 2 is the anode voltage Vpvdd, to turn on the driving transistor M 0 , such that the driving current is transmitted to the light emitting element OLED, to cause the light emitting element OLED to emit light. In this case, the difference between the gate voltage and the source voltage of the driving transistor M 0 is expressed by:

Vgs=Vpvdd −( V data−| Vth |)= Vpvdd−V data+| Vth|   Equation 1

Since the driving transistor M 0 operates in a saturation region in the light emitting phase T 3 , the driving current Id for driving the light emitting element OLED to emit light is determined based on the difference between the gate voltage and the source voltage of the driving transistor M 0 . Therefore, the driving current Id is expressed by:

In Equation 2, Id represents the driving current generated by the drive transistor M 0 , that is, the current for driving the light emitting element to emit light, k represents a constant, and Vgs represents the difference between the gate voltage and the source voltage of the drive transistor M 0 .

Based on the above, a threshold voltage of the driving transistor is compensated through the cooperation of the transistors and the capacitors in the source following manner, such that the driving current generated by the driving transistor for driving a light emitting element to emit light is independent from the threshold voltage of the driving transistor itself, thereby compensating for a threshold drift caused by a process problem and eliminating uneven light emission of the display device, thus improving the uniformity of the light emission of the display device. In addition, the driving transistor and the anode of the light emitting element are reset through the cooperation of the transistors, thereby avoiding from grabbing a different threshold voltage after a gray scale transition, thus avoiding afterimages and insufficient brightness of the first frame after the gray scale transition.

Referring to FIG. 2 , according to the embodiment of the present disclosure, the second low level voltage Vgl 2 may be supplied from an independent voltage terminal. The second low level voltage Vgl 2 and the first low level voltage Vgl 1 may be supplied from the same voltage terminal in a case that the second low level voltage Vgl 2 is the same as the first low level voltage Vgl 1 .

In another embodiment, reference is made to FIG. 8 , which is a schematic structural diagram of another pixel circuit according to Embodiment 1 of the present disclosure. In order to facilitate wiring and reduce wiring ports, in the embodiment of the present disclosure, the second low level voltage Vgl 2 is supplied to a terminal at which the second electrode of the fifth transistor M 5 , the second plate of the second capacitor C 2 and the gate of the driving transistor M 0 are connected with each other.

The pixel circuit shown in FIG. 8 has the same driving process as the driving process of the pixel circuit shown in FIG. 2 , except that in the initialization phase T 1 and the threshold grabbing phase T 2 , the current of the driving transistor M 0 is transmitted to the first node N 1 through the third node.

A pixel circuit according to Embodiment 2 of the present disclosure is described in detail in conjunction with FIG. 9 and FIG. 10 . Reference is made to FIG. 9 , which is a schematic structural diagram of a pixel circuit according to Embodiment 2 of the present disclosure. The pixel circuit is used to drive a light emitting element OLED, and the light emitting element OLED is a light emitting diode. The pixel circuit includes a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4 , a fifth transistor M 5 , a sixth transistor M 6 , a driving transistor M 0 , a first capacitor C and a second capacitor C 2 .

A gate of the first transistor M 1 is supplied with a first driving signal S 1 , a first electrode of the first transistor M 1 is supplied with an anode voltage Vpvdd, and a second electrode of the first transistor M 1 is connected to a source of the driving transistor M 0 .

A gate of the second transistor M 2 is supplied with a second driving signal S 2 , a first electrode of the second transistor M 2 is supplied with a data voltage Vdata, and a second electrode of the second transistor M 2 is connected to the source of the driving transistor M 0 .

A gate of the third transistor M 3 is supplied with a third driving signal S 3 , a first electrode of the third transistor M 3 is connected to a second plate of the first capacitor C 1 , a second electrode of the third transistor M 3 is connected to a second plate of the second capacitor C 2 and a gate of the driving transistor M 0 , and a first plate of the first capacitor C 1 is supplied with a high level voltage Vgh.

A gate of the fourth transistor M 4 is supplied with a fourth driving signal S 4 , a first electrode of the fourth transistor M 4 is connected to the source of the driving transistor M 0 , and a second electrode of the fourth transistor M 4 is connected to a first plate of the second capacitor C 2 .

A gate of the fifth transistor M 5 is supplied with a fifth driving signal S 5 , a first electrode of the fifth transistor M 5 is supplied with a first low level voltage Vgl 1 , and a second electrode of the fifth transistor M 5 is connected to the second plate of the second capacitor C 2 and the gate of the driving transistor M 0 .

A gate of the sixth transistor M 6 is supplied with a sixth driving signal S 6 , a first electrode of the sixth transistor M 6 is supplied with a second low level voltage Vgl 2 , and a second electrode of the sixth transistor M 6 is connected to a drain of the driving transistor M 0 and an anode of the light emitting element OLED, and a cathode of the light emitting element is supplied with a cathode voltage Vpvee.

According to the embodiment of the present disclosure, the first capacitor C 1 is mainly used for voltage maintaining after the third transistor M 3 is turned on. The second capacitor C 2 is mainly used for voltage coupling after the fourth transistor M 4 is turned on. The first capacitor C and the second capacitor C 2 are connected with each other in parallel and are independent from each other, such that the pixel circuit operates more stably.

According to the embodiment of the present disclosure, it is required to simultaneously turn on or simultaneously turn off the first transistor M 1 and the third transistor M 3 during the driving process of the pixel circuit. Therefore, in the embodiment of the present disclosure, an effective level of the first driving signal S 1 and an effective level of the third driving signal S 3 have the same time sequence. The effective level refers to a level for controlling a transistor to be turned on. By setting the effective level of the first driving signal S 1 and the effective level of the third driving signal S 3 to have the same time sequence, it is possible to control the first transistor M 1 and third transistor M 3 to be simultaneously turned on, and it is also possible to control the first transistor M 1 and the third transistor M 3 to be simultaneously turned off in a case of an ineffective level, to achieve the driving requirement that it is required to simultaneously turn on or simultaneously turn off the first transistor M 1 and the third transistor M 3 during the driving process of the pixel circuit.

According to the embodiment of the present disclosure, the first transistor M 1 and the third transistor M 3 may have the same turned-on condition or different turned-on conditions. In the embodiment of the present disclosure, in a case that the first transistor M 1 and the third transistor M 3 have the same turned-on condition, the first driving signal S 1 is the same as the third driving signal S 3 . The first driving signal S and the third driving signal S 3 may be supplied from different voltage terminals via different wires. In one embodiment, the first driving signal S and third driving signal S 3 may be supplied from the same voltage terminal via the same wire, thereby saving wiring ports and facilitating circuit wiring.

According to the embodiment of the present disclosure, the fourth transistor M 4 and the sixth transistor M 6 may also be configured to be simultaneously turned on or simultaneously turned off during the driving process of the pixel circuit. Therefore, in the embodiment of the present disclosure, an effective level of the fourth driving signal S 4 and an effective level of the sixth driving signal S 6 have the same time sequence. The effective level refers to a level for controlling a transistor to be turned on. By setting the effective level of the fourth driving signal S 4 and the effective level of the sixth driving signal S 6 to have the same time sequence, it is possible to control the fourth transistor M 4 and the sixth transistor M 6 to be simultaneously turned on, and it is also possible to control the fourth transistor M 4 and the sixth transistor M 6 to be simultaneously turned off in a case of an ineffective level, to achieve the driving requirement that it is required to simultaneously turn on or simultaneously turn off the fourth transistor M 4 and the sixth transistor M 6 during the driving process of the pixel circuit.

According to the embodiment of the present disclosure, the fourth transistor M 4 and the sixth transistor M 6 may have the same turned-on condition or different turned-on conditions. In the embodiment of the present disclosure, in a case that the fourth transistor M 4 and the sixth transistor M 6 have the same turned-on condition, the fourth driving signal S 4 is the same as the sixth driving signal S 6 . The fourth driving signal S 4 and the sixth driving signal S 6 may be supplied from different voltage terminals via different wires. In one embodiment, the fourth driving signal S 4 and the sixth driving signal S 6 may be supplied from the same voltage terminal via the same wire, thereby saving wiring ports and facilitating circuit wiring.

The driving process of the pixel circuit shown in FIG. 9 of the present disclosure is described in detail hereinafter. Reference is made to FIG. 10 , which is a diagram showing time sequences of the driving signals of the pixel circuit shown in FIG. 9 . Description is made by taking a case that the transistors in the embodiment of the present disclosure are P-type transistors as an example, and the fourth driving signal S 4 and the sixth driving signal S 6 are supplied from the same voltage terminal via the same wire. In the embodiment of the present disclosure, the second low level voltage Vgl 2 may be supplied from an independent voltage terminal. The second low level voltage Vgl 2 and the first low level voltage Vgl 1 may be supplied from the same voltage terminal in a case that the second low level voltage Vgl 2 is the same as the first low level voltage Vgl 1 .

Referring to FIG. 10 , according to the embodiment of the present disclosure, the driving process of the pixel circuit includes an initialization phase T 1 , a threshold grabbing phase T 2 , a data writing phase T 3 and a light emitting phase T 4 .

In the initialization phase T 1 , the first transistor M 1 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 and the sixth transistor M 6 are driven to be turned on, and the second transistor M 2 is driven to be turned off, to drive the driving transistor M 0 to be turned on.

In the threshold grabbing phase T 2 , the fourth transistor M 4 , the fifth transistor M 5 and the sixth transistor M 6 are driven to be turned on, the first transistor M 1 , the second transistor M 2 and the third transistor M 3 are driven to be turned off, and the driving transistor M 0 remains in the on state.

In the data writing phase T 3 , the second transistor M 2 , the fourth transistor M 4 and the sixth transistor M 6 are driven to be turned on, and the first transistor M 1 , the third transistor M 3 and the fifth transistor M 5 are driven to be turned off, to drive the driving transistor M 0 to be turned off.

In the light emitting phase T 4 , the first transistor M 1 and the third transistor M 3 are driven to be turned on, and the second transistor M 2 , the fourth transistor M 4 , the fifth transistor M 5 and the sixth transistor M 6 are driven to be turned off, to drive the driving transistor M 0 to be turned on.

It is to be noted that the four phases of the driving process of the pixel circuit according to Embodiment 2 of the present disclosure are substantially the same as the four phases of the driving process of the pixel circuit according to Embodiment 1 of the present disclosure. Therefore, the above driving process is not repeated in Embodiment 2 of the present disclosure. The difference between the driving process of the pixel circuit according to Embodiment 2 of the present disclosure and the driving process of the pixel circuit according to Embodiment 1 of the present disclosure lies in the driving manner of the sixth transistor M 6 . In Embodiment 2 of the present disclosure, the sixth transistor M 6 is controlled as follows: the sixth transistor M 6 remains in the on state in the initialization phase T 1 , the threshold grabbing phase T 2 and the data writing phase T 3 , such that the sixth transistor M 6 remains in supplying the second low level voltage Vgl 2 to the anode of the light emitting element OLED before the light emitting phase T 4 , making the light emitting element OLED be in a good dark state before the light emitting phase T 4 .

In any of the above embodiments of the present disclosure, the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5 , the sixth transistor M 6 and the driving transistor M 0 are P-type transistors. In another embodiment, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are N-type transistors, and the driving transistor is a P-type transistor, which is not specifically limited in the present disclosure.

In any of the above embodiments of the present disclosure, the high level voltage Vgh and the anode voltage Vpvdd are supplied from the same voltage terminal, that is, the high level voltage Vgh is the same as the anode voltage Vpvdd.

Correspondingly, a display device is further provided according to an embodiment of the present disclosure, which includes the above-described pixel circuit.

A pixel circuit and a display device are provided according to the present disclosure. The pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a driving transistor, a first capacitor and a second capacitor. A threshold voltage of the driving transistor is compensated through the cooperation of the transistors and the capacitors in a source following manner, such that the driving current generated by the driving transistor for driving a light emitting element to emit light is independent from the threshold voltage of the driving transistor itself, thereby compensating for a threshold drift caused by a process problem and eliminating uneven light emission of the display device, thus improving the uniformity of the light emission of the display device. In addition, the driving transistor and the anode of the light emitting element are reset through the cooperation of the transistors, thereby avoiding from grabbing a different threshold voltage after a gray scale transition, thus avoiding afterimages and insufficient brightness of the first frame after the gray scale transition.