Preamplifier circuit with floating transconductor

The present invention relates generally to preamplifier circuits, and, more particularly, to a preamplifier circuit with capacitive, positive feedback.

Clocked comparators are used for Analog-to-Digital converters (ADCs), which convert analog voltages to digital voltages by sampling the analog voltages. A preamplifier circuit is needed to prevent offset and kickback noise. A clocked preamplifier is fast due to timed operation of distinct phases in the amplification process. A high-speed preamplifier can be achieved, but at the cost of increased power. High current in the preamplifier also causes an increase in the size of its input capacitor, which leads to accuracy issues as well as additional circuit area.

It would be advantageous to have an accurate, high-speed preamplifier circuit that does not consume extra current.

The following detailed description of the preferred embodiments of the present invention will be better understood when read in conjunction with the appended drawings. The present invention is illustrated by way of example, and not limited by the accompanying figures, in which like references indicate similar elements.

FIG. 1 is a schematic block diagram of an analog-to-digital converter (ADC) in accordance with an embodiment of the present invention;

FIG. 2 is a schematic diagram of a preamplifier circuit of the ADC of FIG. 1 in accordance with an embodiment of the present invention; and

FIG. 3 is a schematic circuit diagram of the preamplifier circuit of FIG. 2 in accordance with an embodiment of the present invention.

The detailed description of the appended drawings is intended as a description of the currently preferred embodiments of the present invention and is not intended to represent the only form in which the present invention may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the present invention.

For purposes of this description, the terms “couple,” “coupling,” “coupled,” “connect,” “connecting,” or “connected” refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. The terms “directly coupled,” “directly connected,” etc., imply that the connected elements are either contiguous or connected via a conductor for the transmission of electrical signals. In addition, when describing connections to transistors or other electrical components, usage of terms like gate, drain and source means the same as gate terminal, drain terminal and source terminal, so, for instance, gate and gate terminal may be used interchangeably.

The present invention provides a preamplifier circuit that has increased, passive positive feedback at its output to boost speed without adding extra current by adding a transconductor circuit with capacitive positive feedback at the output, where the capacitive feedback circuit is active only in an amplification mode.

In one embodiment, the present invention provides a preamplifier circuit that includes an input stage and a floating transconductor. The input stage includes a first transconductor and a load connected in parallel to the first transconductor. The first transconductor is connected to an external sample-and-hold circuit for receiving first and second voltages, while the floating transconductor is connected in parallel to the input stage for receiving amplified first and second voltages. The floating transconductor outputs amplified third and fourth voltages.

In another embodiment, the first transconductor has first and second input terminals connected to an external sample-and-hold circuit for receiving the first and second voltages, and first and second output terminals for outputting the amplified first and second voltages, respectively. The floating transconductor has third and fourth input terminals for receiving the amplified first and second voltages, and third and fourth output terminals for outputting the amplified third and fourth voltages, respectively. The third and fourth output terminals are connected to the first and second output terminals at first and second nodes, respectively. The preamplifier circuit outputs a first output voltage at the first node based on the amplified first and third voltages, and a second output voltage at the second node based on the amplified second and fourth voltages.

In yet another embodiment, the first transconductor includes first and second transistors and a first tail current source. The first transistor has a gate connected to an external sample-and-hold circuit for receiving a first voltage, and a drain for providing an amplified first voltage. The second transistor has a gate connected to the external sample-and-hold circuit for receiving a second voltage, a source connected to a source of the first transistor, and a drain for providing an amplified second voltage. The first tail current source receives a biasing voltage and outputs a first tail current to the source terminals of the first and second transistors. The floating transconductor includes third and fourth transistors and a second tail current source. The third transistor has a gate connected to the drain of the second transistor for receiving the amplified second voltage, and a drain that provides an amplified third voltage. The fourth transistor has a gate connected to the drain of the first transistor for receiving the amplified first voltage, a source connected to a source of the third transistor, and a drain that provides an amplified fourth voltage. The second tail current source receives the biasing voltage and outputs a second tail current to the source terminals of the third and fourth transistors. The preamplifier circuit outputs a first output voltage based on the amplified first and third voltages, and a second output voltage based on the amplified second and fourth voltages.

Various embodiments of the present invention provide a preamplifier circuit that includes a first transconductor and a floating transconductor. The first transconductor receives first and second voltages and outputs amplified first and second voltages. The floating transconductor receives the amplified first and second voltages by way of positive feedback paths and outputs amplified third and fourth voltages. The preamplifier circuit outputs a first output voltage based on the amplified first and third voltages, and a second output voltage based on the amplified second and fourth voltages.

The first and floating transconductors store their respective offset voltages to reduce the effect of offset noise at the preamplifier circuit output terminals. The preamplifier circuit has low input capacitance, so sizes of transistors in the first and floating transconductors are reduced, which means the area consumed by the preamplifier circuit is manageable. The positive feedback paths assist in enhancing a gain of the preamplifier circuit exponentially without consuming additional current. Further, due to the low input capacitance, the preamplifier circuit consumes less power than conventional preamplifier circuits.

Referring now to FIG. 1 , a schematic block diagram of an analog-to-digital converter (ADC) 100 , in accordance with an embodiment of the present invention is shown. The ADC 100 includes a sample-and-hold circuit 102 , a preamplifier circuit 104 , and a comparator 106 .

The sample-and-hold circuit 102 receives a differential input voltage V+ and V− and a common-mode voltage Vcm. The sample-and-hold circuit 202 samples the input voltage V+ and V− and outputs a sampled differential voltage as V 1 and V 2 .

The preamplifier circuit 104 is connected to the sample-and-hold circuit 102 and receives the sampled differential voltage V 1 , V 2 . In alternative embodiments, the preamplifier circuit 104 could receive the differential voltage V 1 , V 2 from a continuous time amplifier, another preamplifier circuit, or some other analog circuitry that provides sampled analog voltages. The preamplifier circuit 104 generates and outputs an amplified differential voltage Vo− and Vo+.

The comparator 106 is connected to the preamplifier circuit 104 and receives the amplified differential voltage Vo− and Vo+. The comparator 106 compares the amplified voltage Vo− and Vo+ with a reference voltage (not shown), and outputs a digital differential voltage D 1 , D 2 .

Referring to FIG. 2 , a schematic block diagram of the sample and hold circuit 102 and the preamplifier circuit 104 in accordance with an embodiment of the present invention is shown. The sample-and-hold circuit 102 receives the differential input signal V+, V− and the common mode voltage Vcm, and outputs the sampled differential voltage V 1 , V 2 . The preamplifier circuit 104 receives the sampled differential voltage V 1 , V 2 from the sample-and-hold circuit 102 and generates the amplified differential voltage Vo− and Vo+.

The sample and hold circuit 102 includes first through fourth switches 202 a , 202 b , 204 a , and 204 b , and first and second sampling capacitors 206 a and 206 b . The first and second switches 202 a and 202 b are activated when the sample-and-hold circuit 202 is in a sampling mode per a first phase Φs of a clock signal, and the third and fourth switches 204 a and 204 b are activated when the sample-and-hold circuit 202 is in an amplification or hold mode per a second phase Φa of the clock signal (i.e., the first phase Φs of the clock signal indicates a sampling phase and the second phase Φa of the clock signal indicates an amplification phase). In the preferred embodiment, the first and second phases Φs and Φa of the clock signal are non-overlapping.

When the sample-and-hold circuit 202 operates in the sampling phase, the first and second switches 202 a and 202 b are activated (closed), and the first and second sampling capacitors 206 a and 206 b store the differential input voltage V+ and V−, respectively. When the sample-and-hold circuit 202 operates in the amplification phase, the third and fourth switches 204 a and 204 b are activated, and the first and second sampling capacitors 206 a and 206 b store the common-mode voltage Vcm. Thus, during the amplification phase, the sampled differential voltage V 1 output by the sample-and-hold circuit 202 is based on the sum of the differential input voltage V+ and the common-mode voltage Vcm, and voltage V 2 is based on the sum of the voltage V− and the common-mode voltage Vcm.

The preamplifier circuit 104 has an input stage 208 , which includes a first transconductor 210 , a load 212 , and fifth and sixth switches 214 a and 214 b . The first transconductor 210 receives the sampled differential voltage V 1 , V 2 from the sample-and-hold circuit 202 and generates a first amplified differential voltage V 1 amp− and V 1 amp+. The load is connected to the output of the first transconductor and receives the first amplified differential voltage V 1 amp−, V 1 amp+.

More particularly, the first transconductor 210 has a first, positive or non-inverting input terminal and a second, negative or inverting input terminal, which are connected to the sample-and-hold circuit 202 for receiving the sampled differential voltage V 1 and V 2 , respectively, and a first, inverting output terminal and a second, non-inverting output terminal for outputting the first amplified differential voltage V 1 amp− and V 1 amp+, respectively.

The fifth switch 214 a is connected between the first output terminal and the first input terminal, and the sixth switch 214 b is connected between the second output terminal and the second input terminal. The fifth and sixth switches 214 a and 214 b both are active/closed in the sample mode per the first phase Φs of the clock signal (and consequently inactive in the amplification mode), and thus, first and second negative feedback paths are formed during the sampling phase.

As will be explained in more detail with reference to FIG. 3 , a first offset voltage V 1 offset is present at the first output terminal when the fifth switch 214 a is activated and the first output terminal is coupled to the first input terminal. The first offset voltage V 1 offset then is stored on the first sampling capacitor 206 a . Similarly, a second offset voltage V 2 offset is present at the second output terminal when the sixth switch 312 b is activated and the second output terminal is coupled to the second input terminal. The second offset voltage V 2 offset then is stored on the second sampling capacitor 206 b . The first and second offset voltages V 1 offset and V 2 offset are based on offset noise of the preamplifier circuit 104 .

The load 212 , which preferably is a passive load, such as a resistor, capacitor or inductor, or a combination thereof, is connected to the output terminals of the first transconductor 210 by way of first and second nodes N 1 and N 2 . The amplified differential output voltage Vo−, Vo+ also is generated at the first and second nodes N 1 and N 2 . However, in alternative embodiments, the load could include circuit elements that are current or voltage controlled (and hence be an active load).

The input stage 208 also includes a floating transconductor 216 , seventh and eighth switches 218 a and 218 b , and first and second feedback capacitors 220 a and 220 b . As will be discussed in more detail below, the floating transconductor 216 employs passive positive-feedback to boost the output voltage of the preamplifier circuit 104 in the amplification mode. The first and second feedback capacitors enable the floating transconductor to operate as a positive feedback amplifier during the amplification phase Φa of the preamplifier circuit 104 . An output of the floating transconductor 216 is connected to the output of the first transconductor 210 and the input of the load 212 by way of the first and second nodes N 1 and N 2 .

More particularly, the floating transconductor 216 has a third, inverting input terminal, a fourth, non-inverting input terminal, a third, non-inverting output terminal, and a fourth, inverting terminal. The third and fourth output terminals provide a second amplified differential voltage V 2 amp+ and V 2 amp−, respectively.

The third output terminal is connected to the third input terminal by way of the seventh switch 218 a , and the fourth output terminal is connected to the fourth input terminal by way of the eighth switch 218 b . The seventh and eighth switches are controlled by the first phase Φs of the clock signal. The third output terminal also is connected to fourth input terminal by way of the second feedback capacitor 220 b , while the fourth output terminal is connected to the third input terminal by way of the first feedback capacitor 220 a . The first and second feedback capacitors 220 a and 220 b form positive feedback paths.

Further, the third output terminal (of the floating transconductor 316 ) is connected to the second output terminal (of the first transconductor 210 ) and to the load 212 by way of the second node N 2 , and the fourth output terminal (of the floating transconductor 216 ) is connected to the first output terminal (of the first transconductor 210 ) and to the load 212 by way of the first node N 1 . Thus, the first output terminal of the first transconductor 210 is connected to the third input terminal of the floating transconductor 216 by way of the first node N 1 and the first feedback capacitor 220 a , and the second output terminal of the first transconductor 210 is connected to the fourth input terminal of the floating transconductor 216 by way of the second node N 2 and the second feedback capacitor 220 b , so the floating transconductor 216 receives the first amplified voltage V 1 amp− and V 1 amp+ at its input terminals.

As previously noted, the amplified differential output voltage Vo−, Vo+ is generated at the first and second nodes N 1 and N 2 , such that Vo− is based on V 1 amp− and v 2 amp− and v 0 + is based on V 1 amp+ and V 2 amp+.

A third offset voltage V 3 offset is present at the third output terminal during the sampling phase when the seventh switch 218 a is closed and the third output terminal is coupled to the third input terminal. The third offset voltage V 3 offset is stored on the second feedback capacitor 220 b . Similarly, a fourth offset voltage V 4 offset is present at the fourth output terminal during the sampling phase when the eighth switch 218 b is closed and the fourth output terminal is coupled to the fourth input terminal. The fourth offset voltage V 4 offset is stored on the first feedback capacitor 220 a . Thus, negative feedback paths are formed in the sampling phase when the seventh and eighth switches 218 a and 218 b are closed.

As previously noted, the first feedback capacitor 220 a is connected between the fourth output terminal and the third input terminal, while the second feedback capacitor 220 b is connected between the third output terminal and the fourth input terminal. However, the first feedback capacitor 220 a also is connected to the first output terminal by way of the first node N 1 , and so receives the first amplified voltage V 1 amp− during the amplification phase. Similarly, the second feedback capacitor 220 b is connected to the second output terminal by way of the second node N 2 , so receives the first amplified voltage V 1 amp+ during the amplification phase. Thus, during the sampling phase, when Φs is active, the sample-and-hold circuit 102 and the positive-feedback capacitors 220 a and 220 b together store the combined offset voltages of the first and floating transconductors 210 and 216 .

The preamplifier circuit 104 uses the input stage 208 comprising the first transconductor 210 and the parallel connected passive or active load 212 . Offset is stored on the sampling capacitors 206 a and 206 b during the sampling phase (φs). To boost the speed of the first transconductor 210 , a floating transconductor 216 is connected in parallel therewith. This implementation avoids the need for dedicated Vcm levels. The floating transconductor 216 is self-biased from the common-mode voltage of the first transconductor 210 during the sampling phase φs. The first and floating transconductors 210 and 216 both store their own offsets, hence offset is cancelled. During amplification phase (pa, the floating transconductor 216 has positive feedback provided by the feedback capacitors 220 a and 220 b . The first transconductor 210 sees parasitic load of a next-stage and an output parasitic capacitance of the floating transconductor 216 , which is directly driven by the first transconductor 210 . This arrangement avoids capacitive division of the output due to parasitics, and hence leads to higher speed and amplification. One important aspect of this implementation is that the first and floating transconductors 210 and 216 are connected in such a way that the total current consumption is the same as in a conventional preamplifier having a single transconductor stage. The first and floating transconductors 210 and 216 also can be dynamic, even though this implementation uses fixed-bias for tail-current. The floating transconductor 216 can be smaller than the first transconductor 210 as its main purpose is to provide positive feedback to boost the gain when the output of the first transconductor 210 is still small.

Referring now to FIG. 3 , a schematic circuit diagram of the preamplifier circuit 104 in accordance with an embodiment of the present invention is shown. The first transconductor 208 includes first and second transistors 302 a and 302 b , and a first tail current source 304 . The floating transconductor 216 includes third and fourth transistors 306 a and 306 b , and a second tail current source 308 . In one embodiment, the first through fourth transistors 302 a , 302 b , 306 a and 306 b and the first and second tail current sources 304 and 308 are NMOS transistors.

The first tail current source 304 has a first terminal connected to a biasing circuit 310 for receiving a bias voltage, a second terminal connected to a second supply voltage Vss, and a third terminal that provides a first tail current TC 1 . The first transistor 302 a has a gate connected to the sample-and-hold circuit 102 for receiving the first differential voltage V 1 , a source connected to the third terminal of the first tail current source 304 for receiving the first tail current TC 1 , and a drain that provides the amplified first voltage V 1 amp−. The second transistor 302 b has a gate connected to the sample-and-hold circuit 102 for receiving the first differential voltage V 2 , a source connected to the third terminal of the first tail current source 304 for receiving the first tail current TC 1 , and a drain that provides the first amplified voltage V 1 amp+.

The second tail current source 308 has a first (gate) terminal connected to the biasing circuit 310 for receiving the bias voltage, a second (source) terminal that receives the second supply voltage Vss, and a third (drain) terminal that provides a second tail current TC 2 . The third transistor 306 a has a gate connected to the drain of the second transistor 302 b by way of the second feedback capacitor 220 b (and the second node N 2 ) for receiving the amplified voltage V 1 amp+, a source connected to the third terminal of the second tail current source 308 for receiving the second tail current TC 2 , and a drain that provides the second amplified voltage V 2 amp−. The fourth transistor 306 b has a gate connected to the drain of the first transistor 302 a by way of the first feedback capacitor 220 a (and the first node N 1 ) for receiving the amplified first voltage V 1 amp−, a source connected to the third (drain) terminal of the second tail current source 308 for receiving the second tail current TC 2 , and a drain that provides the second amplified voltage V 2 amp+. In one embodiment, the first tail current TC 1 has a higher value (preferred) than the second tail current TC 2 . This is achieved by using different values of current-mirror ratio formed by TC 1 , TC 2 and biasing circuit from the biasing circuit 310 .

The fifth switch 214 a has a gate that receives the first phase Φs of the clock signal, and source and drain terminals connected to the drain and gate terminals of the first transistor 302 a so that the first offset voltage V 1 offset is transmitted from the drain of the first transistor 302 a to its gate by way of the fifth switch 214 a . The sixth switch 214 b has a gate that receives the first phase Φs of the clock signal, and source and drain terminals connected to the drain and gate terminals of the second transistor 302 b so that the second offset voltage V 2 offset is transmitted from the drain of the second transistor 302 b to its gate by way of the sixth switch 214 b.

The seventh switch 218 a has a gate that receives the first phase Φs of the clock signal, and source and drain terminals connected to the drain and gate terminals of the fourth transistor 306 b for transmitting the third offset voltage V 3 offset from the drain of the fourth transistor 306 b to its gate by way of the seventh switch 218 a . The eighth switch 218 b has a gate that receives the first phase Φs of the clock signal, and source and drain terminals connected to the drain and gate terminals of the third transistor 306 a for transmitting the fourth offset voltage V 4 offset from the drain of the third transistor 306 a to its gate by way of the eighth switch 218 b . In one embodiment, the fifth through eighth switches 214 a , 214 b , 218 a , and 218 b are PMOS transistors.

During the sampling phase Φs, the fifth through eighth switches 214 a , 214 b , 218 a , and 218 b are activated/closed. Thus, the first and second offset voltages V 1 offset and V 2 offset are stored on the first and second sampling capacitors 206 a and 206 b , respectively. The first and second sampling capacitors 206 a and 206 b also store the differential input voltage V+ and V−, respectively. Similarly, the third and fourth offset voltages V 3 offset and V 4 offset are stored on the first and second feedback capacitors 220 a and 220 b , respectively.

During the amplification phase Φa, the third and fourth switches 204 a and 204 b ( FIG. 2 ) are activated/closed. Thus, the common-mode voltage Vcm is provided to the first and second sampling capacitors 206 a and 206 b . The first sampling capacitor 206 a stores the common-mode voltage Vcm, the input voltage V+ and the first offset voltage V 1 offset , such that V 1 equals the sum of Vcm, V+ and V 1 offset . Similarly, the second sampling capacitor 206 b stores the common-mode voltage Vcm, the analog voltage V− and the second offset voltage V 2 offset , such that V 2 equals the sum of Vcm, V− and V 2 offset . Thus, the gate of the first transistor 302 a receives the sum of V+, V 1 offset , and Vcm and outputs the amplified first voltage V 1 amp− at its drain terminal. Similarly, the gate of the second transistor 302 b receives the sum of V−, V 2 offset and Vcm and outputs the amplified voltage V 1 amp+ at its drain terminal.

The third transistor 306 a receives the amplified voltage V 1 amp+ at its gate by way of the second feedback capacitor 220 b , and outputs the amplified voltage V 2 amp− at its drain terminal. The fourth transistor 306 b receives the amplified voltage V 1 amp− at its gate by way of the first feedback capacitor 220 a , and outputs the amplified voltage V 2 amp+ at its drain terminal. The output voltage Vo− generated at the first node N 1 is thus a sum of the amplified voltages V 1 amp− and V 2 amp−, and the output voltage Vo+ generated at the second node N 2 is a sum of the amplified voltages V 1 amp+ and V 2 amp+.

The preamplifier circuit 104 can be implemented using a different arrangement of transistors or different types of transistors. For example, in an alternate implementation, the first through fourth transistors 302 a , 302 b , 306 a , and 306 b may comprise PMOS transistors, and the fifth through eighth switches 214 a , 214 b , 218 a , and 218 b may comprise NMOS transistors.

The first and second feedback capacitors 220 a and 220 b provide passive positive feedback, so the speed and gain of the preamplifier circuit 104 are enhanced without consuming additional power. Thus, the preamplifier circuit 104 may be implemented in high-resolution and high-speed ADCs.

The first through fourth offset voltages V 1 offset -V 4 offset are stored on the first and second sampling capacitors 206 a and 206 b , and the first and second feedback capacitors 220 a and 220 b . The differential output voltage Vo−, Vo+ is amplified based on the first through fourth offset voltages V 1 offset -V 4 offset , which reduces the effects of offset and kickback noise. Further, due to the reduction in the effect of offset and kickback noise, errors in the first and second digital signals D 1 and D 2 ( FIG. 1 ) at various process corners are reduced. Thus, the ADC 100 performs well at high operating frequencies.

Due to the absence of sampling capacitors in the preamplifier circuit 104 , the amplitudes of the output voltage Vo−, Vo+ is not affected by capacitive division. Thus, the operating speed of the preamplifier circuit 104 is improved as compared to conventional preamplifier circuits.

The floating transconductor 216 is driven by the first transconductor 210 . Hence, the floating transconductor 216 is not connected to any circuitry that is external to the preamplifier circuit 104 . Further, the first and second transistors 302 a and 302 b and the third and fourth transistors 306 a and 306 b are biased by two independent current sources (i.e., the first and second tail current sources 304 and 308 , respectively) and not by a common current source. Thus, the input capacitance of the preamplifier circuit 104 is lower than the input capacitance of conventional preamplifier circuits. Additionally, the first through fourth transistors 302 a , 302 b , 306 a , and 306 b may be smaller than the transistors in conventional preamplifier circuits. Thus, the preamplifier circuit 104 consumes less chip area.

The present invention provides passive positive-feedback at the output of the preamplifier using the floating transconductor stage, which boosts the speed of the preamplifier circuit through novel biasing and output capturing circuitry.

It will be understood by those of skill in the art that the same functions may be performed by different arrangements of transistors that may operate using either high active or low active signals. Therefore, variations in the arrangement of some of the transistors described above should not be considered to depart from the scope of the present invention.

While various embodiments of the present invention have been illustrated and described, it will be clear that the present invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the present invention, as described in the claims.