Integrated silicon carbide diode rectifier circuits

This application claims priority to and is a continuation-in-part of U.S. Patent Application Ser. No. 62/582,752, filed on Nov. 7, 2017 entitled Integrated Silicon Carbide Diode Rectifier Circuits which is hereby incorporated by reference in its entirety.

This invention was made with government support by the U.S. Department of Energy, advanced data logging electronics for high pressure and temperature subsurface, contact No. DE-SC0017131 (SBIR/STTR-GTC-0024). The government has certain rights in the invention.

Not Applicable.

A portion of the disclosure of this patent document contains material which is subject to intellectual property rights such as but not limited to copyright, trademark, and/or trade dress protection. The owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent files or records but otherwise reserves all rights whatsoever.

1. Field of the Invention

The present invention relates to improvements in electrical circuits. More particularly, the invention relates to integrated silicon carbide diode rectifier circuits. In particular, the present invention relates specifically to an isolation diode from a JFET style N-channel to a P-Substrate.

2. Description of the Known Art

As will be appreciated by those skilled in the art, electrical circuits are known in various forms. Patents disclosing information relevant to circuit designs include:

U.S. Pat. No. 7,688,117, issued to Krasowski on Mar. 30, 2010 entitled N channel JFET based digital logic gate structure; U.S. Pat. No. 7,935,601, issued to Neudeck on May 3, 2011 entitled Method for providing semiconductors having self-aligned ion implant; U.S. Pat. No. 8,416,007, issued to Krasowski on Apr. 9, 2013 entitled N channel JFET based digital logic gate structure; U.S. Pat. No. 8,841,698, issued to Neudeck on Sep. 23, 2014 entitled Method for providing semiconductors having self-aligned ion implant; U.S. Pat. No. 9,013,002, issued to Spry on Apr. 21, 2015 entitled Iridium interfacial stack (IRIS). Each of these patents is hereby expressly incorporated by reference in their entirety.

From these prior references it may be seen that these prior art patents are very limited in their teaching and utilization, and an improved circuit is needed to overcome these limitations.

The present invention is directed to an improved integrated silicon carbide diode rectifier circuits using an isolation diode. In accordance with one exemplary embodiment of the present invention, a isolation diode is provided from a JFET N-channel to a P-Substrate. These and other objects and advantages of the present invention, along with features of novelty appurtenant thereto, will appear or become apparent by reviewing the following detailed description of the invention.

In the following drawings, which form a part of the specification and which are to be construed in conjunction therewith, and in which like reference numerals have been employed throughout wherever possible to indicate like parts in the various views:

FIG. 1 shows a Two-Half-Wave Diode Rectifier for Center-Tap Transformer Schematic and associated waveforms.

FIG. 2 shows an Integrated Full-wave Rectifier with Floating P-Substrate and associated waveforms.

As shown in FIG. 1 of the drawings, one exemplary embodiment of the present invention is generally shown using an isolation diode from the JFET N-channel to the P-Substrate which allows designing integrated diode rectification circuits. The P-Substrate connection must be made with respect to the chosen isolation transformer. It is not clear yet if integrated diode rectifier circuits provide a cost/reliability/performance trade-off with discrete SiC Schottky diodes on a ceramic substrate, however some integrated diode rectification topologies are considered next.

For a two-phase AC input from a center-tap transformer, two-half-wave rectifiers can be integrated on the same chip if the P-Substrate connection is tied to the transformer's center tap as shown in FIG. 1 . The gate-to-channel diodes are shown vertically and the channel-to-substrate isolation diode is drawn horizontally. Note that the P-Substrate is tied to the center-tap of the 2-Phase transformer. Optionally in this circuit the P-Substrate may float with little effect on rectification function or performance.

In a similar fashion, a single-phase transformer output can be full-wave rectified, however in this case the P-Substrate must be allowed to float as shown in FIG. 2 . Again, rectifying gate-to-channel diodes are drawn vertically and channel-to-substrate isolation diodes are drawn horizontally.

Due to the biasing of the P-Substrate it is not possible to rectify AC to a DC supply and use the DC supply to energize JFET logic on the same die.

From the foregoing, it will be seen that this invention well adapted to obtain all the ends and objects herein set forth, together with other advantages which are inherent to the structure. It will also be understood that certain features and subcombinations are of utility and may be employed without reference to other features and subcombinations. This is contemplated by and is within the scope of the claims. Many possible embodiments may be made of the invention without departing from the scope thereof. Therefore, it is to be understood that all matter herein set forth or shown in the accompanying drawings is to be interpreted as illustrative and not in a limiting sense.

When interpreting the claims of this application, method claims may be recognized by the explicit use of the word ‘method’ in the preamble of the claims and the use of the ‘ing’ tense of the active word. Method claims should not be interpreted to have particular steps in a particular order unless the claim element specifically refers to a previous element, a previous action, or the result of a previous action. Apparatus claims may be recognized by the use of the word ‘apparatus’ in the preamble of the claim and should not be interpreted to have ‘means plus function language’ unless the word ‘means’ is specifically used in the claim element. The words ‘defining,’ ‘having,’ or ‘including’ should be interpreted as open ended claim language that allows additional elements or structures. Finally, where the claims recite “a” or “a first” element of the equivalent thereof, such claims should be understood to include incorporation of one or more such elements, neither requiring nor excluding two or more such elements.