Digital double sampling circuit

1. Field of the Invention

The present invention generally relates to digital double sampling (DDS), and more particularly to a DDS circuit with dark-sun prevention scheme adaptable to an image sensor.

2. Description of Related Art

Digital double sampling (DDS) is a scheme commonly used to cancel read-out path offset and comparator delay variation when reading out photodiode information of an image sensor such as a complementary metal-oxide-semiconductor (CMOS) image sensor.

When taking a picture of sun light, the sun image may ordinarily become dark due to electron overflow of the photodiode. A clamp scheme is thus proposed to clamp an image output node of a pixel circuit at a certain level during the reset phase. However, the clamp scheme may disadvantageously affect the signal transfer from the photodiode to the image output node during the reset phase in case of no sun-light or low-light condition, and column fixed pattern noise (CFPN) may therefore occur.

For the reason that conventional clamp scheme could not effectively solve the sun-light phenomenon in the DDS system, a need has thus arisen to propose a novel scheme to overcome drawbacks of the conventional DDS system.

In view of the foregoing, it is an object of the embodiment of the present invention to provide a digital double-sampling (DDS) circuit capable of preventing dark-sun condition and column fixed pattern noise (CFPN).

According to one embodiment, a digital double-sampling (DDS) circuit includes a pixel circuit of an image sensor, a comparator, a reset switch, an analog-to-digital converter (ADC), a subtractor and a clamp circuit. The comparator has a first input node connected to a ramp voltage and a second input node connected to an image output node of the pixel circuit via a capacitor. The reset switch is connected between the first input node and the second input node for resetting the capacitor. The ADC is coupled to receive a comparison output of the comparator, the ADC including a counter that counts while the ramp voltage is ramping, thereby generating a reset-ADC value in a reset phase and generating a signal-ADC value in a signal phase. The subtractor subtracts the reset-ADC value from the signal-ADC value, thereby resulting in a difference value representing a sampled output. The clamp circuit generates a clamp voltage at the image output node. In the reset phase, the clamp circuit is disabled after the capacitor finishes resetting but before the ramp voltage begins ramping.

FIG. 1 shows a circuit diagram illustrating a digital double-sampling (DDS) circuit with dark-sun prevention scheme adaptable to a pixel circuit of an image sensor according to one embodiment of the present invention;

FIG. 2 shows exemplary timing diagrams of pertinent signals of the comparator and the ADC of FIG. 1 ;

FIG. 3 shows exemplary timing diagrams of pertinent signals of the DDS circuit according to one embodiment of the present invention; and

FIG. 4 shows exemplary timing diagrams of pertinent signals of the DDS circuit adopting a scheme different from the embodiment of the present invention as shown in FIG. 3 .

FIG. 1 shows a circuit diagram illustrating a digital double-sampling (DDS) circuit 100 with dark-sun prevention scheme adaptable to a pixel circuit 11 of an image sensor, such as a complementary metal-oxide-semiconductor (CMOS) image sensor, according to one embodiment of the present invention. Although four-transistor (4T) pixel architecture is exemplified in FIG. 1 , it is appreciated that the pixel circuit 11 may have pixel architecture other than the 4T architecture.

Specifically, the pixel circuit 11 may include a transfer transistor m 1 , a reset transistor m 2 , a source follower transistor m 3 and a row selection transistor m 4 , which may, for example, be implemented by N-type metal-oxide-semiconductor (NMOS) transistors. As exemplified in FIG. 1 , a photodiode PD is connected between the transfer transistor m 1 and ground. The transfer transistor m 1 is connected between a floating diffusion (FD) node and the photodiode PD, and a gate of the transfer transistor m 1 is connected to a transfer signal Tx. The reset transistor m 2 is connected between power VDD and the FD node, and a gate of the reset transistor m 2 is connected to a reset signal Rx. The source follower transistor m 3 and the row selection transistor m 4 are connected in series between the power VDD and an image output node VL, and gates of the source follower transistor m 3 and the row selection transistor m 4 are connected to the FD node and a selection signal SEL, respectively. A first bias transistor m 5 may be connected between the image output node VL and the ground, and a gate of the bias transistor m 5 is connected to a first bias voltage VB.

The DDS circuit 100 of the embodiment may include a comparator 12 , which may, for example, be implemented by an operational amplifier. Specifically, a first input node (e.g., positive (+) input node) of the comparator 12 is connected to a ramp voltage Vramp, and a second input node (e.g., negative (−) input node VI) of the comparator 12 is connected to the image output node VL (of the pixel circuit 11 ) via a capacitor Ci. A reset switch SW, controlled by a reset enable signal rst_en is connected between the negative input node VI and the positive (+) input node of the comparator 12 for resetting the capacitor Ci disposed between the image output node VL the and (the negative (−) input node VI of) the comparator 12 .

The DDS circuit 100 of the embodiment may include an analog-to-digital converter (ADC) 13 , which receives a comparison output dout of the comparator 12 , and accordingly generates a digital-counter signal, by a counter 131 that counts while the ramp voltage Vramp is ramping (down). The generated digital-counter signal represents an amount of time during which the comparison output dout is asserted (e.g., high level). FIG. 2 shows exemplary timing diagrams of pertinent signals of the comparator 12 and the ADC 13 of FIG. 1 . In a reset phase of the digital double-sampling performed by the DDS circuit 100 , the counter 131 of the ADC 13 may use m bits to count from 0 to 2 m −1 (e.g., 8-bit counter that counts from 0 to 255), and may generate a reset-ADC value. On the other hand, in a signal phase of the digital double-sampling performed by the DDS circuit 100 , the counter 131 of the ADC 13 may use n bits (m and n are positive integers and m≤n) to count from 0 to 2 n −1 (e.g., 10-bit counter that counts from 0 to 1023) and may generate a signal-ADC value. It is noted that the ADC 13 may include a memory 132 for temporarily storing the generated reset-ADC value and the generated signal-ADC value.

The DDS circuit 100 of the embodiment may include a subtractor with digital-detection (subtractor hereinafter) 14 configured to subtract the reset-ADC value from the signal-ADC value, thereby resulting in a difference value representing a sampled output of the photodiode signal. In the embodiment, if the reset-ADC value is equal to a maximum count (i.e., 2 m −1) of the reset phase, indicating a sun-light condition, an output of the subtractor 14 (i.e., sampled output of the DDS circuit 100 ) is then set to a maximum count (i.e., 2 n −1) of the signal phase, thereby preventing dark-sun result; otherwise the difference value is outputted as the sampled output.

The DDS circuit 100 of the embodiment may include a clamp circuit 15 that is connected between the power VDD and the image output node VL. In the embodiment, the clamp circuit 15 may include a clamp transistor m 6 (e.g., NMOS transistor) configured to generate (for example, at a source thereof) a clamp voltage at the image output node VL. A gate of the clamp transistor m 6 is controlled by a clamp enable signal bs_en. For example, when the clamp enable signal bs_en is asserted (e.g., high level), the clamp circuit 15 is enabled to generate the clamp voltage; otherwise, no clamp voltage is generated. The clamp circuit 15 may further include a second bias transistor m 7 that is connected between the power VDD and the clamp transistor m 6 , and a gate of the second bias transistor m 7 is connected to a second bias voltage vbs, where the second bias transistor m 7 and the clamp transistor m 6 are connected in series between the power VDD and the image output node VL.

FIG. 3 shows exemplary timing diagrams of pertinent signals of the DDS circuit 100 according to one embodiment of the present invention. For better demonstrating aspect of the embodiment, only sun-light condition is shown. Specifically, in the reset phase (time period t 0 -t 6 ) of the digital double-sampling performed by the DDS circuit 100 , firstly the reset signal Rx, the reset enable signal rst_en and the clamp enable signal bs_en become asserted (e.g., high level) at time t 0 to reset the pixel circuit 11 , to reset the comparator 12 , and to enable the clamp circuit 15 , respectively. At time t 1 , the pixel circuit 11 finishes resetting when the reset signal Rx is de-asserted (e.g., low level). Accordingly, the image output node VL is clamped to the clamp voltage Δ V 1 (generated by the clamp circuit 15 ).

At time t 2 , the capacitor Ci finishes resetting (by the reset switch SW) when the reset enable signal rst_en is de-asserted (e.g., low level). Subsequently, at time t 3 , the clamp circuit 15 is disabled when the clamp enable signal bs_en is de-asserted (e.g., low level). Therefore, the image output node VL is no longer clamped. Moreover, the image output node VL drops to 0 volt due to sun-light condition. Afterward, from time t 4 to t 5 , the ramp voltage Vramp is ramping (down) with an amount of Δ V 2 while the counter 131 of the ADC 13 counts from 0 to N 1 (i.e., 2 m −1), and the reset-ADC value is thus generated (by the ADC 13 ). According to one aspect of the embodiment, in the reset phase, the clamp circuit 15 is disabled (at t 3 ) after the capacitor Ci finishes resetting (at t 2 ) but before the ramp voltage Vramp begins ramping (at t 4 ).

In the signal phase (time period t 6 -t 8 ) of the digital double-sampling performed by the DDS circuit 100 , firstly the transfer transistor m 1 becomes enabled at time t 6 to transfer image signal from the photodiode PD to the FD node. Afterward, from time t 7 to t 8 , the ramp voltage Vramp is ramping (down) with an amount of Δ V 3 while the counter 131 of the ADC 13 counts from 0 to N 2 (i.e., 2 n −1), and the signal-ADC value is thus generated (by the ADC 13 ). In one exemplary embodiment, Δ V 2 is about 20% of Δ V 3 , and N 1 /N 2 may be 255/1023 in case of 10-bit ADC resolution.

According to the embodiment set forth above, in the reset phase (particularly during time period t 3 -t 6 ), as the clamp circuit 15 is disabled, no output current I 1 (of the clamp circuit 15 ) flows toward the image output node VL due to unexpectedly turning on the clamp circuit 15 . Accordingly, the output current I 2 of the row selection transistor m 4 would not be affected (e.g., be decreased), particularly in case of no sun-light or low-light condition, and column fixed pattern noise (CFPN) would not occur due to threshold voltage difference between the clamp transistor m 6 and the second bias transistor m 7 (of the clamp circuit 15 ).

FIG. 4 shows exemplary timing diagrams of pertinent signals of the DDS circuit 100 adopting a scheme different from the embodiment of the present invention as shown in FIG. 3 , and only sun-light condition is shown. Compared to FIG. 3 , the clamp circuit 15 is enabled (with asserted clamp enable signal bs_en) until the end of the reset phase. Accordingly, the image output node VL is clamped at a certain level during the reset phase. However, the clamp circuit 15 may be turned on slightly, an output current I 1 (of the clamp circuit 15 ) thus flows toward the image output node VL. This output current I 1 makes the output current I 2 of the row selection transistor m 4 reduced and affects the signal transfer from the photodiode PD to the image output node VL during the reset phase in case of no sun-light or low-light condition. Accordingly, column fixed pattern noise (CFPN) may occur due to threshold voltage difference between the clamp transistor m 6 and the second bias transistor m 7 (of the clamp circuit 15 ).

Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.