Thin film transistor array substrate and display panel

The subject matter herein generally relates to a thin film transistor array substrate and a display panel using the thin film transistor array substrate.

Dual gates in a thin film transistor array substrate can reduce a number of data lines, thus data signal driving chip, and its cost, can be reduced. In a conventional thin film transistor array substrate, scan lines are usually made of a first conductive layer, common lines are made of a second conductive layer. The common line overlaps with two adjacent scan lines to form two equal parasitic capacitances.

However, if there is an offset between the first conductive layer and the second conductive layer during the fabrication process, the common line and the adjacent two scan lines have different overlapping areas, resulting in unequal capacitance values of the parasitic capacitances. Thus, the charging rates of two adjacent columns of pixels are affected. If there are differences in the charging rates of the two adjacent columns of pixels, the display panel will include bright and dark stripes, and the display quality may be greatly reduced, especially in high-resolution products.

Therefore, there is room for improvement in the art.

Implementations of the present disclosure will now be described, by way of example only, with reference to the attached figures.

FIG. 1 is a cross-sectional view showing an embodiment of a display panel.

FIG. 2 is a circuit diagram showing a thin film transistor array substrate of the display panel of FIG. 1 .

FIG. 3 is a cross-sectional view showing the thin film transistor array substrate of FIG. 2 .

FIG. 4 is a plan view showing portion of the thin film transistor array substrate of FIG. 2 .

It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the exemplary embodiments described herein. However, it will be understood by those of ordinary skill in the art that the exemplary embodiments described herein may be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the exemplary embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features of the present disclosure.

The term “comprising” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series, and the like. The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references can mean “at least one”. The term “circuit” is defined as an integrated circuit (IC) with a plurality of electric elements, such as capacitors, resistors, amplifiers, and the like.

FIG. 1 shows an embodiment of a display panel 100 . The display panel 100 includes a color filter (CF) substrate 102 , a liquid crystal layer 103 , and a thin film transistor (TFT) substrate 101 . The color filter substrate 102 and the thin film transistor array substrate 101 are on opposite sides of the liquid crystal layer 103 , and the liquid crystal layer 103 is between the color filter substrate 102 and the thin film transistor array substrate 101 .

In FIG. 2 , the thin film transistor array substrate 101 includes scan line pairs 10 , data lines D 1 -Dn, and common lines L 1 -Ln, wherein n is an integer which is larger than or equal to 2. Each scan line 10 includes a first scan line G 1 and a second scan line G 2 both extending in a first direction X. Each data line and each common line extend in a second direction Y intersecting with the first direction X. The data lines D 1 -Dn and the common lines L 1 -Ln are alternately arranged in the first direction X.

In FIG. 2 , the thin film transistor array substrate 101 further includes pixel units 40 . Each pixel unit 40 is between two adjacent common lines L(n−1)-Ln. The pixel units 40 are arranged in a matrix of rows and columns. Each pixel unit 40 is electrically connected to one first scan line G 1 , one second scan line G 2 , one data line Dn, and one common line Ln. The pixel units 40 of one column share one data line Dn and one common line Ln.

Taking one pixel unit 40 as an example, the connection and positional relationship between the first scan line G 1 , the second scan line G 2 , the common line Ln, and the pixel unit 40 are as follows.

As shown in FIG. 2 , each pixel unit 40 includes a first sub-pixel 42 and a second sub-pixel 44 on opposite sides of one pair of scan lines 10 . The first sub-pixel 42 is electrically connected to the first scan line G 1 , the data line Dn, and the common line Ln. The second sub-pixel 44 is electrically connected to the second scan line G 2 , the data line Dn, and the common line Ln. The first sub-pixel 42 and the second sub-pixel 44 are on opposite sides of, and electrically connected to, one of the data lines D 1 -Dn.

In FIG. 2 and FIG. 4 , the first sub-pixel 42 includes a first thin film transistor M 1 , a first sub-pixel electrode 422 (shown in FIG. 4 ), and a first liquid crystal capacitor C 3 and a first storage capacitor C 4 . The first thin film transistor M 1 includes a gate electrode 421 (shown in FIG. 4 ), a source electrode 423 (shown in FIG. 4 ), and a drain electrode 425 (shown in FIG. 4 ). The gate electrode 421 is electrically connected to the first scan line G 1 . The source electrode 423 is electrically connected to the data line Dn. The first liquid crystal capacitor C 3 includes two ends (a and b). The first storage capacitor C 4 includes two ends (c and d). The drain electrode 425 is electrically connected to the end a of the first liquid crystal capacitor C 3 and the end c of the first storage capacitor C 4 .

In the present embodiment, the data line Dn transmits a signal to the first thin film transistor M 1 . The common line Ln transmits a signal to the first thin film transistor M 1 . The first scan line G 1 controls the first thin film transistor M 1 to receive the data signal. Thus, charging and discharging of the first liquid crystal capacitor C 3 are controlled. The first storage capacitor C 4 is used to maintain a potential difference between two ends of the first liquid crystal capacitor C 3 to prevent current leakage from the first liquid crystal capacitor C 3 .

In FIG. 2 , the second sub-pixel 44 includes a second thin film transistor M 2 , a second sub-pixel electrode 442 (shown in FIG. 4 ), a second liquid crystal capacitor C 5 , and a second storage capacitor C 6 . The second thin film transistor M 2 includes a gate electrode 441 (shown in FIG. 4 ), a source electrode 443 (shown in FIG. 4 ), and a drain electrode 445 (shown in FIG. 4 ). The gate electrode 441 is electrically connected to the second scan line G 2 . The source electrode 443 is electrically connected to the data line Dn. The second liquid crystal capacitor C 5 includes two ends (e and f). The second storage capacitor C 6 includes two ends (g and h). The drain electrode 445 is electrically connected to the end e of the second liquid crystal capacitor and the end g of the second storage capacitor.

In this embodiment, the data line Dn transmits a signal to the second thin film transistor M 2 . The common line Ln transmits a signal to the second thin film transistor M 2 , and the second scan line G 2 controls the second thin film transistor M 2 to receive the data signal. Thus, charging and discharging of the second liquid crystal capacitor C 5 are controlled. The second storage capacitor C 6 is used to maintain a potential difference between two ends of the second liquid crystal capacitor C 5 to prevent current leakage from the second liquid crystal capacitor C 5 .

Referring to FIGS. 2 and 3 , the thin film transistor array substrate 101 includes a substrate 61 , a first conductive layer 62 , an insulating layer 63 , a first electrode layer 67 , a semiconductor layer 64 , a second conductive layer 65 , a protective layer 66 , and a second electrode layer 68 .

In the present embodiment, the substrate 61 includes components of the thin film transistor array substrate 101 on the substrate 61 . The substrate 61 may be transparent, and made of materials such as glass, transparent plastic, or the like.

Referring to FIGS. 3 and 4 , in the present embodiment, the first conductive layer 62 defines the gate electrode 421 of the first thin film transistor M 1 , the gate electrode 441 of the second thin film transistor M 2 , the first scan line G 1 , and the second scan line G 2 . In the present embodiment, the formation of the first conductive layer 62 also forms connection lines connecting the first scan line G 1 to the gate electrode 421 and connection lines connecting the second scan line G 2 to the gate electrode 441 .

In FIG. 3 , the insulating layer 63 covering the first conductive layer 62 is formed on a side of the first conductive layer 62 away from the substrate 61 . The insulating layer 63 serves as a gate insulating layer of the first thin film transistor M 1 and the second thin film transistor M 2 .

The first electrode layer 67 is formed on a side of the insulating layer 63 away from the substrate 61 . The first electrode layer 67 forms the first sub-pixel electrode 422 (shown in FIG. 4 ) and the second sub-pixel electrode 442 (shown in FIG. 4 ).

The semiconductor layer 64 is formed on a region of the insulating layer 63 without the first electrode layer 67 . The second conductive layer 65 is formed on a side of the semiconductor layer 64 away from the substrate 61 , a side of the insulating layer 63 away from the substrate 61 , and a side of the first electrode layer 67 away from the substrate 61 . The second conductive layer 65 forms the source electrode 423 of the first thin film transistor M 1 , the drain electrode 425 of the first thin film transistor M 1 , the source electrode 443 of the second thin film transistor M 2 , the drain electrode 445 of the second thin film transistor M 2 , the common lines L 1 -Ln, and the data lines D 1 -Dn.

In the present embodiment, the source electrode 423 and the drain electrode 425 are located above the gate electrode 421 of the first thin film transistor M 1 . The source electrode 443 and the drain electrode 445 of the first thin film transistor M 2 are located above the gate electrode 441 of the second thin film transistor M 2 . The semiconductor layer 64 is located below the source electrode 423 and the drain electrode 425 and also below the source electrode 443 and the drain electrode 445 of the second thin film transistor M 2 .

In FIG. 4 , the source electrode 423 and the source electrode 443 are electrically connected to the data line Dn. The drain electrode 425 is electrically connected to the first sub-pixel electrode 422 . The drain electrode 445 is electrically connected to the second sub-pixel electrode 442 . The first thin film transistor M 1 and the second thin film transistor M 2 are on opposite sides of the data line Dn. The first thin film transistor 442 and the second thin film transistor M 2 are on opposite sides of the first scan line G 1 and the second scan line G 2 . The common line Ln is between two adjacent data lines D(n−1)-Dn.

In FIG. 3 , the semiconductor layer 64 and the second conductive layer 65 are covered by a protective layer 66 . The protective layer 66 defines a via hole 662 to couple the common line Ln to the common electrode 50 .

The protective layer 66 covers the semiconductor layer 64 and the second conductive layer 65 .

The second electrode layer 68 is formed on a side of the protective layer 66 away from the substrate 61 , and the second electrode layer 68 forms the common electrode 50 . The common electrode 50 is on opposite sides of both the first sub-pixel electrode 422 and the second sub-pixel electrode 442 . The common electrode 50 is electrically connected to the common line Ln by the via hole 662 , and the common line Ln sends signals to the common electrode 50 .

In the present embodiment, the material of the protective layer 66 and the insulating layer 63 may be silicon nitride or other insulating materials. The material of the first electrode layer 67 and the second electrode layer 68 may be Indium Tin Oxide (ITO) or other various conductive materials which are also transparent.

Slits 52 are defined in the common electrode 50 corresponding to the first sub-pixel electrode 422 and the second sub-pixel electrode 442 to form common electrode strips 54 . A parallel electric field is formed between the common electrode strips 54 and the first sub-pixel electrode 422 and is also formed between the common electrode strips 54 and the second sub-pixel electrode 442 . The liquid crystal molecules in the liquid crystal layer 103 are thus driven to rotate.

Referring to both FIGS. 2 and 4 , the common electrode strips 54 are arranged to be substantially parallel to the common line Ln and the data line Dn, and are substantially perpendicular to the scan lines 10 . In the present embodiment, the common electrode strips 54 are arranged at substantially equal intervals, but are not limited thereto.

In FIGS. 3 and 4 , the common electrode 50 is formed with a slit 52 that is not corresponding to the common electrode line Ln. The common electrode 50 is electrically connected to the common electrode line Ln by the via hole 662 in the protective layer 66 .

In FIG. 2 , the common line Ln is perpendicular to, and crosses, one pair of scan lines 10 . A first parasitic capacitance C 1 is formed between each common line Ln and each first scan line G 1 . A second parasitic capacitance C 2 is formed between each common line Ln and each second scan line G 2 .

In FIG. 4 , the common line Ln includes bridges 36 . Each bridge 36 crosses one pair of scan lines 10 , e.g., first scan line G 1 and second scan line G 2 , and each bridge 36 overlaps with a portion of one scan line 10 extending along the second direction Y. The projection of each bridge 36 on the substrate 61 overlaps with projections of both the first scan line G 1 and the second scan line G 2 on the substrate 61 .

In the present embodiment, the portion of the first scan line G 1 that overlaps with the bridge 36 is equal in size to the area in which the second scan line G 2 overlaps with the bridge 36 . Even when there is a deviation between the first conductive layer 62 and the second conductive layer 65 , the value of the first parasitic capacitance C 1 always equal to the value of the second parasitic capacitance C 2 in each pixel unit 40 .

In the present embodiment, a size of the common line Ln in the first direction X is defined as a line width of the common line Ln. A size of the first scan line G 1 along the second direction Y is defined as a line width of the first scan line G 1 . A size of the second scan line G 2 in the second direction Y is defined as a line width of the second scan line G 2 .

In FIG. 4 , a line width of the common electrode line Ln when crossing one scan lines 10 is greater than a line width of other portions of the common line Ln. A line width of the portion of the first scan line G 1 that overlaps with the bridge 36 is less than a line width of other portions of the first scan line G 1 . A line width of the portion of the second scan line G 2 that overlaps with the bridge 36 is less than a line width of other portions of the second scan line G 2 . Thus, the size of the bridge 36 in the second direction Y can be reduced.

Referring to FIG. 2 , the display panel 100 operates as follows. In a row of pixel units 40 , the gate electrodes 421 of the first thin film transistors M 1 of all the first sub-pixels 42 are electrically connected to one first scan line G 1 . When a sufficiently large positive voltage is applied to the first scan line G 1 , the first thin film transistors M 1 electrically connected to the first scan line G 1 are turned on. At this time, the first sub-pixel electrodes 422 on the first scan line G 1 are electrically connected to the adjacent data line Dn, and data signals are applied by the data line Dn. The first sub-pixel electrodes 422 on the first scan line G 1 are thereby charged to an appropriate voltage. At this time, a parallel electric field is formed between the first sub-pixel electrode 422 and the opposite common electrode 50 to rotate the liquid crystal molecules in the liquid crystal layer 103 .

Then, a sufficiently large negative voltage is applied to the first scan line G 1 , and the first thin film transistors M 1 electrically connected to the first scan line G 1 are turned off. In the meantime, the charge is stored on the first liquid crystal capacitor C 3 .

Then, the second scan line G 2 is activated, and the second thin film transistors M 2 electrically connected to the second scan line G 2 are turned on. The second sub-pixel electrodes 442 on the second scan line G 2 are electrically connected to the adjacent data line Dn, and the data signals are applied by the data line Dn to the the second scan lines G 2 . The second sub-pixel electrodes 442 are charged to an appropriate voltage. At this time, a parallel electric field is formed between the second sub-pixel electrodes 442 and the opposite common electrode 50 to rotate the liquid crystal molecules in the liquid crystal layer 103 .

In the present embodiment, the portion of the first scan line G 1 that overlaps with the bridge 36 is equal to the portion of the second scan line G 2 that overlaps with the bridge 36 . Thus, the value of the first parasitic capacitance C 1 between each first scan line G 1 and the bridge 36 is equal to the value of the second parasitic capacitance C 2 between each second scan line G 2 and the bridge 36 . Thus, the charging rate of the first sub-pixel electrodes 422 on one scan line G 1 is substantially the same as the charging rate of the second sub-pixel electrodes 442 on the second scan line G 2 . The resistance-capacitance phenomenon caused by the common line Ln does not occur and light and dark streaks, caused by the differences in brightness of two adjacent columns in the display image, are absent. The display quality of the display panel 100 is improved.

It is to be understood, even though information and advantages of the present exemplary embodiments have been set forth in the foregoing description, together with details of the structures and functions of the present exemplary embodiments, the disclosure is illustrative only. Changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the present exemplary embodiments to the full extent indicated by the plain meaning of the terms in which the appended claims are expressed.