Electronic component

1. Field of the Invention

The present invention relates to an electric component.

2. Description of Related Art

Known electronic components include an element body of a rectangular parallelepiped shape, a plurality of external electrodes, and a plurality of internal electrodes (see, for example, Japanese Unexamined Patent Publication No. H8-107038). The element body includes a pair of principle surfaces opposing each other, a pair of end surfaces opposing each other, and a pair of side surfaces opposing each other. The plurality of external electrodes is disposed at each end portion of the element body in a direction in which the pair of end surfaces opposes each other. The external electrode includes a conductive resin layer covering the entire end surface.

An object of one aspect of the present invention is to provide an electronic component that suppresses occurrence of a crack in an element body and a solder fillet.

An electronic component according to one aspect includes an element body of a rectangular parallelepiped shape, a plurality of external electrodes, and an internal conductor. The element body includes a first principle surface arranged to constitute a mounting surface, a second principle surface opposing the first principle surface in a first direction, a pair of side surfaces opposing each other in a second direction, and a pair of end surfaces opposing each other in a third direction. The plurality of external electrodes is disposed at both end portions of the element body in the third direction. The internal conductor is exposed to a corresponding end surface of the pair of end surface. The external electrodes include a conductive resin layer formed on the corresponding end surface. A thickness of the conductive resin layer gradually increases from the second principle surface toward the first principle surface in the first direction. The conductive resin layer includes a thickest portion having a maximum thickness at a position near the first principle surface in the first direction.

In a case where an electronic component is solder-mounted on an electronic device, an external force applied onto the electronic component from the electronic device sometimes may act as a stress on the element body. The electronic device includes, for example, a circuit board or an electronic component. The external force acts on the element body from a solder fillet formed at the solder-mounting, through the external electrode. In this case, a crack may occur in the element body.

In the one aspect, the conductive resin layer is formed on the end surface. Therefore, even in a case where an external force acts on the electronic component from the electronic device, the conductive resin layer absorbs the external force. Consequently, the one aspect suppresses occurrence of a crack in the element body.

In a case where compressive stress or tensile stress due to thermal shock acts on the solder fillet, a crack may occur in the solder fillet. The compressive stress or tensile stress due to thermal shock tends to be concentrated in the region near the first principle surface of the solder fillet. Hereinafter, the compressive stress or tensile stress due to thermal shock is simply referred to as “thermal shock stress”.

In the one aspect, the conductive resin layer absorbs the thermal shock stress. The thickness of the conductive resin layer gradually increases from the second principle surface toward the first principle surface in the first direction, and the thickest portion is located near the first principle surface in the first direction. The thickest portion of the conductive resin layer is very effective in absorbing the thermal shock stress. Therefore, the thermal shock stress tends not to be concentrated in the region near the first principle surface of the solder fillet. Consequently, the one aspect suppresses occurrence of a crack in the solder fillet.

In the one aspect, the thickest portion may be located nearer to the first principle surface than the second principle surface in the first direction. In this configuration, the conductive resin layer effectively absorbs the thermal shock stress concentrated in the region near the first principle surface of the solder fillet. Therefore, this configuration is reliably suppresses the occurrence of the crack in the solder fillet.

In the one aspect, the thickest portion may be located nearer to the first principle surface than the second principle surface, in the first direction in the conductive resin layer. In this configuration, the conductive resin layer effectively absorbs the thermal shock stress concentrated in the region near the first principle surface of the solder fillet. Therefore, this configuration is reliably suppresses the occurrence of the crack in the solder fillet.

In the one aspect, the conductive resin layer may cover a ridge portion located between the first principle surface and the corresponding end surface. A portion of the conductive resin layer covering the ridge portion may be located nearer to the first principle surface than the thickest portion in the first direction. The portion of the conductive resin layer covering the ridge portion may have a thickness smaller than the thickness of the thickest portion.

In this configuration, a curvature radius of the portion covering the ridge portion of the conductive resin layer is large, as compared with a configuration in which the thickness of the portion covering the ridge portion of the conductive resin layer is equal to or greater than the thickness of the thickest portion. In this configuration, therefore, a curvature radius of the ridge portion near the first principle surface of the external electrode corresponding to the ridge portion of the element body is also large. Consequently, this configuration improves flexibility of the electronic component and further reliably suppresses the occurrence of the crack in the element body.

Since the thickness of the portion covering the ridge portion of the conductive resin layer is smaller than the thickness of the thickest portion, the solder tends to accumulate at a position corresponding to the ridge portion of the external electrode. Therefore, this configuration can provide a solder pool.

In a case in which an element is described as covering another element, the element may directly cover the other element or indirectly cover the other element.

In the one aspect, the conductive resin layer may cover a region near the first principle surface of the corresponding end surface. A region between the element body and the conductive resin layer may act as a path through which moisture infiltrates. In a case where moisture infiltrates from the region between the element body and the conductive resin layer, durability of the electronic component decreases. This configuration includes few paths through which moisture infiltrates, as compared with a configuration in which the conductive resin layer covers the entire end surface. Therefore, this configuration improves moisture resistance reliability.

In the one aspect, the conductive resin layer may cover a region near the corresponding end surface of the first principle surface. In a case where the external force applied onto the electronic component from the electronic device tends to act on a region near an end surface of the first principle surface of the element body. In a configuration in which the conductive resin layer covers the region near the end surface of the first principle surface, the external force applied onto the electronic component from the electronic device tends not to act on the element body. Therefore, this configuration suppresses the occurrence of the crack in the element body.

In the one aspect, the external electrodes may include a sintered metal layer formed on the corresponding end surface to be connected to the internal conductor. The sintered metal layer may include a first region covered with the conductive resin layer and a second region exposed from the conductive resin layer. In this configuration, the sintered metal layer is favorably in contact with the internal conductor. This allows reliable electrical connection between the external electrode and the internal conductor. The conductive resin layer includes a conductive material and a resin. The conductive material includes, for example, metal powder. The resin includes, for example, a thermosetting resin. Electric resistance of the conductive resin layer is larger than electric resistance of the sintered metal layer. In a case where the sintered metal layer includes the second region, the second region is electrically connected to the electronic device without passing through the conductive resin layer. Therefore, this configuration suppresses an increase in equivalent series resistance (ESR) even in a case where the external electrode includes the conductive resin layer.

In the one aspect, the external electrodes may include a plating layer covering the conductive resin layer and the second region of the sintered metal layer. In this configuration, the electronic component can be solder-mounting on the electronic device. The second region of the sintered metal layer is electrically connected to the electronic device via the plating layer. Therefore, this configuration further suppresses the increase in the ESR.

The present invention will become more fully understood from the detailed description given hereinafter and the accompanying drawings which are given by way of illustration only, and thus are not to be considered as limiting the present invention.

Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

FIG. 1 is a perspective view of a multilayer capacitor according to a first embodiment;

FIG. 2 is a side view of the multilayer capacitor according to the first embodiment;

FIG. 3 is a view illustrating a cross-sectional configuration of the multilayer capacitor according to the first embodiment;

FIG. 4 is a view illustrating a cross-sectional configuration of an external electrode;

FIG. 5 is a view illustrating a cross-sectional configuration of the multilayer capacitor according to the first embodiment;

FIG. 6 is a view illustrating a cross-sectional configuration of the multilayer capacitor according to the first embodiment;

FIG. 7 is a plan view illustrating an element body, a first electrode layer, and a second electrode layer;

FIG. 8 is a side view illustrating the element body, the first electrode layer, and the second electrode layer;

FIG. 9 is an end view illustrating the element body, the first electrode layer, and the second electrode layer;

FIG. 10 is a view illustrating a mounted structure of the multilayer capacitor according to the first embodiment;

FIG. 11 is a plan view of a multilayer feedthrough capacitor according to a second embodiment;

FIG. 12 is a plan view of the multilayer feedthrough capacitor according to the second embodiment;

FIG. 13 is a side view of the multilayer feedthrough capacitor according to the second embodiment;

FIG. 14 is an end view of the multilayer feedthrough capacitor according to the second embodiment;

FIG. 15 is a view illustrating a cross-sectional configuration of the multilayer feedthrough capacitor according to the second embodiment;

FIG. 16 is a view illustrating a cross-sectional configuration of the multilayer feedthrough capacitor according to the second embodiment;

FIG. 17 is a view illustrating a cross-sectional configuration of the multilayer feedthrough capacitor according to the second embodiment; and

FIG. 18 is a side view illustrating an element body, a first electrode layer, and a second electrode layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same elements or elements having the same functions are denoted with the same reference numerals and overlapped explanation is omitted.

First Embodiment

A configuration of a multilayer capacitor C 1 according to a first embodiment will be described with reference to FIGS. 1 to 9 . FIG. 1 is a perspective view of the multilayer capacitor according to the first embodiment. FIG. 2 is a side view of the multilayer capacitor according to the first embodiment. FIGS. 3, 5, and 6 are views illustrating a cross-sectional configuration of the multilayer capacitor according to the first embodiment. FIG. 4 is a view illustrating a cross-sectional configuration of an external electrode. FIG. 7 is a plan view illustrating an element body, a first electrode layer, and a second electrode layer. FIG. 8 is a side view illustrating the element body, the first electrode layer, and the second electrode layer. FIG. 9 is an end view illustrating the element body, the first electrode layer, and the second electrode layer. In the first embodiment, an electronic component is, for example, the multilayer capacitor C 1 .

As illustrated in FIG. 1 , the multilayer capacitor C 1 includes an element body 3 of a rectangular parallelepiped shape and a plurality of external electrodes 5 . In the present embodiment, the multilayer capacitor C 1 includes a pair of external electrodes 5 . The pair of external electrodes 5 is disposed on an outer surface of the element body 3 . The pair of external electrodes 5 is spaced apart from each other. The rectangular parallelepiped shape includes a rectangular parallelepiped shape in which corners and ridges are chamfered, and a rectangular parallelepiped shape in which the corners and ridges are rounded.

The element body 3 includes a pair of principal surfaces 3 a and 3 b opposing each other, a pair of side surfaces 3 c opposing each other, and a pair of end surfaces 3 e opposing each other. The pair of principal surfaces 3 a and 3 b and the pair of side surfaces 3 c have a rectangular shape. The direction in which the pair of principal surfaces 3 a and 3 b opposes each other is a first direction D 1 . The direction in which the pair of side surfaces 3 c opposes each other is a second direction D 2 . The direction in which the pair of end surfaces 3 e opposes each other is a third direction D 3 . The multilayer capacitor C 1 is solder-mounted on an electronic device. The electronic device includes, for example, a circuit board or an electronic component. The principal surface 3 a of the multilayer capacitor C 1 opposes the electronic device. The principal surface 3 a is arranged to constitute a mounting surface. The principal surface 3 a is the mounting surface.

The first direction D 1 is a direction orthogonal to the respective principal surfaces 3 a and 3 b and is orthogonal to the second direction D 2 . The third direction D 3 is a direction parallel to the respective principal surfaces 3 a and 3 b and the respective side surfaces 3 c , and is orthogonal to the first direction D 1 and the second direction D 2 . The second direction D 2 is a direction orthogonal to the respective side surfaces 3 c . The third direction D 3 is a direction orthogonal to the respective end surfaces 3 e . In the first embodiment, a length of the element body 3 in the third direction D 3 is larger than a length of the element body 3 in the first direction D 1 , and larger than a length of the element body 3 in the second direction D 2 . The third direction D 3 is a longitudinal direction of the element body 3 .

The pair of side surfaces 3 c extends in the first direction D 1 to couple the pair of principal surfaces 3 a and 3 b . The pair of side surfaces 3 c also extends in the third direction D 3 . The pair of end surfaces 3 e extends in the first direction D 1 to couple the pair of principal surfaces 3 a and 3 b . The pair of end surfaces 3 e also extends in the second direction D 2 .

The element body 3 includes a pair of ridge portions 3 g , a pair of ridge portions 3 h , four ridge portions 3 i , a pair of ridge portions 3 j , and a pair of ridge portions 3 k . The ridge portion 3 g is located between the end surface 3 e and the principal surface 3 a . The ridge portion 3 h is located between the end surface 3 e and the principal surface 3 b . The ridge portion 3 i is located between the end surface 3 e and the side surface 3 c . The ridge portion 3 j is located between the principal surface 3 a and the side surface 3 c . The ridge portion 3 k is located between the principal surface 3 b and the side surface 3 c . In the present embodiment, each of the ridge portions 3 g , 3 h , 3 i , 3 j , and 3 k is rounded to curve. The element body 3 is subject to what is called a round chamfering process.

The end surface 3 e and the principal surface 3 a are indirectly adjacent to each other with the ridge portion 3 g therebetween. The end surface 3 e and the principal surface 3 b are indirectly adjacent to each other with the ridge portion 3 h therebetween. The end surface 3 e and the side surface 3 c are indirectly adjacent to each other with the ridge portion 3 i therebetween. The principal surface 3 a and the side surface 3 c are indirectly adjacent to each other with the ridge portion 3 j therebetween. The principal surface 3 b and the side surface 3 c are indirectly adjacent to each other with the ridge portion 3 k therebetween.

The element body 3 is configured by laminating a plurality of dielectric layers in the second direction D 2 . The element body 3 includes the plurality of laminated dielectric layers. In the element body 3 , a lamination direction of the plurality of dielectric layers coincides with the second direction D 2 . Each dielectric layer includes, for example, a sintered body of a ceramic green sheet containing a dielectric material. The dielectric material includes, for example, a dielectric ceramic of BaTiO 3 base, Ba(Ti,Zr)O 3 base, or (Ba,Ca)TiO 3 base. In an actual element body 3 , each of the dielectric layers is integrated to such an extent that a boundary between the dielectric layers cannot be visually recognized. In the element body 3 , the lamination direction of the plurality of dielectric layers may coincide with the first direction D 1 .

As illustrated in FIGS. 2, 5, and 6 , the multilayer capacitor C 1 includes a plurality of internal electrodes 7 and a plurality of internal electrodes 9 . Each of the internal electrodes 7 and 9 is an internal conductor disposed in the element body 3 . Each of the internal electrodes 7 and 9 is made of a conductive material that is commonly used as an internal conductor of a multilayer electronic component. The conductive material includes, for example, a base metal. The conductive material includes, for example, Ni or Cu. Each of the internal electrodes 7 and 9 is configured as a sintered body of conductive paste containing the conductive material described above. In the first embodiment, the internal electrodes 7 and 9 are made of Ni.

The internal electrodes 7 and the internal electrodes 9 are disposed in different positions (layers) in the second direction D 2 . The internal electrodes 7 and the internal electrodes 9 are alternately disposed in the element body 3 to oppose each other in the second direction D 2 with an interval therebetween. Polarities of the internal electrodes 7 and the internal electrodes 9 are different from each other. In a case where the lamination direction of the plurality of dielectric layers is the first direction D 1 , the internal electrodes 7 and the internal electrodes 9 are disposed in different positions (layers) in the first direction D 1 . One end of each of the internal electrodes 7 and 9 is exposed to a corresponding end surface 3 e . Each of the internal electrodes 7 and 9 includes one end exposed to the corresponding end surface 3 e . A plurality of internal electrodes 7 and a plurality of internal electrodes 9 are alternately disposed in the second direction D 2 . The internal electrodes 7 and 9 are located in a plane substantially orthogonal to the principle surfaces 3 a and 3 b . The internal electrodes 7 and the internal electrodes 9 oppose each other in the second direction D 2 . The direction (second direction D 2 ) in which the internal electrodes 7 and the internal electrodes 9 oppose each other is orthogonal to the direction (first direction D 1 ) orthogonal to the principle surfaces 3 a and 3 b.

As illustrated in FIG. 2 , the external electrodes 5 are disposed at both end portions of the element body 3 in the third direction D 3 . Each of the external electrodes 5 is disposed on the corresponding end surface 3 e side of the element body 3 . As illustrated in FIGS. 3, 5, and 6 , the external electrode 5 includes a plurality of electrode portions 5 a , 5 b , 5 c , and 5 e . The electrode portion 5 a is disposed on the principal surface 3 a and on the ridge portion 3 g . The electrode portion 5 b is disposed on the ridge portion 3 h . The electrode portion 5 c is disposed on each side surface 3 c and on each ridge portion 3 i . The electrode portion 5 e is disposed on the corresponding end surface 3 e . The external electrode 5 also includes electrode portions disposed on the ridge portions 3 j and 3 k.

The external electrode 5 is formed on the four surfaces, that is, the principal surface 3 a , the end surface 3 e , and the pair of side surfaces 3 c , as well as on the ridge portions 3 g , 3 h , 3 i , and 3 j . The electrode portions 5 a , 5 b , 5 c , and 5 e adjacent each other are coupled and are electrically connected to each other. In the present embodiment, the external electrode 5 is not intentionally formed on a principal surface 3 b . Each electrode portion 5 e disposed on each end surface 3 e covers all one ends of the corresponding internal electrodes 7 or 9 . Each of the internal electrodes 7 and 9 is directly connected to the corresponding electrode portion 5 e . Each of the internal electrodes 7 and 9 is electrically connected to the corresponding external electrode 5 .

As illustrated in FIGS. 3, 5, and 6 , the external electrode 5 includes a first electrode layer E 1 , a second electrode layer E 2 , a third electrode layer E 3 , and a fourth electrode layer E 4 . The fourth electrode layer E 4 is the outermost layer of the external electrode 5 . Each of the electrode portions 5 a , 5 c , and 5 e includes the first electrode layer E 1 , the second electrode layer E 2 , the third electrode layer E 3 , and the fourth electrode layer E 4 . The electrode portion 5 b includes the first electrode layer E 1 , the third electrode layer E 3 , and the fourth electrode layer E 4 .

The first electrode layer E 1 included in the electrode portion 5 a is disposed on the ridge portion 3 g , and is not disposed on the principal surface 3 a . In the present embodiment, the first electrode layer E 1 included in the electrode portion 5 a is in contact with the entire ridge portion 3 g . The principal surface 3 a is not covered with the first electrode layer E 1 , thereby being exposed from the first electrode layer E 1 . The second electrode layer E 2 included in the electrode portion 5 a is disposed on the first electrode layer E 1 and on the principal surface 3 a . The first electrode layer E 1 is entirely covered with the second electrode layer E 2 . In the electrode portion 5 a , the second electrode layer E 2 is in contact with a part of the principal surface 3 a and the entire first electrode layer E 1 . The electrode portion 5 a is four-layered on the ridge portion 3 g , and is three-layered on the principal surface 3 a.

As described above, in a case in which an element is described as covering another element, the element may directly cover the other element or indirectly cover the other element. In a case in which an element is described as indirectly covering another element, an intervening element is present between the element and the other element. In a case in which an element is described as directly covering another element, no intervening element is present between the element and the other element.

The second electrode layer E 2 included in the electrode portion 5 a is formed to cover the entire ridge portion 3 g and a part of the principle surface 3 a . The second electrode layer E 2 included in the electrode portion 5 a indirectly covers the entire ridge portion 3 g in such a manner that the first electrode layer E 1 is located between the second electrode layer E 2 and the ridge portion 3 g . The second electrode layer E 2 included in the electrode portion 5 a directly covers the part of the principle surface 3 a . The second electrode layer E 2 included in the electrode portion 5 a directly covers an entire portion of the first electrode layer E 1 formed on the ridge portion 3 g.

The first electrode layer E 1 included in the electrode portion 5 b is disposed on the ridge portion 3 h , and is not disposed on the principal surface 3 b . In the present embodiment, the first electrode layer E 1 included in the electrode portion 5 b is in contact with the entire ridge portion 3 h . The principal surface 3 b is not covered with the first electrode layer E 1 , thereby being exposed from the first electrode layer E 1 . The electrode portion 5 b does not include the second electrode layer E 2 . The principal surface 3 b is not covered with the second electrode layer E 2 , thereby being exposed from the second electrode layer E 2 . The electrode portion 5 b is three-layered.

The first electrode layer E 1 included in the electrode portion 5 c is disposed on the ridge portion 3 i , and is not disposed on the side surface 3 c . In the present embodiment, the first electrode layer E 1 included in the electrode portion 5 c is in contact with the entire ridge portion 3 i . The side surface 3 c is not covered with the first electrode layer E 1 , thereby being exposed from the first electrode layer E 1 . The second electrode layer E 2 included in the electrode portion 5 c is disposed on the first electrode layer E 1 and on the side surface 3 c . A part of the first electrode layer E 1 is covered with the second electrode layer E 2 . In the electrode portion 5 c , the second electrode layer E 2 is in contact with a part of the side surface 3 c and a part of the first electrode layer E 1 .

The second electrode layer E 2 included in the electrode portion 5 c is formed to cover a part of the ridge portion 3 i and a part of the side surface 3 c . The second electrode layer E 2 included in the electrode portion 5 c indirectly covers the part of the ridge portion 3 i in such a manner that the first electrode layer E 1 is located between the second electrode layer E 2 and the ridge portion 3 i . The second electrode layer E 2 included in the electrode portion 5 c indirectly covers a region near the principle surface 3 a of the ridge portion 3 i . The second electrode layer E 2 included in the electrode portion 5 c directly covers the part of the side surface 3 c . The second electrode layer E 2 included in the electrode portion 5 c directly covers a part of the portion of the first electrode layer E 1 formed in the ridge portion 3 i.

The electrode portion 5 c includes a region 5 c 1 and a region 5 c 2 . The region 5 c 2 is located closer to the principal surface 3 a than the region 5 c 1 . In the present embodiment, the electrode portion 5 c includes only two regions 5 c 1 , 5 c 2 . The region 5 c 1 includes the first electrode layer E 1 , the third electrode layer E 3 , and the fourth electrode layer E 4 . The region 5 c 1 does not include the second electrode layer E 2 . The region 5 c 1 is three-layered. The region 5 c 2 includes the first electrode layer E 1 , the second electrode layer E 2 , the third electrode layer E 3 , and the fourth electrode layer E 4 . The region 5 c 2 is four-layered on the ridge portion 3 i , and is three-layered on the side surface 3 c . The region 5 c 1 is the region where the first electrode layer E 1 is exposed from the second electrode layer E 2 . The region 5 c 2 is the region where the first electrode layer E 1 is covered with the second electrode layer E 2 .

The first electrode layer E 1 included in the electrode portion 5 e is disposed on the end surface 3 e . The end surface 3 e is entirely covered with the first electrode layer E 1 . The first electrode layer E 1 included in the electrode portion 5 e is in contact with the entire end surface 3 e . The second electrode layer E 2 included in the electrode portion 5 e is disposed on the first electrode layer E 1 . A part of the first electrode layer E 1 is covered with the second electrode layer E 2 . In the electrode portion 5 e , the second electrode layer E 2 is in contact with the part of the first electrode layer E 1 . The second electrode layer E 2 included in the electrode portion 5 e is formed to cover a part of the end surface 3 e . The second electrode layer E 2 included in the electrode portion 5 e indirectly covers the part of the end surface 3 e in such a manner that the first electrode layer E 1 is located between the second electrode layer E 2 and the end surface 3 e . The second electrode layer E 2 included in the electrode portion 5 e directly covers a part of the portion of the first electrode layer E 1 formed on the end surface 3 e.

The electrode portion 5 e includes a region 5 e 1 and a region 5 e 2 . The region 5 e 2 is located closer to the principal surface 3 a than the region 5 e 1 . In the present embodiment, the electrode portion 5 e includes only two regions 5 e 1 , 5 e 2 . The region 5 e 1 includes the first electrode layer E 1 , the third electrode layer E 3 , and the fourth electrode layer E 4 . The region 5 e 1 does not include the second electrode layer E 2 . The region 5 e 1 is three-layered. The region 5 e 2 includes the first electrode layer E 1 , the second electrode layer E 2 , the third electrode layer E 3 , and the fourth electrode layer E 4 . The region 5 e 2 is four-layered. The region 5 e 1 is the region where the first electrode layer E 1 is exposed from the second electrode layer E 2 . The region 5 e 2 is the region where the first electrode layer E 1 is covered with the second electrode layer E 2 .

The first electrode layer E 1 is formed by sintering conductive paste applied onto the surface of the element body 3 . The first electrode layer E 1 is formed to cover the end surface 3 e and the ridge portions 3 g , 3 h , and 3 i . The first electrode layer E 1 is formed by sintering a metal component (metal powder) contained in the conductive paste. The first electrode layer E 1 is a sintered metal layer. The first electrode layer E 1 is a sintered metal layer formed on the element body 3 . The first electrode layer E 1 is not intentionally formed on the pair of principal surfaces 3 a and 3 b and the pair of side surfaces 3 c . The first electrode layer E 1 may be formed on the principal surfaces 3 a and 3 b and the side surfaces 3 c due to a manufacturing error, for example.

In the present embodiment, the first electrode layer E 1 is a sintered metal layer made of Cu. The first electrode layer E 1 may be a sintered metal layer made of Ni. The first electrode layer E 1 contains a base metal. The conductive paste contains, for example, powder made of Cu or Ni, a glass component, an organic binder, and an organic solvent.

The second electrode layer E 2 is formed by curing conductive resin applied onto the first electrode layer E 1 , the principal surface 3 a , and the pair of side surfaces 3 c . The second electrode layer E 2 is fainted over the first electrode layer E 1 and the element body 3 . The second electrode layer E 2 covers a partial region of the first electrode layer E 1 . The second electrode layer E 2 covers the regions, of the first electrode layer E 1 , corresponding to the electrode portion 5 a , the region 5 c 2 of the electrode portion 5 c , and the region 5 e 2 of the electrode portion 5 e . The second electrode layer E 2 directly covers a part of the ridge portion 3 j . The second electrode layer is in contact with the part of the ridge portion 3 j . The first electrode layer E 1 serves as an underlying metal layer for forming the second electrode layer E 2 . The second electrode layer E 2 is a conductive resin layer formed on the first electrode layer E 1 .

The conductive resin contains, for example, a resin, a conductive material, and an organic solvent. The resin is, for example, a thermosetting resin. The conductive material is, for example, metal powder. The metal powder is, for example, Ag powder or Cu powder. The thermosetting resin is, for example, a phenolic resin, an acrylic resin, a silicone resin, an epoxy resin, or a polyimide resin. Electric resistance of the second electrode layer E 2 is larger than electric resistance of the first electrode layer E 1 .

The third electrode layer E 3 is formed on the second electrode layer E 2 and on the first electrode layer E 1 by plating method. The third electrode layer E 3 is formed on a portion of the first electrode layer E 1 exposed from the second electrode layer E 2 . The third electrode layer E 3 directly covers the second electrode layer E 2 and the portion of the first electrode layer E 1 exposed from the second electrode layer E 2 . In the present embodiment, the third electrode layer E 3 is formed on the first electrode layer E 1 and the second electrode layer E 2 by Ni plating. The third electrode layer E 3 is a Ni plating layer. The third electrode layer E 3 may be an Sn plating layer, a Cu plating layer, or an Au plating layer. The third electrode layer E 3 contains Ni, Sn, Cu, or Au.

The fourth electrode layer E 4 is formed on the third electrode layer E 3 by plating method. The fourth electrode layer E 4 indirectly covers the second electrode layer E 2 and the portion of the first electrode layer E 1 exposed from the second electrode layer E 2 in such a manner that the third electrode layer E 3 is located between the fourth electrode layer E 4 and the second electrode layer E 2 and portion of the first electrode layer E 1 exposed from the second electrode layer E 2 . In the present embodiment, the fourth electrode layer E 4 is formed on the third electrode layer E 3 by Sn plating. The fourth electrode layer E 4 is an Sn plating layer. The fourth electrode layer E 4 may be a Cu plating layer or an Au plating layer. The fourth electrode layer E 4 contains Sn, Cu, or Au. The third electrode layer E 3 and fourth electrode layer E 4 form a plating layer disposed on the second electrode layer E 2 . In the present embodiment, the plating layer disposed on the second electrode layer E 2 is a two-layered plating layer.

The first electrode layer E 1 included in the electrode portion 5 a , the first electrode layer E 1 included in the electrode portion 5 b , the first electrode layer E 1 included in the electrode portion 5 c , and the first electrode layer E 1 included in the electrode portion 5 e are integrally formed. The second electrode layer E 2 included in the electrode portion 5 a , the second electrode layer E 2 included in the electrode portion 5 c , and the second electrode layer E 2 included in the electrode portion 5 e are integrally formed. The third electrode layer E 3 included in the electrode portion 5 a , the third electrode layer E 3 included in the electrode portion 5 b , the third electrode layer E 3 included in the electrode portion 5 c , and the third electrode layer E 3 included in the electrode portion 5 e are integrally formed. The fourth electrode layer E 4 included in the electrode portion 5 a , the fourth electrode layer E 4 included in the electrode portion 5 b , the fourth electrode layer E 4 included in the electrode portion 5 c , and the fourth electrode layer E 4 included in the electrode portion 5 e are integrally formed.

Each of the first electrode layers E 1 (first electrode layers E 1 included in the electrode portions 5 e ) is formed on the end surface 3 e to be connected to the respective internal electrodes 7 and 9 . The first electrode layer E 1 covers the entire end surface 3 e , the entire ridge portion 3 g , the entire ridge portion 3 h , and the entire ridge portion 3 i . The second electrode layer E 2 (second electrode layer E 2 included in the electrode portions 5 a , 5 c , and 5 e ) continuously covers a part of the principle surface 3 a , a part of the end surface 3 e , and a part of each of the pair of side surfaces 3 c . The second electrode layer E 2 integrally covers a region near the end surface 3 e of the principle surface 3 a , a region near the principle surface 3 a of the end surface 3 e , and a region near the principle surface 3 a of the side surface 3 c.

The second electrode layer E 2 (second electrode layer E 2 included in the electrode portions 5 a , 5 c , and 5 e ) covers the entire ridge portion 3 g , a part of the ridge portion 3 i , and a part of the ridge portion 3 j . The second electrode layer E 2 covers the entire ridge portion 3 g , the part of the ridge portion 3 i , and the part of the ridge portion 3 j in such a manner that the first electrode layer E 1 is located between the second electrode layer E 2 and the ridge portions 3 g , 31 , and 3 j . The second electrode layer E 2 directly covers the entire portion formed on the ridge portion 3 g , a part of the portion formed on the ridge portion 3 i , and a part of the portion formed on the ridge portion 3 j , of the first electrode layer E 1 . The second electrode layer E 2 includes a plurality of portions each corresponding to the part of the principle surface 3 a , the part of the end surface 3 e , the part of each of the pair of side surfaces 3 c , the entire ridge portion 3 g , the part of the ridge portion 3 i , and the part of the ridge portion 3 j.

The first electrode layer E 1 (first electrode layer E 1 included in the electrode portions 5 a , 5 b , 5 c , and 5 e ) includes a region covered with the second electrode layer E 2 (second electrode layer E 2 included in the electrode portions 5 a , 5 c , and 5 e ), and a region not covered with the second electrode layer E 2 (second electrode layer E 2 included in the electrode portions 5 a , 5 c , and 5 e ). The region not covered with the second electrode layer E 2 is a region exposed from the second electrode layer E 2 . The third electrode layer E 3 and the fourth electrode layer E 4 cover a region of the first electrode layer E 1 not covered with the second electrode layer E 2 and the second electrode layer E 2 . The first electrode layer E 1 (first electrode layer E 1 included in the electrode portion 5 e ) is directly connected to the respective internal electrodes 7 and 9 .

As illustrated in FIG. 4 , a thickness of the second electrode layer E 2 gradually increases from the principle surface 3 b toward the principle surface 3 a in the first direction D 1 . The thickness of the second electrode layer E 2 is, for example, the shortest distance between the first electrode layer E 1 and the third electrode layer E 3 . The thickness of the second electrode layer E 2 is, for example, the thickness of the second electrode layer E 2 in the normal direction of the surface in contact with the second electrode layer E 2 of the first electrode layer E 1 .

The second electrode layer E 2 includes a thickest portion E 2 m . The thickest portion Elm is the portion where the second electrode layer E 2 has a maximum thickness. The thickest portion E 2 m is located near the principle surface 3 a in the first direction D 1 . The thickest portion E 2 m is located nearer to the principle surface 3 a than the principle surface 3 b in the first direction D 1 . The thickest portion E 2 m is located nearer to the principle surface 3 a than the principle surface 3 b in the first direction D 1 , in the second electrode layer E 2 . For example, a distance between a virtual plane including the principle surface 3 a and the thickest portion E 2 m in the first direction D 1 is smaller than a distance between a virtual plane including the principle surface 3 b and the thickest portion E 2 m in the first direction D 1 . For example, the distance between the virtual plane including the principle surface 3 a and the thickest portion E 2 m in the first direction D 1 is smaller than a distance between a virtual plane including the end edge E 2 e near the principle surface 3 b of the second electrode layer E 2 (see FIG. 9 ) and in parallel with the principle surface 3 b and the thickest portion E 2 m in the first direction D 1 .

The second electrode layer E 2 includes a ridge portion E 2 r covering the ridge portion 3 g of the element body 3 . The ridge portion E 2 r indirectly covers the ridge portion 3 g . The ridge portion E 2 r is located nearer to the principle surface 3 a than the thickest portion E 2 m in the first direction D 1 . In the second electrode layer E 2 , the ridge portion E 2 r is located nearer to the principle surface 3 a than the thickest portion E 2 m in the first direction D 1 . For example, a distance between the virtual plane including the principle surface 3 a and the ridge portion E 2 r in the first direction D 1 is smaller than the distance between the virtual plane including the principle surface 3 a and the thickest portion E 2 m in the first direction D 1 .

A thickness Mb of the ridge portion E 2 r is smaller than a thickness Ma of the thickest portion E 2 m . The thickness Mb gradually decreases in a direction from the principle surface 3 b along the first direction D 1 to the principle surface 3 a . The thickness Mb is smaller than the thickness Ma at any position in the first direction D 1 in the ridge portion E 2 r . As described above, the thickness of the second electrode layer E 2 is a maximum at the thickest portion E 2 m . For example, the thickness of the second electrode layer E 2 gradually increases from the end edge E 2 e located near the principle surface 3 b toward the thickest portion E 2 m in the first direction D 1 . For example, the thickness of the second electrode layer E 2 gradually decreases toward the principle surface 3 a at the ridge portion E 2 r beyond the thickest portion E 2 m.

The ridge portion E 2 r has a rounded shape to achieve a predetermined curvature radius. Since the thickness Mb is smaller than the thickness Ma, a degree of roundness of the ridge portion E 2 r is small, or a curvature radius R 2 of the ridge portion E 2 r is large, as compared with a configuration in which the thickness Mb is greater than or equal to the thickness Ma. The curvature radius R 2 is larger than a curvature radius R 1 of the ridge portion 3 g . The degree of roundness of the ridge portion E 2 r is smaller than a degree of rounding of the ridge portion 3 g . The third electrode layer E 3 and fourth electrode layer E 4 are formed by plating method along the surface of the second electrode layer E 2 . Therefore, a curvature radius of the portion covering the ridge portion E 2 r of the second electrode layer E 2 of the third electrode layer E 3 and fourth electrode layer E 4 is substantially equal to the curvature radius R 2 . A curvature radius of a ridge portion B 1 near the principle surface 3 a in the external electrode 5 is substantially equal to the curvature radius R 2 . Like the curvature radius R 2 , the curvature radius of the ridge portion B 1 is larger than the curvature radius R 1 .

As illustrated in FIG. 7 , when viewed from the first direction D 1 , the entire portion of the first electrode layer E 1 (first electrode layer E 1 included in the electrode portion 5 a ) is covered with the second electrode layer E 2 . When viewed from the first direction D 1 , the first electrode layer E 1 (first electrode layer E 1 included in the electrode portion 5 a ) is not exposed from the second electrode layer E 2 .

As illustrated in FIG. 8 , when viewed in the second direction D 2 , the end region near the principle surface 3 a of the first electrode layer E 1 is covered with the second electrode layer E 2 . The end region near the principle surface 3 a of the first electrode layer E 1 includes the first electrode layer E 1 included in the region 5 c 2 . When viewed from the second direction D 2 , the end edge E 2 e of the second electrode layer E 2 crosses the end edge E 1 e of the first electrode layer E 1 . When viewed from the second direction D 2 , the end region near the principle surface 3 b of the first electrode layer E 1 is exposed from the second electrode layer E 2 . The end region near the principle surface 3 b of the first electrode layer E 1 includes the first electrode layer E 1 included in the region 5 c 1 . An area of the second electrode layer E 2 located on the side surface 3 c and the ridge portion 3 i is larger than an area of the first electrode layer E 1 located on the ridge portion 3 i.

As illustrated in FIG. 9 , when viewed from the third direction D 3 , the end region near the principle surface 3 a of the first electrode layer E 1 is covered with the second electrode layer E 2 . The end region near the principle surface 3 a of the first electrode layer E 1 includes the first electrode layer E 1 included in the region 5 e 2 . When viewed from the third direction D 3 , the end edge E 2 e of the second electrode layer E 2 is located on the first electrode layer E 1 . When viewed from the third direction D 3 , the end region near the principle surface 3 b of the first electrode layer E 1 is exposed from the second electrode layer E 2 . The end region near the principle surface 3 b of the first electrode layer E 1 includes the first electrode layer E 1 included in the region 5 e 1 . An area of the second electrode layer E 2 located on the end surface 3 e and the ridge portion 3 g is smaller than an area of the first electrode layer E 1 located on the end surface 3 e and the ridge portion 3 g.

In the present embodiment, the second electrode layer E 2 continuously covers only the part of the principle surface 3 a , only the part of the end surface 3 e , and only the part of each of the pair of side surfaces 3 c . The second electrode layer E 2 covers the entire ridge portion 3 g , only the part of the ridge portion 3 i , and only the part of the ridge portion 3 j . The part of a portion, of the first electrode layer E 1 , covering the ridge portion 3 i is exposed from the second electrode layer E 2 . For example, the first electrode layer E 1 included in the region 5 c 1 is exposed from the second electrode layer E 2 .

As illustrated in FIG. 2 , a width of the region 5 c 2 in a third direction D 3 decreases with an increase in distance from the principal surface 3 a . The width of the region 5 c 2 in a third direction D 3 decreases with an increase in distance from the electrode portion 5 a . A width of the region 5 c 2 in a first direction D 1 decreases with an increase in distance from the end surface 3 e . The width of the region 5 c 2 in a first direction D 1 decreases with an increase in distance from the electrode portion 5 e . In the present embodiment, an end edge of the region 5 c 2 has a substantially arc shape when viewed from a second direction D 2 . The region 5 c 2 has a substantially fan shape when viewed from a second direction D 2 . In the present embodiment, as illustrated in FIG. 8 , the width of the second electrode layer E 2 viewed from the second direction D 2 decreases with an increase in distance from the principal surface 3 a . An end edge E 2 e of the second electrode layer E 2 has a substantially arc shape.

Next, a mounted structure of the multilayer capacitor C 1 will be described with reference to FIG. 10 . FIG. 10 is a view illustrating a mounted structure of a multilayer capacitor according to the first embodiment.

As illustrated in FIG. 10 , an electronic component device ECD 1 includes the multilayer capacitor C 1 and an electronic device ED. The electronic device ED includes, for example, a circuit board or an electronic component.

The multilayer capacitor C 1 is solder-mounted on the electronic device ED. The electronic device ED includes a principal surface EDa and a plurality of pad electrodes PE 1 and PE 2 . In the present embodiment, the electronic device ED includes two pad electrodes PE 1 and PE 2 . Each of the pad electrodes PE 1 and PE 2 is disposed on the principal surface EDa. The two pad electrodes PE 1 and PE 2 are spaced apart from each other. The multilayer capacitor C 1 is disposed on the electronic device ED in such a manner that the principal surface 3 a and the principal surface EDa oppose each other. As described above, the principal surface 3 a is arranged to constitute a mounting surface.

When the multilayer capacitor C 1 is solder-mounted, molten solder wets to the external electrodes 5 (fourth electrode layer E 4 ). Solder fillets SF are formed on the external electrodes 5 by solidification of the wet solder. The external electrodes 5 and the pad electrodes PE 1 and PE 2 corresponding to each other are coupled via the solder fillets SF.

The solder fillet SF is formed on the regions 5 e 1 and 5 e 2 of the electrode portion 5 e . That is, in addition to the region 5 e 2 , the region 5 e 1 that does not include the second electrode layer E 2 is also coupled to pad electrodes PE 1 and PE 2 via the solder fillet SF. Although illustration is omitted, the solder fillet SF is also formed on the regions 5 c 1 and 5 c 2 of the electrode portion 5 c . The solder fillet SF overlaps the region of the first electrode layer E 1 exposed from the second electrode layer E 2 when viewed from the third direction D 3 .

In the electronic component device ECD 1 , as described above, the electrode layer E 2 tends not to peel off from the element body and the moisture resistance reliability is improved.

When viewed from the third direction D 3 , the solder fillet SF overlaps the region of the first electrode layer E 1 exposed from the second electrode layer E 2 . The region of the first electrode layer E 1 exposed from the second electrode layer E 2 is electrically connected to the electronic device ED via the solder fillet SF. The region of the first electrode layer E 1 exposed from the second electrode layer E 2 is electrically connected to the electronic device ED without passing through the second electrode layer E 2 . Therefore, the electronic component device ECD 1 suppresses the increase of the ESR even in a case where the external electrode 5 includes the second electrode layer E 2 .

Like the curvature radius R 2 , as described above, the curvature radius of the ridge portion B 1 of the external electrode 5 is larger than the curvature radius R 1 of the ridge portion 3 g (see FIGS. 3 and 4 ). The ridge portion B 1 has a shape rounded such that the curvature radius of the ridge portion B 1 is larger than the curvature radius R 1 . Therefore, as illustrated in FIG. 10 , a region Si where the solder tends to accumulate is formed around the ridge portion B 1 in proportion to the rounded ridge portion B 1 . The region Si is arranged to constitute a solder pool.

In a case where the multilayered capacitor C 1 is solder-mounted on the electronic device ED, an external force applied onto the multilayered capacitor C 1 from the electronic device ED may act as a stress on the element body 3 . The external force acts on the element body 3 from the solder fillet SF through the external electrode 5 . In this case, a crack may occur in the element body 3 .

In the multilayered capacitor C 1 , the second electrode layer E 2 is formed on the end surface 3 e . Therefore, even in a case where the external force acts on the multilayered capacitor C 1 from the electronic device ED, the second electrode layer E 2 absorbs the external force. Consequently, the multilayered capacitor C 1 suppresses the occurrence of the crack in the element body 3 .

In a case where thermal shock stress acts on the solder fillet SF, the crack may occur in the solder fillet SF. The thermal shock stress tends to be concentrated in the region near the principle surface 3 a in the solder fillet SF.

In the multilayered capacitor C 1 , the second electrode layer E 2 absorbs thermal shock stress. The thickness of the second electrode layer E 2 gradually increases from the principle surface 3 b toward the principle surface 3 a in the first direction D 1 , and the thickest portion E 2 m is located near the principle surface 3 a in the first direction D 1 . The thickest portion E 2 m is highly effective in absorbing the thermal shock stress than other portions of the second electrode layer E 2 . Therefore, the thermal shock stress tends not to be concentrated in the region near the principle surface 3 a in the solder fillet SF. Consequently, the multilayered capacitor C 1 suppresses occurrence of a crack in the solder fillet SF.

In the multilayered capacitor C 1 , the thickest portion E 2 m is located nearer to the principle surface 3 a than the principle surface 3 b in the first direction D 1 . Therefore, the second electrode layer E 2 effectively absorbs the thermal shock stress concentrated in the region near the principle surface 3 a of the solder fillet SF. Consequently, the multilayered capacitor C 1 reliably suppresses the occurrence of the crack in the solder fillet SF.

In the multilayered capacitor C 1 , the thickest portion E 2 m is located nearer to the principle surface 3 a than the principle surface 3 b in the first direction D 1 , in the second electrode layer E 2 . Therefore, the second electrode layer E 2 effectively absorbs the thermal shock stress concentrated in the region near the principle surface 3 a of the solder fillet SF. Consequently, the multilayered capacitor C 1 reliably suppresses the occurrence of the crack in the solder fillet SF.

In the multilayered capacitor C 1 , the second electrode layer E 2 includes the ridge portion E 2 r covering the ridge portion 3 g . The ridge portion E 2 r is located nearer to the principle surface 3 a than the thickest portion E 2 m in the first direction D 1 . The thickness Mb of the ridge portion E 2 r is smaller than the thickness Ma of the thickest portion E 2 m.

In the multilayered capacitor C 1 , the curvature radius R 2 of the ridge portion E 2 r is large, as compared with a configuration in which the thickness Mb is equal to or greater than the thickness Mb. Therefore, the curvature radius of the ridge portion B 1 of the external electrode 5 is also large. Consequently, the multilayered capacitor C 1 improves flexibility of the multilayered capacitor C 1 and further reliably suppresses the occurrence of the crack in the element body 3 .

Since the thickness Mb is smaller than the thickness Ma, the solder tends to accumulate at a position corresponding to the ridge portion B 1 of the external electrode 5 . Therefore, the multilayered capacitor C 1 can provide the solder pool.

The second electrode layer E 2 covers the region near the principle surface 3 a of the end surface 3 e . A region between the element body 3 and the second electrode layer E 2 may act as a path through which moisture infiltrates. In a case where moisture infiltrates from the region between the element body 3 and the second electrode layer E 2 , durability of the multilayered capacitor C 1 decreases. The multilayered capacitor C 1 includes few paths through which moisture infiltrates, as compared with a configuration in which the second electrode layer E 2 covers the entire end surface 3 e . Therefore, the multilayered capacitor C 1 improves the moisture resistance reliability.

In a case where the multilayer capacitor C 1 is solder-mounting on the electronic device, the external force applied onto the multilayer capacitor C 1 from the electronic device may act as the stress on the element body. The external force acts on the element body 3 from the solder fillet formed at the solder-mounting, through the external electrode 5 . The external force tends to act on the region near the end surface 3 e of the principle surface 3 a of the element body 3 . In the configuration in which the second electrode layer E 2 covers the region near the end surface 3 e of the principle surface 3 a , the external force applied onto the multilayer capacitor C 1 from the electronic device tends not to act on the element body 3 . Therefore, the multilayer capacitor C 1 suppresses the occurrence of the crack in the element body 3 .

The external electrode 5 includes the first electrode layer E 1 formed on the end surface 3 e to be connected to the respective internal electrodes 7 and 9 . The first electrode layer E 1 includes the region covered with the second electrode layer E 2 and the region exposed from the second electrode layer E 2 . The first electrode layer E 1 is favorably in contact with the respective internal electrodes 7 and 9 . This allows reliable electrical connection between the external electrode 5 and the internal electrodes 7 and 9 .

The electric resistance of the second electrode layer E 2 is larger than electric resistance of the first electrode layer E 1 . In the multilayer capacitor C 1 , the region of the first electrode layer E 1 exposed from the second electrode layer E 2 is electrically connected to the electronic device without passing through the second electrode layer E 2 . Therefore, the multilayer capacitor C 1 suppresses the increase of ESR even in a case where the external electrode 5 includes the second electrode layer E 2 .

In the multilayer capacitor C 1 , the external electrode 5 includes the third electrode layer E 3 and fourth electrode layer E 4 . Therefore, the multilayer capacitor C 1 can be solder-mounting on the electronic device.

The region of the first electrode layer E 1 exposed from the second electrode layer E 2 is electrically connected to the electronic device via the third electrode layer E 3 and fourth electrode layer E 4 . Therefore, the multilayer capacitor C 1 further suppresses the increase in the ESR.

Second Embodiment

With reference to FIGS. 11 to 18 , a configuration of a multilayer feedthrough capacitor C 3 according to a second embodiment will be described. FIGS. 11 and 12 are plan views of the multilayer feedthrough capacitor according to the second embodiment. FIG. 13 is a side view of the multilayer feedthrough capacitor according to the second embodiment. FIG. 14 is an end view of the multilayer feedthrough capacitor according to the second embodiment. FIGS. 15 , 16 , and 17 are views illustrating a cross-sectional configuration of the multilayer feedthrough capacitor according to the second embodiment. FIG. 18 is a side view illustrating an element body, a first electrode layer, and a second electrode layer. In the second embodiment, an electronic component is, for example, the multilayer feedthrough capacitor C 3 . Hereinafter, differences between the multilayer capacitor C 1 and the multilayer feedthrough capacitor C 3 will be mainly described.

As illustrated in FIGS. 11 to 14 , the multilayer feedthrough capacitor C 3 includes an element body 3 , a pair of external electrodes 5 , and one external electrode 6 . The pair of external electrodes 5 and the one external electrode 6 are disposed on an outer surface of the element body 3 . In the present embodiment, the element body 3 is configured by laminating a plurality of dielectric layers in the first direction D 1 . The pair of external electrodes 5 and the one external electrode 6 are separated from each other. The pair of external electrodes 5 is arranged to constitute signal terminal electrodes, and the external electrode 6 is arranged to constitute a ground terminal electrode.

As illustrated in FIGS. 15, 16, and 17 , the multilayer feedthrough capacitor C 3 includes a plurality of internal electrodes 17 and a plurality of internal electrodes 19 . Each of the internal electrodes 17 and 19 is an internal conductor disposed in the element body 3 . As with the internal electrodes 7 and 9 , each of the internal electrodes 17 and 19 is made of a conductive material that is commonly used as an internal electrode of a multilayer electronic component. Also in the second embodiment, each of the internal electrodes 17 and 19 is made of Ni.

The internal electrode 17 and the internal electrode 19 are disposed in different positions (layers) in the first direction D 1 . The internal electrode 17 and the internal electrode 19 are alternately disposed in the element body 3 to oppose each other in the first direction D 1 with an interval therebetween. Polarities of the internal electrode 17 and the internal electrode 19 are different from each other. In a case where a lamination direction of the plurality of dielectric layers is a second direction D 2 , the internal electrode 17 and the internal electrode 19 are disposed in different positions (layers) in the second direction D 2 . An end of the internal electrode 17 is exposed to a pair of end surfaces 3 e . An end of the internal electrode 19 is exposed to a pair of side surfaces 3 c.

As with the external electrodes 5 of the multilayer capacitor C 1 , the external electrodes 5 are disposed at both end portions of the element body 3 in a third direction D 3 . Each of the external electrodes 5 is disposed on the corresponding end surface 3 e side of the element body 3 . The external electrode 5 includes a plurality of electrode portions 5 a , 5 b , 5 c , and 5 e . The electrode portion 5 a is disposed on the principal surface 3 a and on the ridge portion 3 g . The electrode portion 5 b is disposed on the ridge portion 3 h . The electrode portion 5 c is disposed on each side surface 3 c and on each ridge portion 3 i . The electrode portion 5 e is disposed on the corresponding end surface 3 e . The external electrode 5 also includes a electrode portion disposed on the ridge portions 3 j.

The electrode portion 5 e covers all the ends exposed to the end surface 3 e , of the internal electrode 17 . The internal electrodes 17 are directly connected to each electrode portion 5 e . The internal electrodes 17 are electrically connected to the pair of external electrodes 5 .

The external electrode 6 is disposed on a central portion of the element body 3 in the third direction D 3 . The external electrode 6 is located between the pair of external electrode 5 in the third direction D 3 . The external electrode 6 includes an electrode portion 6 a and a pair of electrode portions 6 c . The electrode portion 6 a is disposed on the principal surface 3 a . Each of the electrode portions 6 c is disposed on the side surface 3 c and on the ridge portions 3 j and 3 k . The external electrode 6 is formed on the three surfaces, that is, the principal surface 3 a and the pair of side surfaces 3 c , as well as on the ridge portions 3 j and 3 k . The electrode portions 6 a and 6 c adjacent each other are coupled and are electrically connected to each other.

The electrode portion 6 c covers all the ends exposed to the side surface 3 c , of the internal electrode 19 . The internal electrodes 19 are directly connected to each electrode portion 6 c . The internal electrodes 19 are electrically connected to the one external electrode 6 .

As illustrated in FIGS. 14, 15, and 16 , the external electrode 6 includes a first electrode layer E 1 , a second electrode layer E 2 , a third electrode layer E 3 , and a fourth electrode layer E 4 . The fourth electrode layer E 4 is the outermost layer of the external electrode 6 . The electrode portion 6 a includes the second electrode layer E 2 , the third electrode layer E 3 , and the fourth electrode layer E 4 . Each of the electrode portions 6 c includes the first electrode layer E 1 , the second electrode layer E 2 , the third electrode layer E 3 , and the fourth electrode layer E 4 .

The first electrode layer E 2 included in the electrode portion 6 a is disposed on the principal surface 3 a . The electrode portion 6 a does not include the first electrode layer E 1 . The first electrode layer E 2 included in the electrode portion 6 a is in contact with the principal surface 3 a . The electrode portion 6 a is three-layered.

The first electrode layer E 1 included in the electrode portion 6 c is disposed on the side surface 3 c and on the ridge portions 3 j and 3 k . The first electrode layer E 2 included in the electrode portion 6 c is disposed on the first electrode layer E 1 , on the side surface 3 c , and on the ridge portion 3 j . A part of the first electrode layer E 1 is covered with the second electrode layer E 2 . The first electrode layer E 2 included in the electrode portion 6 c is in contact with the side surface 3 c and the ridge portion 3 j.

The electrode portion 6 c includes a region 6 c 1 and a region 6 c 2 . The region 6 c 2 is located closer to the principal surface 3 a than the region 6 c 1 . The region 6 c 1 includes the first electrode layer E 1 , the third electrode layer E 3 , and the fourth electrode layer E 4 . The region 6 c 1 does not include the second electrode layer E 2 . The region 6 c 1 is three-layered. The region 6 c 2 includes the first electrode layer E 1 , the second electrode layer E 2 , the third electrode layer E 3 , and the fourth electrode layer E 4 . The region 6 c 2 is four-layered. The region 6 c 1 is the region where the first electrode layer E 1 is exposed from the second electrode layer E 2 . The region 6 c 2 is the region where the first electrode layer E 1 is covered with the second electrode layer E 2 .

The first electrode layer E 1 is formed to cover the side surface 3 c and the ridge portion 3 j and 3 k . The first electrode layer E 1 is not intentionally formed on the pair of principal surfaces 3 a and 3 b . The first electrode layer E 1 may be formed on the principal surfaces 3 a and 3 b due to a manufacturing error, for example.

The second electrode layer E 2 is formed over the first electrode layer E 1 and the element body 3 . The second electrode layer E 2 covers a partial region of the first electrode layer E 1 . The second electrode layer E 2 covers a region corresponding to the region 6 c 2 of the electrode portion 6 c . The second electrode layer E 2 covers a partial region of the principal surface 3 a , a partial region of the side surface 3 c , and a partial region of the ridge portion 3 j.

The third electrode layer E 3 is formed on the second electrode layer E 2 and on the first electrode layer E 1 by plating method. The third electrode layer E 3 is formed on a portion of the first electrode layer E 1 exposed from the second electrode layer E 2 . The fourth electrode layer E 4 is formed on the third electrode layer E 3 by plating method.

The second electrode layer E 2 included in the electrode portion 6 a and the second electrode layer E 2 included in the electrode portion 6 c are integrally formed. The third electrode layer E 3 included in the electrode portion 6 a and the third electrode layer E 3 included in the electrode portion 6 c are integrally formed. The fourth electrode layer E 4 included in the electrode portion 6 a and the fourth electrode layer E 4 included in the electrode portion 6 are integrally formed.

With regard to the external electrode 6 , as illustrated in FIG. 18 , when viewed in the second direction D 2 , the end region near the principle surface 3 a of the first electrode layer E 1 is covered with the second electrode layer E 2 . The end region near the principle surface 3 a of the first electrode layer E 1 includes the first electrode layer E 1 included in the region 6 c 2 . When viewed from the second direction D 2 , the end edge E 2 e of the second electrode layer E 2 crosses the end edge E 1 e of the first electrode layer E 1 . When viewed from the second direction D 2 , the end region near the principle surface 3 b of the first electrode layer E 1 is exposed from the second electrode layer E 2 . The end region near the principle surface 3 b of the first electrode layer E 1 includes the first electrode layer E 1 included in the region 6 c 1 .

As illustrated in FIG. 13 , a width of the region 6 c 2 in a third direction D 3 decreases with an increase in distance from the principal surface 3 a . The width of the region 5 c 2 in a third direction D 3 decreases with an increase in distance from the electrode portion 6 a . In the present embodiment, an end edge of the region 6 c 2 has a substantially arc shape when viewed from a second direction D 2 . The region 6 c 2 has a substantially semicircular shape when viewed from a second direction D 2 . In the present embodiment, as illustrated in FIG. 18 , the width of the second electrode layer E 2 viewed from the second direction D 2 decreases with an increase in distance from the principal surface 3 a . An end edge E 2 e of the second electrode layer E 2 included in the region 6 c 2 has a substantially arc shape.

The multilayer feedthrough capacitor C 3 is also solder-mounted on the electronic device. In the multilayer feedthrough capacitor C 3 , the principal surface 3 a opposes the electronic device. The principal surface 3 a is arranged to constitute a mounting surface.

The configuration of the external electrode 5 is the same as the configuration of the external electrode 5 of the first embodiment. In the second embodiment, a thickness of the second electrode layer E 2 formed on the end surface 3 e also gradually increases from the principle surface 3 b toward the principle surface 3 a in the first direction D 1 . The second electrode layer E 2 includes a thickest portion E 2 m at a position near the principle surface 3 a in the first direction D 1 . Like the multilayered capacitor C 1 , therefore, the multilayered feed-through capacitor C 3 suppresses occurrence of a crack in the element body 3 and the solder fillet SF. In the second embodiment, illustration of a cross-sectional configuration of the external electrode 5 corresponding to the cross-sectional configuration illustrated in FIG. 4 is omitted.

In the multilayer feedthrough capacitor C 3 , when viewed in the second direction D 2 , the end region near the principle surface 3 a of the first electrode layer E 1 is covered with the second electrode layer E 2 with regard to the external electrode 6 . Therefore, the stress tends not to concentrate on the end edge of the first electrode layer E 1 included in the region 6 c 2 . Consequently, the multilayer feedthrough capacitor C 3 suppresses occurrence of a crack in the element body 3 .

In the region 6 c 1 of the electrode portion 6 c , the first electrode layer E 1 is exposed from the second electrode layer E 2 . The region 6 c 1 does not include the second electrode layer E 2 . In region 6 c 1 , the first electrode layer E 1 is electrically connected to the electronic device without passing through the second electrode layer E 2 . Therefore, the multilayer feedthrough capacitor C 3 suppresses an increase of ESR.

The region 6 c 2 of the electrode portion 6 c includes the second electrode layer E 2 . Therefore, the stress tends not to concentrate on the end edge of the external electrode 6 even in the case where the external electrode 6 includes the electrode portion 6 c . The end edge of the external electrode 6 tends not to serve as an origination of a crack. Consequently, the multilayer feedthrough capacitor C 3 reliably suppresses the occurrence of a crack in the element body 3 .

The end edge of the region 6 c 2 may be substantially linear. The end edge of the region 6 c 2 may include a side extending in the third direction D 3 and a side extending in the first direction D 1 . The end edge of the region 6 c 2 includes the end edge E 2 e of the second electrode layer E 2 .

Although the embodiments and modifications of the present invention have been described above, the present invention is not necessarily limited to the embodiments and modifications, and the embodiment can be variously changed without departing from the scope of the invention.

In the first and second embodiments, the second electrode layer E 2 covers a part of the end surface 3 e . The second electrode layer E 2 covers a region near the principle surface 3 a . The configuration of the second electrode layer E 2 may include another configuration other than those described above. The second electrode layer E 2 may cover at least the part of the end surface 3 e . The second electrode layer E 2 may cover the entire end surface 3 e . The second electrode layer E 2 may cover the ridge portion 3 h . The second electrode layer E 2 may cover a part of the principle surface 3 b to extend beyond the ridge portion 3 h entirely or partially from the end surface 3 e . The second electrode layer E 2 may cover the entire ridge portion 3 i . The second electrode layer E 2 may cover a part of the side surface 3 c to extend beyond the entire ridge portion 3 i from the end surface 3 e.

In the first and second embodiments, the thickest portion E 2 m is located nearer to the principle surface 3 a than the principle surface 3 b in the first direction D 1 . The thickest portion E 2 m is located nearer to the principle surface 3 a than the principle surface 3 b in the first direction D 1 , in the second electrode layer E 2 . The thickest portion E 2 m may be located at a position other than the above-mentioned position. The thickest portion E 2 m may not be located nearer to the principle surface 3 a than the principle surface 3 b in the first direction D 1 , in the second electrode layer E 2 .

The first electrode layer E 1 may be formed on the principle surface 3 a to extend beyond the ridge portion 3 g entirely or partially from the end surface 3 e . The first electrode layer E 1 may be formed on the principle surface 3 b to extend beyond the ridge portion 3 h entirely or partially from the end surface 3 e . The first electrode layer E 1 may be formed on the side surface 3 c to extend beyond the ridge portion 3 i entirely or partially from the end surface 3 e.

The electronic component of the first embodiment is a multilayer capacitor C 1 . The electronic component of the second embodiment is a multilayer feedthrough capacitor C 3 . Applicable electronic components are not limited to multilayer capacitors and multilayer feedthrough capacitors. Examples of the applicable electronic components include, but not limited to, multilayer electronic components such as a multilayer inductor, a multilayer varistor, a multilayer piezoelectric actuator, a multilayer thermistor, or a multilayer electronic component, and electronic components other than the multilayer electronic components.