Device and method for generating a differential voltage

The present invention relates to a device and a method for generating a differential voltage.

To generate a differential voltage, a first terminal is connected to a supply voltage via a first switch and a first current limiting and a second terminal is connected to ground via a second switch and a second current limiting. Since the switches do not switch at exactly the same time and the currents swell to a differently strong extent at the terminals depending on the temperature and aging, common-mode interferences develop which interfere with the differential signal transfer in the further course due to asymmetric conductor guidance.

Common-mode interferences due to asymmetric signal generation should be avoided, so that the signals are less interfered with.

The present invention provides the advantage that common-mode interferences due to asymmetric signal generation are prevented. Thus, the signals are less interfered with.

It is provided to generate a corresponding differential signal with the aid of a current from an electrically isolated energy source.

In the embodiment according to the present invention, a capacitor C 1 may be charged when switches S 3 and S 4 are closed, switches S 1 and S 2 being open at the same time. After charging the capacitor, switches S 3 and S 4 are opened. To generate a differential voltage, switches S 1 and S 2 are closed. Due to the electrical isolation, it is possible to open and close switches S 1 and S 2 with a time delay, without an undesirable common-mode signal resulting therefrom. The currents via switches S 1 and S 2 and thus at corresponding terminals L and H always have exactly the same absolute value.

Preferably, those capacitors should be used which may be implemented in silicon. To generate longer signals, a second parallel circuit according to the present invention is thus provided, it being possible to permanently achieve a desired level.

It is also possible to generate a negative level, as is implemented in a third specific embodiment.

Additional advantages and advantageous embodiments may be derived from the description of the figures and the drawings.

FIG. 1 shows a circuit drawing of one exemplary embodiment of the circuit according to the present invention.

FIG. 2 shows a circuit drawing of a second exemplary embodiment of the circuit according to the present invention.

FIG. 3 shows a circuit drawing of a third exemplary embodiment of the circuit according to the present invention.

FIG. 4 shows a flow chart of one exemplary embodiment of the method according to the present invention.

FIG. 5 shows a flow chart of a second exemplary embodiment of the method according to the present invention.

FIG. 1 shows a circuit for generating differential voltages. The differential voltage is measured at terminals H and L. A current limiting I lim , a switch S 1 , a first capacitor C 1 , and a switch S 2 are connected between terminals H and L.

First capacitor C 1 is provided to facilitate a current flow I 1 from terminal L to terminal H in the charged state. A current cannot flow from L to H until both switches S 1 and S 2 are closed. The currents via S 1 and S 2 and thus at terminals L and H have exactly the same absolute value, regardless of temperatures, aging, or the like. If, for example, a differential voltage of 2 volts is to be achieved and the cable impedance is 60 ohm, then the current is limited to 33 mA with the aid of current limiting I lim . It is also conceivable, however, that larger or smaller currents flow, so that the desired differential voltage may be achieved faster or have a higher degree of accuracy.

In this process, first capacitor C 1 is discharged.

In order to charge first capacitor C 1 , two further switches S 3 and S 4 are provided. When switches S 3 and S 4 are closed, a potential V CC is connected to GND via first capacitor C 1 and first capacitor C 1 is charged.

FIG. 2 shows a circuit for generating differential voltages. The design is similar to the design of the circuit, such as the one shown in FIG. 1 , a second capacitor C 2 being connected in parallel to first capacitor C 1 . Second capacitor C 2 is connected between the two switches S 5 and S 6 .

If first capacitor C 1 is exhausted, although the differential voltage is to be continuously maintained, second capacitor C 2 is provided to facilitate the flow of current I 2 from L to H. Current I 2 flows from L to H, when both switches S 5 and S 6 are closed. During this time, first capacitor C 1 may be recharged, so that its energy is available as soon as second capacitor C 2 requires charging.

In order to charge second capacitor C 2 , two further switches S 7 and S 8 are provided. When switches S 7 and S 8 are closed, a potential V CC is connected to GND via second capacitor C 2 and second capacitor C 2 is charged.

As a result of the mutual support of capacitors C 1 and C 2 , it is possible to permanently achieve a desired voltage level, while the capacitors may have smaller dimensions, since they must be able to store only a fraction of the energy necessary to transfer one or multiple bits.

If the supply is switched from first capacitor C 1 to second capacitor C 2 , switches S 5 and S 6 are closed in addition to already closed switches S 1 and S 2 and then switches S 1 and S 2 are opened. Two diodes D 1 and D 2 are tasked with allowing switches S 1 , S 2 , S 5 , and S 6 to be closed simultaneously, without a high compensating current being able to flow from one of capacitors C 1 , C 2 to the respective other capacitor. As soon as switches S 1 and S 2 are open, first capacitor C 1 may be charged when switches S 3 and S 4 are closed.

FIG. 3 shows two circuits, such as the ones shown in FIG. 2 , connected in series.

If negative differential voltage changes or negative differential voltages are supposed to be generated, switches S 11 through S 18 are actuated in the same manner as switches S 1 through S 8 .

FIG. 4 shows a flow chart of the method according to the present invention for generating differential voltages.

At beginning 100 , a first capacitor C 1 is charged. In a step 110 , a switch S 1 and a switch S 2 are closed. Thereupon, a current I 1 flows from a terminal L to a terminal H. As a result, first capacitor C 1 is discharged. In [step] 120 , switches S 3 and S 4 are closed. As a result, a potential V CC is connected to GND via first capacitor C 1 and first capacitor C 1 is charged.

FIG. 5 shows a flow chart of the method according to the present invention for generating differential voltages.

At beginning 100 , a first capacitor C 1 is charged. In step 110 , switch S 1 and switch S 2 are closed. Thereupon, a current I 1 flows from a terminal L to a terminal H. As a result, first capacitor C 1 is discharged.

In [step] 120 , switches S 5 and S 6 are closed. The two diodes D 1 and D 2 are tasked with allowing switches S 1 , S 2 , S 5 , and S 6 to be closed simultaneously, without a high compensating current being able to flow from one of capacitors C 1 , C 2 to the respective other capacitor. In [step] 130 , switches S 1 and S 2 are opened. As soon as switches S 1 and S 2 are open, switches S 3 and S 4 are closed, so that first capacitor C 1 may be charged.