Current sensing circuit and integrated circuit for four-switch buck-boost convertor

This application claims the benefit of CN application 201710730990.8, filed on Aug. 23, 2018, and incorporated herein by reference.

The present invention relates generally to electrical circuits, and more particularly but not exclusively to current sensing circuits.

Portable electronic devices are becoming smaller and smaller, which accordingly causes the volume and capacity of their batteries to decrease. In order to improve endurance of the batteries, power supply modules of these electronic devices are required to provide a stable output voltage when the battery voltage varies in a wide range. Four-switch buck-boost converters thus are widely used in these applications.

A four-switch buck-boost converter typically requires the input current, the output current and/or the inductor current to be sensed in some way to control the power switches and/or to protect the converter. Conventionally, the inductor current is sensed by placing a sensing resistor in series with the inductor, the voltage across the sensing resistor is detected using a sensing amplifier to produce a signal proportional to the inductor current. This type of current sensing approach has the drawback of adding power dissipated in the sensing resistor thereby reducing the overall efficiency of the buck-boost converter.

Alternatively, it is known to use one of the power switches as a sensing resistor and detect the voltage drop across the internal resistance between drain and source of the MOS device (RDSON). This alternative approach overcomes the efficiency reduction caused by a sensing resistor. Nevertheless, since the four power switches in the buck-boost converter are controlled and driven for three different working modes including a buck mode, a boost mode and a buck-boost mode, the current flowing though one of the power switches is simply a part of the inductor current, so multiple current sensing circuits are required to respectively detect the current flowing though each power switch. However, each of multiple current sense circuits is dependent on the different circuit configurations, which increases the cost and size of the system application, and also increases the complexity of a control circuit and the current sense circuits.

Accordingly, a simpler current sensing circuit used for a four-switch buck-boost converter is required to at least address one or some of the above deficiencies.

Embodiments of the present invention are directed to a current sensing circuit for a buck-boost converter, wherein the buck-boost converter comprises a first high side switch and a first low side switch which are couple in series between an input voltage and a ground and a second high side switch and a second low side switch which are coupled in series between an output voltage and the ground, the current sensing circuit comprises a first normally-ON transistor, a second normally-ON transistor, a first sensing circuit and a second sensing circuit. The first normally-ON transistor has a first terminal and a second terminal, wherein during a turn ON time of the first low side switch, the first terminal is coupled to the ground, and during a turn ON time of the second low side switch, the first terminal is coupled to a second switch node that is connected to a terminal of the second high side switch and a terminal of the second low side switch. The second normally-ON transistor has a first terminal and a second terminal, wherein during the turn ON time of the first low side switch, the first terminal is coupled to a first switch node that is connected to a terminal of the first high side switch and a terminal of the first low side switch, and during the turn ON time of the second low side switch, the first terminal is coupled to the ground. The first sensing circuit having a first input terminal coupled to the second terminal of the first normally-ON transistor, a second input terminal coupled to the second terminal of the second normally-ON transistor and an output terminal configured to provide detection current. The second sensing circuit detects an average value of the detection current and provides a current sensing signal in accordance with the average value of the detection current, wherein during the turn ON time of the first low side switch, the detection current represents a current flowing though the first low side switch, the current sensing signal represents an output current of the buck-boost converter, and during the turn ON time of the second low side switch, the detection current represents a current flowing though the second low side switch, the current sensing signal represents an input current of the buck-boost converter.

Non-limiting and non-exhaustive embodiments are described with reference to the following drawings. The drawings are only for illustration purpose. These drawings are not necessarily drawn to scale. The relative sizes of elements illustrated by the drawings may differ from the relative size depicted.

FIG. 1 shows a schematic diagram of a four-switch buck-boost converter 100 in accordance with an embodiment of the present invention.

FIG. 2 shows a circuit diagram of a four-switch buck-boost converter 200 in accordance with an embodiment of the present invention.

FIG. 3 shows a waveform diagram of signals of the buck-boost converter 200 in FIG. 2 working in a buck mode in accordance with an embodiment of the present invention.

FIG. 4 shows a waveform diagram of signals of the buck-boost converter 200 in FIG. 2 working in a boost mode in accordance with an embodiment of the present invention.

FIG. 5 shows a circuit diagram of a four-switch buck-boost converter 300 in accordance with an embodiment of the present invention.

FIG. 6 shows a waveform diagram of signals of the buck-boost converter 300 in FIG. 5 working in a buck mode in accordance with an embodiment of the present invention.

FIG. 7 shows a waveform diagram of signals of the buck-boost converter 300 in FIG. 5 working in a boost mode in accordance with an embodiment of the present invention.

FIG. 8 shows a waveform diagram of signals of the buck-boost converter 300 in FIG. 5 working in a buck-boost mode in accordance with an embodiment of the present invention.

The use of the same reference label in different drawings indicates the same or like components.

Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

FIG. 1 shows a schematic diagram of a four-switch buck-boost converter 100 in accordance with an embodiment of the present invention. In the embodiment of FIG. 1 , the buck-boost converter 100 is configured to convert an input voltage VIN to an output voltage VOUT, and comprises a pair of buck switches, a pair of boost switches, an inductor L, an output capacitor COUT, and a current sensing circuit. Wherein the pair of buck switches has a first high side switch S 1 and a first low side switch S 2 which are coupled in series between the input voltage VIN and a ground. The pair of boost switches has a second high side switch S 4 and a second low side switch S 3 which are coupled in series between the output voltage VOUT and the ground. The pair of buck switches has a first switch node SW 1 that is connected to a terminal of the first high side switch S 1 and a terminal of the first low side switch S 2 , the pair of boost switches has a second switch node SW 2 that is connected to a terminal of the second high side switch S 4 and a terminal of the second low side switch S 3 . The switches in the buck-boost converter 100 may be any controllable semiconductor devices, such as MOSFET (metal oxide semiconductor field effect transistor), IGBT (isolated gate bipolar transistor) and so on.

As shown in FIG. 1 , the first high side switch S 1 has a drain terminal, a source terminal and a gate terminal, wherein the drain terminal is coupled to the input voltage VIN, the source terminal is coupled to the first switch node SW 1 , and the gate terminal is configured to receive a buck control signal CTRL 1 generated by a driving circuit. The first low side switch S 2 has a drain terminal, a source terminal and a gate terminal, wherein the drain terminal is coupled to the first switch node SW 1 , the source terminal is coupled to the ground, and the gate terminal is configured to receive the buck control signal CTRL 1 through an inverter N 1 . The second low side switch S 3 has a drain terminal, a source terminal and a gate terminal, wherein the drain terminal is coupled to the second switch node SW 2 , the source terminal is coupled to the ground, and the gate terminal is configured to receive a boost control signal CTRL 2 generated by the driving circuit. The second high side switch S 4 has a drain terminal, a source terminal and a gate terminal, wherein the drain terminal is coupled to the output voltage VOUT, the source terminal is coupled to the second switch node SW 2 , and the gate terminal is configured to receive the boost control signal CTRL 2 through an inverter N 2 . The inductor L has a first terminal coupled to the first switch node SW 1 and a second terminal coupled to the second switch node SW 2 . The output capacitor COUT has a first terminal coupled to the output voltage VOUT and a second terminal coupled to the ground.

Conventionally, the buck-boost converter 100 has two operational modes including a buck mode and a boost mode. In the buck mode, the second high side switch S 4 is turned ON, the second low side switch S 3 is turned OFF, the first high side switch S 1 and the first low side switch S 2 are turned ON and OFF alternatively by the buck control signal CTRL 1 so as to convert the input voltage VIN to the output voltage VOUT. During a turn ON time of the first low side switch S 2 , a current I 1 is flowing from the ground to the first switch node SW 1 through the first low side switch S 2 . In the boost mode, the first high side switch S 1 is turned ON, the first low side switch S 2 is turned OFF, the second high side switch S 4 and the second low side switch S 3 are turned ON and OFF alternatively by the boost control signal CTRL 2 so as to convert the input voltage VIN to the output voltage VOUT. During a turn ON time of the second low side switch S 3 , a current I 2 is flowing from the second switch node SW 2 to the ground through the second low side switch S 3 . In one embodiment, the method of controlling the pair of buck switches or the pair of boost switches may apply PWM (Pulse Width Modulation). In another embodiment, the method of controlling the pair of buck switches may apply COT (Constant ON-Time), the method of controlling the pair of boost switches may apply COFT (Constant OFF-Time).

In the embodiment of FIG. 1 , in the buck mode, during the turn ON time of the first low side switch S 2 , the current sensing circuit is configured to detect the current I 1 flowing through the first low side switch S 2 and to provide a current sensing signal ICS representing an output current of the buck-boost converter 100 . In the boost mode, during the turn ON time of the second low side switch S 3 , the current sensing circuit is configured to detect the current I 2 flowing through the second low side switch S 3 and to provide the current sensing signal ICS that represents an input current of the buck-boost converter 100 . The current sensing signal ICS may be a detection voltage signal which is proportional to the current flowing through a resistor R 0 , the detection voltage signal represents the output current in the buck mode and represents the input current in the boost mode, respectively.

FIG. 2 shows a circuit diagram of a four-switch buck-boost converter 200 in accordance with an embodiment of the present invention. In the embodiment of FIG. 2 , when the buck-boost converter 200 works in the buck mode, the current sensing circuit is configured to detect the current I 1 flowing through the first low side switch S 2 during the turn ON time of the first low side switch S 2 and provides the current sensing signal ICS that represents the output current. When the buck-boost converter 200 works in the boost mode, the current sensing circuit is configured to detect the current I 2 flowing through the second low side switch S 3 during the turn ON time of the second low side switch S 3 and provides the current sensing signal ICS that represents the input current.

In the embodiment of FIG. 2 , the current sensing circuit comprises a pair of sensing transistors 202 having a first normally-ON transistor MS 1 and a second normally-ON transistor MS 2 , a first sensing circuit 203 and a second sensing circuit 204 . In one embodiment, the first and second normally-ON transistors MS 1 and MS 2 are driven by a supply voltage VCC to keep continuous conduction. In another embodiment, the continuous conduction of the first and second normally-ON transistors MS 1 and MS 2 may be controlled by other voltage instead of the supply voltage VCC. The first and second normally-ON transistors MS 1 and MS 2 are matching and of a same type of transistor. Either of the first low side switch S 2 and the second low side switch S 3 has a larger size of the same type of transistor of the first and second normally-ON transistors MS 1 and MS 2 .

The first normally-ON transistor MS 1 has a first terminal and a second terminal, wherein during the turn ON time of the first low side switch S 2 , the first terminal is coupled to the ground, and during the turn ON time of the second low side switch S 3 , the first terminal is coupled to the second switch node SW 2 . The second normally-ON transistor MS 2 has a first terminal and a second terminal, wherein during the turn ON time of the first low side switch S 2 , the first terminal is coupled to a first switch node SW 1 , and during the turn ON time of the second low side switch S 3 , the first terminal is coupled to the ground.

In the embodiment of FIG. 2 , the current sensing circuit further comprises a switch array 201 . The switch array 201 comprises a first switch M 1 , a second switch M 2 , a third switch M 3 and a fourth switch M 4 , each of which has a source terminal, a drain terminal and a gate terminal. And wherein the drain terminal of the first switch M 1 is coupled to the first switch node SW 1 , the source terminal of the first switch M 1 is coupled to the first terminal of the second normally-ON transistor MS 2 , the gate terminal of the first switch M 1 is coupled to the buck control signal CTRL 1 . The drain terminal of the second switch M 2 is coupled to the ground, the source terminal of the second switch M 2 is coupled to the first terminal of the second normally-ON transistor MS 2 , the gate terminal of the second switch M 2 is coupled to the buck control signal CTRL 2 through an inverter N 11 . The drain terminal of the third switch M 3 is coupled to the second switch node SW 2 , the source terminal of the third switch M 3 is coupled to the first terminal of the first normally-ON transistor MS 1 , the gate terminal is coupled to the boost control signal CTRL 2 . The drain terminal of the fourth switch M 4 is coupled to the ground, the source terminal of the fourth switch M 4 is coupled to the first terminal of the first normally-ON transistor MS 1 , the gate terminal is coupled to the boost control signal CTRL 2 through an inverter N 22 . In a first state of the switch array 201 , the first low side switch S 2 is turned ON, the first switch M 1 and the fourth switch M 4 are turned ON, the second switch M 2 and the third switch M 3 are turned OFF. In a second state of the switch array 201 , the second low side switch S 3 is turned ON, the first switch S 1 and the fourth switch S 4 are turned OFF, the second switch M 2 and the third switch M 3 are turned ON. In a third state of the switch array 201 , the first and second low side switches S 2 and S 3 are turned OFF, the first and third switches M 1 and M 3 are turned OFF, the second and fourth switches M 2 and M 4 are turned ON.

The first sensing circuit 203 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the second terminal of the first normally-ON transistor MS 1 , the second input terminal is coupled to the second terminal of the second normally-ON transistor MS 2 , the output terminal is configured to provide the detection current ISEN that represents a current flowing through one of the first and second low side switches S 2 and S 3 currently conducting. More specifically, the first sensing circuit 203 may not only, in the first state of the switch array 201 , provides the detection current ISEN that represents the current I 1 flowing though the first low side switch S 2 during the turn ON time of the first low side switch S 2 , but also, in the second state of the switch array 201 , provides the detection current ISEN that represents the current I 2 flowing though the second low side switch S 3 during the turn ON time of the second low side switch S 3 .

In the embodiment of FIG. 2 , the first sensing circuit 203 comprises a first operational amplifier OP 1 , a transistor Q 1 and a resistor R 1 . The first operational amplifier OP 1 has a non-inversing terminal coupled to the second terminal of the first normally-ON transistor MS 1 , an inversing terminal coupled to the second terminal of the second normally-ON transistor MS 2 , and an output terminal. The transistor Q 1 comprises an N type DMOS (Double Diffused Metal Oxide Semiconductor) transistor. The transistor Q 1 has a drain terminal coupled to a first terminal of the resistor R 1 , a source terminal coupled to the inverting terminal of the first operational amplifier OP 1 , and a gate terminal coupled to the output terminal of the first operation amplifier OP 1 . A second terminal of the resistor R 1 is coupled to the supply voltage VCC.

Assuming the voltage at the non-inverting input terminal of the first operational amplifier OP 1 is VP 1 , and the voltage at the inverting input terminal of the first operational amplifier OP 1 is VN 1 . When the first low side switch S 2 is turned ON, as can be deviated from the circuit in FIG. 2 , VP 1 =VSW 1 +I 1 *RdsON 1 , and VN 1 =VSW 1 +ISEN*RdsONs 2 . Because the voltages at two input terminals of the first operational amplifier OP 1 are equal, i.e., VP 1 =VN 1 , as a result, ISEN=I 1 *(RdsON 1 /RdsONs 2 ). Wherein RdsON 1 is the ON resistance of the first low side switch S 2 and RdsONs 2 is the ON resistance of the second normally-ON transistor MS 2 . Similarly, when the second low side switch S 3 is turned ON, as can be deviated from the circuit in FIG. 2 , VP 1 =I 2 *RdsON 2 , and VN 1 =ISEN*RdsONs 2 . Because VP 1 =VN 1 , ISEN=I 2 *(RdsON 2 /RdsONs 2 ), wherein RdsON 2 is the ON resistance of the second low side switch S 3 . So during the turn ON time of the first low side switch S 2 , the detection current ISEN is directly proportional to the current I 1 flowing through the first low side switch S 2 , with a proportionality RdsON 1 /RdsONs 2 . In other words, the detection current ISEN can represent the current I 1 flowing through the first low side switch S 2 during the turn ON time of the first low side switch S 2 . During the turn ON time of the second low side switch S 3 , the detection current ISEN is directly proportional to the current I 2 flowing through the second low side switch S 2 , with a proportionality RdsON 2 /RdsONs 2 . In other words, the detection current ISEN can represent the current I 2 flowing through the second low side switch S 3 during the turn ON time of the second low side switch S 3 . The detection current ISEN flows through the transistor Q 1 and the resistor R 1 , a detection voltage across the resistor R 1 is generated and can represent the current I 1 flowing through the first low side switch S 2 or the current I 2 flowing through the second low side switch S 3 .

The second sensing circuit 204 comprises a transistor Q 2 , a capacitor C 1 , a resistor R 2 , a second operational amplifier OP 2 , a transistor Q 3 and a resistor R 0 . The second sensing circuit 204 is configured to sample an average of the detection current ISEN through the transistor Q 2 and holds the average of the detection current ISEN as charge stored in the capacitor C 1 .

Those of skill in the art will appreciate that the detection current ISEN can represent the current I 1 flowing through the first low side switch S 2 or the current I 2 flowing through the second low side switch S 3 , and thus the average of the detection current ISEN also can represent the average of the current I 1 or the average of the current I 2 . The average of the current I 1 is detected by sampling the current I 1 at the midpoint of the turn ON time of the first low side switch S 2 . The average of the current I 2 is detected by sampling the current I 2 at the midpoint of the turn ON time of the second low side switch S 3 .

The transistor Q 2 has a drain terminal, a source terminal and a gate terminal, wherein the drain terminal is coupled to a first terminal of the resistor R 1 , a gate terminal is coupled to a control signal SH 1 . The second operational amplifier OP 2 has a non-inverting terminal, an inverting terminal and an output terminal, wherein the non-inverting terminal is coupled to the supply voltage VCC and a first terminal of the capacitor C 1 through a resistor R 2 , the inverting terminal is coupled to the source terminal of the transistor Q 2 and a second terminal of the capacitor C 1 . The transistor Q 3 has a drain terminal, a source terminal and a gate terminal, wherein the drain terminal is coupled to the non-inverting terminal of the second operational amplifier OP 2 , the source terminal is coupled to the ground through the resistor R 0 , the gate terminal is coupled to the output terminal of the operational amplifier OP 2 . In one embodiment, the resistance of the resistors R 1 and R 2 is equal or matching.

In the embodiment of FIG. 2 , when the control signal SH 1 coupled to the gate terminal of the transistor Q 2 is logic high, the transistor Q 2 is turned ON, the second sensing circuit 204 detects an average of the detection current ISEN. When the control signal SH 1 is logic low, the transistor Q 2 is turned OFF, the second sensing circuit 204 holds the average of the detection current ISEN as charge stored in the capacitor C 1 . The control signal SH 1 may be generated by a controller (not shown) or another circuit without detracting from the merits of the present invention.

More specifically, when the buck-boost converter 200 works in the buck mode and the first low side switch S 2 is turned ON, the average of the detection current ISEN is detected and held as the charge stored in the capacitor C 1 at the midpoint of the turn ON time of the first low side switch S 2 , the charge stored in the capacitor C 1 is configured to generate the current sensing signal ICS that represents the output current. And when the buck-boost converter 200 works in the boost mode and the second low side switch S 3 is turned ON, the average of the detection current ISEN is detected and held as the charge stored in the capacitor C 1 at the midpoint of the turn ON time of the second low side switch S 3 , the charge stored in the capacitor C 1 is configured to generate the current sensing signal ICS that represents the input current.

In the embodiment of FIG. 2 , the current sensing circuit further comprises a bias current source 206 . The bias current source 206 has a first terminal coupled to the supply voltage VCC and a second terminal coupled to the first input terminal of the first sensing circuit 203 , to provide a bias current IOFFSET. Those of skill in the art will appreciate that, in other embodiment, the bias current source 206 may be coupled to one or more of the first input terminal and the second input terminal of the first sensing circuit 203 , to provide the bias current IOFFSET.

In one embodiment, the resistor R 2 with variable resistance is configured to trim the integrated circuit after its manufacture to improve mismatch and temperature excursion.

FIG. 3 shows a waveform diagram of signals of the buck-boost converter 200 in FIG. 2 working in a buck mode in accordance with an embodiment of the present invention. FIG. 3 shows the switch signal at the first switch node SW 1 (plot 151 ), the switch signal at the second switch node SW 2 (plot 152 ), the inductor current IL (plot 153 ), the buck control signal CTRL 1 for the pair of buck switches (plot 155 ), the gate signal SH 1 driving the transistor Q 2 (plot 156 ), and the voltage VC 1 on the capacitor C 1 (plot 157 ).

Referring to FIGS. 2 and 3 , when the buck-boost converter 200 works in the buck mode, the second high side switch S 4 is turned ON, the second low side switch S 3 is turned OFF, the fourth switch M 4 is turned ON, the third switch M 3 is turned OFF. The first high side switch S 1 and the first low side switch S 2 are turned ON and OFF alternatively by the buck control signal CTRL 1 . When the buck control signal CTRL 1 is logic low, the first low side switch S 2 and the first switch M 1 are turned ON, the second switch M 2 is turned OFF, the first input terminal of the first sensing circuit 203 is coupled to the ground through the first normally-ON transistor MS 1 , the second input terminal of the first sensing circuit 203 is coupled to the first switch node SW 1 through the second normally-ON transistor MS 2 . The first operational amplifier OP 1 of the first sensing circuit 203 is configured to detect the current I 1 flowing through the first low side switch S 2 and to drive the transistor Q 1 to generate the detection current ISEN that represents the current I 1 , the detection current ISEN flows through the resistor R 1 to generate a detection voltage signal that can represent the current I 1 . At the start of the period T 0 , the control signal SH 1 transits in logic high, the transistor Q 2 is turned ON, the detection voltage signal on the resistor R 2 starts to charge the capacitor C 1 to sample to the value of the detection current ISEN. Upon the end of the period T 0 , i.e. at the midpoint of the turn ON time of the first low side switch S 2 , the transistor Q 2 is turned OFF and the average of the detection current ISEN is stored as the charge in the capacitor C 1 . The input terminals of the second operational amplifier OP 2 in the second sensing circuit 204 are coupled across the capacitor C 1 , and the second operational amplifier OP 2 is configured to generate the current sensing signal ICS that represents the average of the detection current ISEN in accordance with the charge stored in the capacitor C 1 .

In the example of FIG. 3 , the buck-boost converter 200 works in a buck mode, the output current IOUT and the current sensing signal ICS satisfy an equation that: IOUT=ICS, the input current IIN and the current sensing signal ICS satisfy an equation that: IIN=ICS*D 1 , wherein the D 1 is the duty cycle of the buck control signal CTRL 1 .

FIG. 4 shows a waveform diagram of signals of the buck-boost converter 200 in FIG. 2 working in a boost mode in accordance with an embodiment of the present invention. FIG. 4 shows the switch signal at the first switch node SW 1 (plot 161 ), the switch signal at the second switch node SW 2 (plot 162 ), the inductor current IL (plot 163 ), the boost control signal CTRL 2 for the pair of boost switches (plot 165 ), the gate signal SH 1 driving the transistor Q 2 (plot 166 ), and the voltage VC 1 on the capacitor C 1 (plot 167 ).

Referring to FIGS. 2 and 4 , when the buck-boost converter 200 works in the boost mode, the first high side switch S 1 is turned ON, the first low side switch S 2 is turned OFF, the second switch M 2 is turned ON, the first switch M 1 is turned OFF. The second high side switch S 4 and the second low side switch S 3 are turned ON and OFF alternatively by the boost control signal CTRL 2 . When the boost control signal CTRL 2 is logic high, the second low side switch S 3 and the third switch M 3 are turned ON, the fourth switch M 4 is turned OFF, the first input terminal of the first sensing circuit 203 is coupled to the second switch node SW 2 through the first normally-ON transistor MS 1 , the second input terminal of the first sensing circuit 203 is coupled to the ground through the second normally-ON transistor MS 2 . The first operational amplifier OP 1 of the first sensing circuit 203 is configured to detect the current I 2 flowing through the second low side switch S 3 and to drive the transistor Q 1 to generate the detection current ISEN that represents the current I 2 , the detection current ISEN flows through the resistor R 1 to generate the detection voltage signal that can represent the current I 2 .

At the start of the period T 1 , the control signal SH 1 transits in logic high, the transistor Q 2 is turned ON, the detection voltage signal on the resistor R 1 starts to charge the capacitor C 1 to sample to the value of the detection current ISEN. Upon the end of the period T 1 , i.e. at the midpoint of the turn ON time of the second low side switch S 3 , the transistor Q 2 is turned OFF and the average of the detection current ISEN is held as the charge stored in the capacitor C 1 . The input terminals of the second operational amplifier OP 2 in the second sensing circuit 204 are coupled across the capacitor C 1 , and the second operational amplifier OP 2 is configured to generate the current sensing signal ICS that represents the average of the detection current ISEN in accordance with the charge stored in the capacitor C 1 . In the example of FIG. 4 , the buck-boost converter 200 works in a boost mode, the input current IIN and the current sensing signal ICS satisfy an equation that: IIN=ICS, the output current IOUT and the current sensing signal ICS satisfy an equation that: IOUT=ICS*(1−D 2 ), wherein the D 2 is the duty cycle of the boost control signal CTRL 2 .

FIG. 5 shows a circuit diagram of a four-switch buck-boost converter 300 in accordance with an embodiment of the present invention. The circuit of the buck-boost converter 300 in FIG. 5 is different from that of the buck-boost converter 200 shown in FIG. 2 . A major difference is that a first sensing circuit 203 A comprises a first auto-zero amplifier OP 3 instead of the first operational amplifier OP 1 , a second sensing circuit 204 A comprises a second auto-zero amplifier OP 4 instead of the second operational amplifier OP 2 .

In the embodiment of FIG. 5 , the first sensing circuit 203 A comprises the first auto-zero amplifier OP 3 , the transistor Q 1 and the resistor R 1 . The first auto-zero amplifier OP 3 has a non-inverting terminal, an inverting terminal, a clock input terminal and an output terminal, wherein the non-inverting terminal is coupled to the second terminal of the second normally-ON transistor MS 2 , the inverting terminal is coupled to the second terminal of the first normally-ON transistor MS 1 , the clock input terminal is coupled to the first clock signal CLK 1 . The transistor Q 1 has a drain terminal, a source terminal and a gate terminal, wherein the drain terminal is coupled to the first terminal of the resistor R 1 , the source terminal is coupled to the inverting terminal of the first auto-zero amplifier OP 3 , the gate terminal is coupled to the output terminal of the first auto-zero amplifier OP 3 . A second terminal of the resistor R 1 is coupled to the supply voltage VCC.

The second sensing circuit 204 A comprises a transistor Q 2 , a capacitor C 1 , a resistor R 2 , a second auto-zero amplifier OP 4 , a transistor Q 3 and a resistor R 0 . The transistor Q 2 has a drain terminal, a source terminal and a gate terminal, wherein the drain terminal is coupled to the first terminal of the resistor R 1 , the gate terminal is coupled to the control signal SH 1 . The second auto-zero amplifier OP 2 has a non-inverting terminal, an inverting terminal, a clock input terminal and an output terminal, wherein the non-inverting terminal is coupled to the supply voltage VCC through the resistor R 2 and is coupled to a first terminal of the capacitor C 1 , the inverting terminal is coupled to the source terminal of the transistor Q 2 and a second terminal of the capacitor C 1 , the clock input terminal is coupled to the second clock signal CLK 2 . In one embodiment, the second clock signal CLK 2 is complementary with the first clock signal CLK 1 . The transistor Q 3 has a drain terminal, a source terminal and a gate terminal, wherein the drain terminal is coupled to the non-inverting terminal of the second auto-zero amplifier OP 4 , the source terminal is coupled to the ground through the resistor R 0 , the gate terminal is coupled to the output terminal of the second auto-zero amplifier OP 4 . In one embodiment, the resistance of the resistors R 1 and R 2 is matching. In one embodiment, the resistor R 2 with variable resistance is configured to trim the integrated circuit after its manufacture to improve mismatch and temperature excursion.

An auto-zero amplifier has two working modes including an outputting mode and a zeroing mode. In the outputting mode of the auto-zero amplifier, an error signal is stored in a holding circuit, subsequently, in the zeroing mode of the auto-zero amplifier, the error signal previously stored is added to a main amplifier unit of the auto-zero amplifier to cancel out the offset. Traditionally, the auto-zero amplifier is configured to operate in one of the outputting mode and the zeroing mode, and this switching is accomplished by applying a clock signal generated by a timer to the internal analog switch elements of the auto-zero amplifier. In one embodiment, the first clock signal CLK 1 and the second clock signal CLK 2 are complementary and have duty cycles of 0.5. In the embodiment of FIG. 5 , when the first clock signal CLK 1 is logic high, the second clock signal CLK 2 is logic low, the first auto-zero amplifier OP 3 is at the outputting mode, the second auto-zero amplifier OP 3 is at the zeroing mode. When the first clock signal CLK 1 is logic low, the second clock signal CLK 2 is logic high, the second auto-zero amplifier OP 4 is at the outputting mode, the first auto-zero amplifier OP 3 is at the zeroing mode. The first clock signal CLK 1 and the second clock signal CLK 2 are related to the frequency of the buck control signal CTRL 1 or the boost control signal CTRL 2 . Accordingly, the first clock signal CLK 1 and the second clock signal CLK 2 may be generated by a controller (not shown) or another circuit (e.g. 210 ) without detracting from the merits of the present invention. Several of the details of the embodiments described below with reference to FIGS. 6-8 .

FIG. 6 shows a waveform diagram of signals of the buck-boost converter 300 in FIG. 5 working in a buck mode in accordance with an embodiment of the present invention. FIG. 6 shows the switch signal at the first switch node SW 1 (plot 171 ), the switch signal at the second switch node SW 2 (plot 172 ), the inductor current IL (plot 173 ), the buck control signal CTRL 1 for the pair of buck switches (plot 175 ), the gate signal SH 1 driving the transistor Q 2 (plot 176 ), and the voltage VC 1 on the capacitor C 1 (plot 177 ), the first clock signal CLK 1 for the first auto-zero amplifier OP 3 (plot 178 ) and the second clock signal CLK 2 for the second auto-zero amplifier OP 4 (plot 179 ).

Referring to FIGS. 5 and 6 , when the buck-boost converter 300 works in the buck mode, the second high side switch S 4 is turned ON, the second low side switch S 3 is turned OFF, the fourth switch M 4 is turned ON, the third switch M 3 is turned OFF. The first high side switch S 1 and the first low side switch S 2 are turned ON and OFF alternatively by the buck control signal CTRL 1 .

During the period of T 2 , the first clock signal CLK is logic high, and the second clock signal CLK 2 is logic low, the first auto-zero amplifier OP 3 is at the outputting mode, the second auto-zero amplifier OP 4 is at the zeroing mode. In the embodiment of FIG. 6 , the frequency of the buck control signal CTRL 1 is twice as much as that of the first clock signal CLK 1 or the second clock signal CLK 2 . In other embodiment, the frequency of the buck control signal CTRL 1 is 2*N times as much as that of the first clock signal CLK 1 or the second clock signal CLK 2 , wherein N is an integer higher than 1.

During the period of T 4 , the control signal SH 1 is logic high and the buck control signal CTRL 1 is logic low, the first low side switch S 2 and the first switch M 1 are turned ON, the second switch M 2 is turned OFF, the first auto-zero amplifier OP 3 at the outputting mode is configured to detect the current I 1 flowing through the first low side switch S 2 and to generate the detection current ISEN that represents the current I 1 . During the period of T 4 , the transistor Q 2 is turned ON, the detection voltage signal on the resistor R 1 starts to charge the capacitor C 1 to sample the value of the detection current ISEN. Upon the end of the period T 4 , i.e. at the midpoint of the turn ON time of the first low side switch S 2 , the transistor Q 2 is turned OFF and the average of the detection current ISEN is held as the charge stored in the capacitor C 1 . During the period of T 3 , the second auto-zero amplifier OP 4 at the zeroing mode is configured to generate the detection current ICS in accordance with the charge stored in the capacitor C 1 .

In the example of FIG. 6 , the buck-boost converter 300 works in a buck mode, the output current IOUT and the current sensing signal ICS satisfy an equation that: IOUT=ICS, the input current IIN and the current sensing signal ICS satisfy an equation that: IIN=ICS*D 1 , wherein the D 1 is the duty cycle of the buck control signal CTRL 1 .

FIG. 7 shows a waveform diagram of signals of the buck-boost converter 300 in FIG. 5 working in a boost mode in accordance with an embodiment of the present invention. FIG. 7 shows the switch signal at the first switch node SW 1 (plot 181 ), the switch signal at the second switch node SW 2 (plot 182 ), the inductor current IL (plot 183 ), the boost control signal CTRL 2 for the pair of boost switches (plot 185 ), the gate signal SH 1 driving the transistor Q 2 (plot 186 ), and the voltage VC 1 on the capacitor C 1 (plot 187 ), the first clock signal CLK 1 for the first auto-zero amplifier OP 3 (plot 188 ) and the second clock signal CLK 2 for the second auto-zero amplifier OP 4 (plot 189 ).

Referring to FIGS. 5 and 7 , when the buck-boost converter 300 works in the boost mode, the first high side switch S 1 is turned ON, the first low side switch S 2 is turned OFF, the second switch M 2 is turned ON, the first switch M 1 is turned OFF. The second high side switch S 4 and the second low side switch S 3 are turned ON and OFF alternatively by the boost control signal CTRL 2 .

During the period of T 5 , the first clock signal CLK is logic high, and the second clock signal CLK 2 is logic low, the first auto-zero amplifier OP 3 is at the outputting mode, the second auto-zero amplifier OP 4 is at the zeroing mode. During the period of T 6 , the first clock signal CLK is logic low, and the second clock signal CLK 2 is logic high, the first auto-zero amplifier OP 3 is at the zeroing mode, the second auto-zero amplifier OP 4 is at the outputting mode. In the embodiment of FIG. 7 , the frequency of the boost control signal CTRL 2 is twice as much as that of the first clock signal CLK 1 or the second clock signal CLK 2 .

During the period of T 7 , the control signal SH 1 is logic high and the boost control signal CTRL 2 is logic high, the second low side switch S 3 and the third switch M 3 are turned ON, the fourth switch M 4 is turned OFF, the first auto-zero amplifier OP 3 at the outputting mode is configured to detect the current I 2 flowing through the second low side switch S 3 and to generate the detection current ISEN that represents the current I 2 . During the period of T 7 , the transistor Q 2 is turned ON, the detection voltage signal on the resistor R 1 starts to charge the capacitor C 1 to sample the value of the detection current ISEN. Upon the end of the period T 7 , i.e. at the midpoint of the turn ON time of the second low side switch S 3 , the transistor Q 2 is turned OFF and the average of the detection current ISEN is held as the charge stored in the capacitor C 1 . During the period of T 8 , the second auto-zero amplifier OP 4 at the outputting mode is configured to generate the detection current ICS in accordance with the charge stored in the capacitor C 1 .

In the example of FIG. 7 , the buck-boost converter 300 works in a boost mode, the input current IIN and the current sensing signal ICS satisfy an equation that: IIN=ICS, the output current IOUT and the current sensing signal ICS satisfy an equation that: IOUT=ICS(1−D 2 ), wherein the D 2 is the duty cycle of the boost control signal CTRL 2 .

FIG. 8 shows a waveform diagram of signals of the buck-boost converter 300 in FIG. 5 working in a buck-boost mode in accordance with an embodiment of the present invention.

FIG. 8 shows the switch signal at the first switch node SW 1 (plot 191 ), the switch signal at the second switch node SW 2 (plot 192 ), the inductor current IL (plot 193 ), the buck control signal CTRL 1 for the pair of buck switches (plot 195 ), the gate signal SH 1 driving the transistor Q 2 (plot 196 ), and the voltage VC 1 on the capacitor C 1 (plot 197 ), the first clock signal CLK 1 for the first auto-zero amplifier OP 3 (plot 198 ) and the second clock signal CLK 2 for the second auto-zero amplifier OP 4 (plot 199 ).

Referring to FIGS. 5 and 8 , when the buck-boost converter 300 works in the buck-boost mode, when the first high side switch S 1 and the second low side switch S 3 are turned ON, the first low side switch S 2 and the second high side switch S 4 are turned OFF. When the first high side switch S 1 and the second low side switch S 3 are turned OFF, the first low side switch S 2 and the second high side switch S 4 are turned ON.

During the period of TA and TC, the first clock signal CLK 1 is logic high, the second clock signal CLK 2 is logic low, the first auto-zero amplifier OP 3 is at the outputting mode, the second auto-aero amplifier OP 4 is at the zeroing mode. During the period of TB, the first clock signal CLK 1 is logic low, the second clock signal is logic high, the first auto-zero amplifier OP 3 is at the zeroing mode, the second auto-zero amplifier OP 4 is at the outputting mode. In the embodiment of the FIG. 8 , the first clock signal CLK 1 and the second clock signal CLK 2 are complementary and have the duty cycle of 0.5.

During the period of T 8 , the control signal SH 1 is logic high and the buck control signal CTRL 1 is logic low, the first low side switch S 2 and the first switch M 1 is turned ON, the second switch M 2 is turned OFF, the first auto-zero amplifier at the outputting mode is configured to detect the current I 1 flowing through the first low side switch S 2 and generate the detection current ISEN that represents the current I 1 . During the period of T 8 , the transistor Q 2 is turned ON, the detection current ISEN flows the resistor R 1 to generate a detection voltage signal that charges the capacitor C 1 to sample the value of the detection current ISEN. Upon completion of period of T 8 , i.e. at the midpoint of the turn ON time of the first low side switch S 2 , the transistor Q 2 is turned OFF, the average of the detection current ISEN is held as the charge stored in the capacitor C 1 . During the period of TB, the second auto-zero amplifier OP 4 at the outputting mode is configured to generate the current sensing signal ICS that represents the output current in accordance with the charge on the capacitor C 1 .

During the period of T 9 , the control signal SH 1 is logic high and the boost control signal CTRL 2 is logic high, the second low side switch S 3 and the third switch M 3 is turned ON, the fourth switch M 4 is turned OFF, the first auto-zero amplifier OP 3 at the outputting mode is configured to detect the current I 2 flowing through the second low side switch S 3 to generate the detection current ISEN that represents the current I 2 . During the period of T 9 , the transistor Q 2 is turned ON, the detection current ISEN flows through the resistor R 1 to generate a detection voltage signal that charges the capacitor C 1 to sample the value of the detection current ISEN. Upon completion of the period of T 9 , i.e. at the midpoint of the turn ON time of the second low side switch S 3 , the transistor Q 2 is turned OFF, the average of the detection current ISEN is held as the charge stored in the capacitor C 1 . In the next cycle after the period of TC, the second auto-zero amplifier OP 4 at the outputting mode is configured to generate the current sensing signal ICS that presents the input current in accordance with the charge stored on the capacitor C 1 .

Even though the periods TA, TB and TC are continuous and ordered in the embodiment of FIG. 8 , however, in another embodiment, for example in the buck-boost mode, a current sensing circuit used for a buck-boost converter 300 may be configured to detect the average of the current I 1 every fourth switching cycle during the first M 1 switching cycles (M 1 and generate the current sensing signal ICS that represents the output current IOUT. At the same time, the current sensing circuit may be configured to detect the average of the current I 2 every fifth switching cycle during the sequential M 2 switching cycles (M 25 ) following the first M 1 switching cycles and to generate the current sensing signal ICS that represents the input current IIN. In one embodiment, the sequence of the first M 1 switching cycles for sensing the current I 1 and the M 2 switching cycles for sensing the current I 2 can be changed. In a further embodiment, the current sensing circuit can average all the current sensing signal ICS during the first M 1 switching cycles or during the subsequent M 2 switching cycles, to improve at least one of accuracy and precision.

Obviously many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. It should be understood, of course, the foregoing disclosure relates only to a preferred embodiment (or embodiments) of the invention and that numerous modifications may be made therein without departing from the spirit and the scope of the invention as set forth in the appended claims. Various modifications are contemplated and they obviously will be resorted to by those skilled in the art without departing from the spirit and the scope of the invention as hereinafter defined by the appended claims as only a preferred embodiment(s) thereof has been disclosed.