Clamp logic circuit

This application claims the benefit of U.S. Provisional Application No. 62/549,968, filed on Aug. 25, 2017, the contents of which are incorporated herein in their entirety.

The present invention relates generally to a clamp logic circuit, and more specifically pertains to a clamp logic circuit for high frequency radio frequency (RF) applications.

As the semiconductor process progresses, the electronic components (e.g., transistors) become smaller, causing the signals of the electronic components easily affected by external radio frequency (RF) signals. Please refer to FIG. 1A . FIG. 1A is a functional block diagram of a logic circuit 100 according to the prior art. An input signal S 1 is inputted to the logic circuit 100 via an input terminal A. A parasitic capacitor Cp 1 exists between the logic circuit 100 and an external RF device (e.g., an RF chip), and an external alternating current (AC) signal Sr (e.g., an RF signal) from the external RF device may be transmitted to the input terminal A via the parasitic capacitor Cp 1 . As a result, the logic circuit 100 may operate abnormally due to the interference of the external AC signal Sr. For example, transition of a logic level of an output terminal B (e.g., from a high level to a low level or from the low level to the high level) of the logic circuit 100 may be abnormal. Moreover, the logic circuit 100 may consume a lot of power due to the electronic characteristics of the logic circuit 100 . Please refer to FIG. 1B . FIG. 1B is a relationship diagram of a current I flowing from the input terminal A into the logic circuit 100 versus a voltage level of the input signal S 1 . When the voltage level of the input signal S 1 is greater than 1 volt, the current that flows from the input terminal A into the logic circuit 100 increases as the potential of the input signal S 1 increases, causing the logic circuit 100 to consume excessive electric power.

In an embodiment of the present invention, a clamp logic circuit is provided. The clamp logic circuit comprises a logic circuit, a control terminal, a current clamp circuit and an output terminal. The logic circuit comprises at least a junction field-effect transistor (JFET). The control terminal is configured to receive an input signal. The current clamp circuit comprises a transistor and a resistor. A first end of the transistor is coupled to the control terminal, a second end of the transistor is coupled to a first end of the resistor, a control end of the transistor is coupled to a reference voltage, and a second end of the resistor is coupled to an input end of the logic circuit. The output terminal is coupled to an output end of the logic circuit.

FIG. 1A is a functional block diagram of a logic circuit according to the prior art.

FIG. 1B is a relationship diagram of a current flowing from the input terminal into the logic circuit shown in FIG. 1A versus a voltage level of an input signal.

FIG. 2A is a functional block diagram of a clamp logic circuit according to an embodiment of the present invention.

FIG. 2B is a relationship diagram of a current flowing from the control terminal into the current clamp circuit of the clamp logic circuit shown in FIG. 2A versus a voltage level of an input signal.

FIG. 3 is a circuit diagram of a clamp logic circuit according to another embodiment of the present invention.

FIG. 4 is a circuit diagram of a clamp logic circuit according to another embodiment of the present invention.

FIG. 5A to FIG. 5C are circuit diagrams of high impedance networks of the current clamp circuit of the clamp logic circuit according to different embodiments of the present invention.

FIG. 6A to FIG. 6C are circuit diagrams of the clamp logic circuit according to different embodiments of the present invention.

FIG. 7A is a relationship diagram of a current flowing from the control terminal into the current clamp circuit of the clamp logic circuit shown in FIG. 6B versus a voltage level of the input signal.

FIG. 7B is a relationship diagram of a current flowing from the control terminal into the current clamp circuit of the clamp logic circuit shown in FIG. 6C versus a voltage level of the input signal.

FIG. 8 is circuit diagram of the clamp logic circuit according to another embodiment of the present invention.

FIG. 9A to FIG. 9C are circuit diagrams of the low pass filter of the clamp logic circuit according to different embodiments of the present invention.

FIG. 10A to FIG. 10C are circuit diagrams of the clamp logic circuit according to different embodiments of the present invention.

Below, exemplary embodiments will be described in detail with reference to accompanying drawings so as to be easily realized by a person having ordinary knowledge in the art. The inventive concept may be embodied in various forms without being limited to the exemplary embodiments set forth herein. Descriptions of well-known parts are omitted for clarity, and like reference numerals refer to like elements throughout.

Please refer to FIG. 2A . FIG. 2A is a functional block diagram of a clamp logic circuit 200 according to an embodiment of the present invention. The clamp logic circuit 200 comprises an input terminal A, a current clamp circuit 210 , a logic circuit 220 and an output terminal B. The input terminal A is used as a control terminal of the clamp logic circuit 200 and is configured to receive an input signal S 1 . The input signal S 1 may be a direct-current (DC) voltage signal or a digital signal. An input end E of the logic circuit 220 is coupled to the current clamp circuit 210 , and an output end F of the logic circuit 220 is coupled to the output terminal B of the clamp logic circuit 200 . In addition, a parasitic capacitor Cp 1 exists between the clamp logic circuit 200 and an external RF device, and an external AC signal Sr from the external RF device is transmitted to the control terminal A via the parasitic capacitor Cp 1 . In the case of direct current (DC) analysis, the current clamp circuit 210 is used to clamp a current I flowing from the control terminal A into the current clamp circuit 210 . Due to the current clamp circuit 210 , a maximum current flowing from the control terminal A into the clamp logic circuit 200 is limited. Please refer to FIG. 2B . FIG. 2B is a relationship diagram of a current I flowing from the control terminal A into the current clamp circuit of the clamp logic circuit 200 versus a voltage level of the input signal S 1 . As shown in FIG. 2B , the maximum current flowing from the control terminal A into the clamp logic circuit 200 does not exceed a maximum current value, for example, 20 micro-ampere (μA). Accordingly, power consumption of the clamp logic circuit 200 is smaller than that of the logic circuit 100 .

Please refer to FIG. 3 . FIG. 3 is a circuit diagram of a clamp logic circuit 300 according to another embodiment of the present invention. The clamp logic circuit 300 comprises a logic circuit 320 , a control terminal A, a current clamp circuit 310 and an output terminal B. An input end E of the logic circuit 320 is coupled to the current clamp circuit 310 , and an output end F of the logic circuit 320 is coupled to the output terminal B of the clamp logic circuit 300 . The logic circuit 320 may be an inverter and may comprise at least a junction field-effect transistor (JFET). In the embodiment, the logic circuit 320 comprises a resistor Ra and a plurality of JFETs Ta and Tb. A first end of the JFET Ta may be coupled to a reference voltage VDD, a second end of the JFET Ta may be coupled to a first end of the resistor Ra, and a control end of the JFET Ta may be coupled to a second end of the resistor Ra and the output end F of the logic circuit 320 . A first end of the JFET Tb may be coupled to the second end of the resistor Ra and the output end F of the logic circuit 320 , a second end of the JFET Tb may be coupled to a reference voltage Vr, and a control end of the JFET Tb may be coupled to the input end E of the logic circuit 320 . The reference voltage VDD may be a variable voltage, and the reference voltage Vr may be a constant voltage. For example, the reference voltage VDD may be a supply voltage, and the reference voltage Vr may be a ground voltage. In an embodiment of the present invention, the JFETs Ta and Tb may be pseudomorphic high-electron-mobility transistors (pHEMTs). In another embodiment of the present invention, the JFET Ta may be a depletion-mode (D-mode) field-effect transistor (FET), and the JFET Tb may be an enhancement-mode (E-mode) field-effect transistor (FET).

The current clamp circuit 310 is also used to clamp the current I flowing from the control terminal A into the current clamp circuit 310 . The current clamp circuit 310 comprises a transistor T 1 and a resistor R 1 . A first end N 1 of the transistor T 1 is coupled to the control terminal A, a second end N 2 of the transistor T 1 is coupled to a first end of the resistor R 1 , a control end Nc of the transistor T 1 is coupled to the reference voltage Vr, and a second end of the resistor R 1 is coupled to the input end E of the logic circuit 320 . The transistor T 1 may be a D-mode FET and has a negative threshold voltage (i.e., a threshold voltage less than 0 volts (e.g., −1 volts)). In the case of high frequency analysis, when the signal strength of the external AC signal Sr is greater than the threshold voltage of the transistor T 1 , the external AC signal Sr will be transmitted from the first end N 1 to the second end N 2 , and the external AC signal Sr will not be distorted. However, when the signal strength of the external AC signal Sr is less than the threshold voltage of the transistor T 1 , the external AC signal Sr Will be intercepted, causing distortion of the external AC signal Sr. In another embodiment, the transistor T 1 may be an E-mode FET.

Please refer to FIG. 4 . FIG. 4 is a circuit diagram of a clamp logic circuit 400 according to another embodiment of the present invention. In the embodiment, the clamp logic circuit 400 is similar to the clamp logic circuit 300 . The main difference between the clamp logic circuits 300 and 400 is that a current clamp circuit 410 of the clamp logic circuit 400 comprises not only the transistor T 1 and the resistor R 1 but also a high impedance network 420 . The high impedance network 420 is coupled between the control end Nc of the transistor T 1 and the reference voltage Vr. The high impedance network 420 provides high impedance between the control end Nc and the reference voltage Vr so as to increase the linearity of the transistor T 1 . For example, the high impedance network 420 may have a resistance of 50K ohms. Moreover, as shown in FIG. 4 , a parasitic capacitor Cpa may exist between the first end N 1 and the control end Nc, and another parasitic capacitor Cpb may exist between the second end N 2 and the control end Nc. An AC signal transmission path between the first end N 1 and the second end N 2 is formed due to the parasitic capacitors Cpa and Cpb. Therefore, distortion of the external AC signal Sr caused by the transistor T 1 would be reduced and integrity of the external AC signal Sr would be maintained.

As shown in FIG. 4 , the high impedance network 420 of the clamp logic circuit 400 has two ends a and b. More specifically, the end a of the high impedance network 420 is coupled to the control end Nc of the transistor T 1 , and the end b of the high impedance network 420 is coupled to the reference voltage Vr. In an embodiment of the present invention, the high impedance network 420 may be implemented by a high impedance network 420 A illustrated in FIG. 5A , which comprises a resistor R. In another embodiment of the present invention, the high impedance network 420 may be implemented by a high impedance network 420 B illustrated in FIG. 5B , which comprises a transistor Q. In another embodiment of the present invention, the high impedance network 420 may be implemented by a high impedance network 420 C illustrated in FIG. 5C , which comprises an inductor L.

Please refer to FIG. 6A . FIG. 6A is a circuit diagram of a clamp logic circuit 800 according to another embodiment of the present invention. In the embodiment, the clamp logic circuit 800 is similar to the clamp logic circuit 400 shown in FIG. 4 . The main difference between the clamp logic circuits 400 and 800 is that the clamp logic circuit 800 further comprises a DC offset circuit 610 and a capacitor C. The DC offset circuit 610 is coupled between the control terminal A and the first end N 1 of the transistor T 1 . The DC offset circuit 610 is configured to adjust the DC voltage level of the DC input signal S 1 (e.g., adjust the DC voltage level of the DC input signal S 1 according to the threshold value of the logic circuit 320 ). The DC offset circuit 610 comprises a rectifying device 620 . A first end of the rectifying device 620 is coupled to the control terminal A, and a second end of the rectifying device 620 is coupled to the first end N 1 of the transistor T 1 . In addition, a first end of the capacitor C is coupled between the input end E of the logic circuit 320 and the second end of the resistor R 1 , and a second end of the capacitor C is coupled to the reference voltage Vr. The resistor R 1 and the capacitor C form a low pass filter that allows the input signal S 1 to pass through and is configured to filter out the external AC signal Sr. In another embodiment of the present invention, the clamp logic circuit 800 may further comprise an inductor coupled between the second end of the resistor R 1 and the first end of the capacitor C. The resistor R 1 , the capacitor C and the inductor form a low pass filter that allows the input signal S 1 to pass through and is configured to filter out the external AC signal Sr. Due to the existence of the high impedance network 420 , distortion of the external AC signal Sr caused by the transistor T 1 would be reduced and integrity of the external AC signal Sr would be maintained, so that the external AC signal Sr could be substantially filtered out (e.g., the external AC signal Sr can be removed) by the low pass filter. As a result, effect of the external AC signal Sr on the DC voltage level of the input end E of the logic circuit 320 may be reduced, such that the transition of the logic level of the output end F of the logic circuit 320 would be normal. Accordingly, the transition of the logic level of the output terminal B of the clamp logic circuit 800 would be normal. In another embodiment, the DC offset circuit 610 may be omitted based on different design choices of the clamp logic circuit 800 .

Please refer to FIG. 6B . FIG. 6B is a circuit diagram of a clamp logic circuit 900 according to another embodiment of the present invention. In the embodiment, the clamp logic circuit 900 is similar to the clamp logic circuit 800 shown in FIG. 6A . The DC offset circuit 610 of the clamp logic circuit 800 is implemented by a DC offset circuit 610 A of the clamp logic circuit 900 . The DC offset circuit 610 A comprises a rectifying device 620 A coupled between the control terminal A and the first end N 1 of the transistor T 1 . The rectifying device 620 A of the DC offset circuit 610 A comprises a diode-connected transistor T 2 . A first end N 3 and a control end Nc 2 of the diode-connected transistor T 2 are coupled to each other and are coupled to the control terminal A, and a second end N 4 of the diode-connected transistor T 2 is coupled to the first end N 1 of the transistor T 1 . The diode-connected transistor T 2 may be an E-mode FET.

Please refer to FIG. 6C . FIG. 6C is a circuit diagram of a clamp logic circuit 1000 according to another embodiment of the present invention. In the embodiment, the clamp logic circuit 1000 is similar to the clamp logic circuit 800 shown in FIG. 6A . The DC offset circuit 610 of the clamp logic circuit 800 is implemented by a DC offset circuit 610 B of the clamp logic circuit 1000 . The DC offset circuit 610 B comprises a rectifying device 620 B coupled between the control terminal A and the first end N 1 of the transistor T 1 . The rectifying device 620 B of the DC offset circuit 610 B comprises a first diode D 1 . A first end (i.e., an anode) of the first diode D 1 is coupled to the control terminal A, and a second end (i.e., a cathode) of the first diode D 1 is coupled to the first end N 1 of the transistor T 1 .

Please refer to FIG. 2B and FIGS. 7A to 7B . FIG. 7A is a relationship diagram of a current I flowing from the control terminal A into the current clamp circuit 410 of the clamp logic circuit 900 shown in FIG. 6B versus a voltage level of the input signal S 1 . FIG. 7 B is a relationship diagram of a current I flowing from the control terminal A into the current clamp circuit 410 of the clamp logic circuit 1000 shown in FIG. 6C versus a voltage level of the input signal S 1 . As shown in FIG. 2B , the current I flowing from the control terminal A into the current clamp circuit 210 of the clamp logic circuit 200 , for example, may be greater than 0 μA as long as the voltage level of the input signal S 1 is greater than 0V. As shown in FIG. 7A , due to the DC offset circuit 610 A, the current flowing from the control terminal A into the current clamp circuit 410 of the clamp logic circuit 900 , for example, may be greater than 0 μA as long as the voltage level of the input signal S 1 is greater than 0.3V. As shown in FIG. 7B , due to the DC offset circuit 610 B, the current flowing from the control terminal A into the current clamp circuit 410 of the clamp logic circuit 1000 , for example, may be greater than 0 μA as long as the voltage level of the input signal S 1 is greater than 0.5V.

Please refer to FIG. 8 . FIG. 8 is a circuit diagram of a clamp logic circuit 1300 according to another embodiment of the present invention. In the embodiment, the clamp logic circuit 1300 is similar to the clamp logic circuit 800 shown in FIG. 6A . The main difference between the clamp logic circuits 800 and 1300 is that the clamp logic circuit 1300 further comprises the low pass filter 530 . The low pass filter 530 is coupled between the control terminal A and the DC offset circuit 610 . More specifically, a first end B 1 of the low pass filter 530 is coupled to the control terminal A, and a second end B 2 of the low pass filter 530 is coupled to the DC offset circuit 610 . The low pass filter 530 is used to adjust the amplitude of the external AC signal Sr. To reduce the effect of the external AC signal Sr having a greater amplitude, the low pass filter 530 can be added in to provide an auxiliary filtering function to filter out the external AC signal Sr, so as to reduce the amplitude of the external AC signal Sr.

In an embodiment of the present invention, the low pass filter 530 shown in FIG. 8 may be implemented by a low pass filter 530 A illustrated in FIG. 9A , which comprises a resistor R 2 and a capacitor Ca. A first end of the resistor R 2 is coupled to the first end B 1 of the low pass filter 530 A, a second end of the resistor R 2 is coupled to the second end B 2 of the low pass filter 530 A and a first end of the capacitor Ca, and a second end of the capacitor Ca is coupled to the reference voltage Vr. In another embodiment of the present invention, the low pass filter 530 shown in FIG. 8 may be implemented by a low pass filter 530 B illustrated in FIG. 9B , which comprises the resistor R 2 , an inductor L 1 and the capacitor Ca. The first end of the resistor R 2 is coupled to the first end B 1 of the low pass filter 530 B, the second end of the resistor R 2 is coupled to a first end of the inductor L 1 , a second end of the inductor L 1 is coupled to the second end B 2 of the low pass filter 530 B and the first end of the capacitor Ca, and the second end of the capacitor Ca is coupled to the reference voltage Vr. In another embodiment of the present invention, the low pass filter 530 shown in FIG. 8 may be implemented by a low pass filter 530 C illustrated in FIG. 9C , which comprises the capacitor Ca. The first end of the capacitor Ca is coupled to the first end B 1 and the second end B 2 of the low pass filter 530 C, and the second end of the capacitor Ca is coupled to the reference voltage Vr.

Please refer to FIG. 10A . FIG. 10A is a circuit diagram of a clamp logic circuit 1400 according to another embodiment of the present invention. In the embodiment, the clamp logic circuit 1400 is similar to the clamp logic circuit 900 shown in FIG. 6B . The main difference between the clamp logic circuits 900 and 1400 is that the clamp logic circuit 1400 further comprises at least one of high pass filters 710 , 720 and 730 . In other words, the clamp logic circuit 1400 may further comprise one, two or all of the high pass filters 710 , 720 and 730 based on different design choices of the clamp logic circuit 1400 . The high pass filter 710 is coupled between the first end N 1 and the second end N 2 of the transistor T 1 , the high pass filter 720 is coupled between the first end N 3 and the second end N 4 of the diode-connected transistor T 2 , and the high pass filter 730 is coupled between the control end Nc of the transistor T 1 and the control end Nc 2 of the diode-connected transistor T 2 . In the embodiment, for the external AC signal Sr, the high pass filter 710 provides a low impedance path from the first end N 1 of the transistor T 1 through the high pass filter 710 to the second end N 2 of the transistor T 1 , the high pass filter 720 provides a low impedance path from the first end N 3 of the diode-connected transistor T 2 through the high pass filter 720 to the second end N 4 of the diode-connected transistor T 2 , and the high pass filter 730 provides a low impedance path from the first end N 3 of the diode-connected transistor T 2 through the high pass filter 730 to the control end Nc of the transistor T 1 . Since each of the high pass filters 710 , 720 and 730 may provide a low impedance path for the external AC signal Sr, effect of the non-linearity of the transistors T 1 and the diode-connected transistor T 2 on the external AC signal Sr would be reduced. Accordingly, distortion of the external AC signal Sr would be decreased, and integrity of the external AC signal Sr would be maintained. More specifically, the external AC signal Sr could be substantially filtered out (e.g., the external AC signal Sr can be removed) by the low pass filter. As a result, effect of the external AC signal Sr on the DC voltage level of the input end E of the logic circuit 320 may be reduced, such that the transition of the logic level of the output terminal B would be normal. In addition, each of the high pass filters 710 , 720 and 730 may also provide a bi-directional conducting path (e.g. a voltage path of positive half period of the external AC signal Sr and a voltage path of negative half period of the external AC signal Sr), which is helpful to reduce distortion of the external AC signal Sr. The high pass filter 710 may be a capacitor C 1 , the high pass filter 720 may be a capacitor C 2 , or the high pass filter 730 may be a capacitor C 3 .

Please refer to FIG. 10B . FIG. 10B is a circuit diagram of a clamp logic circuit 1500 according to another embodiment of the present invention. In the embodiment, the clamp logic circuit 1500 is similar to the clamp logic circuit 900 shown in FIG. 6B . The main difference between the clamp logic circuits 900 and 1500 is that the clamp logic circuit 1500 further comprises at least one of high pass filters 730 and 740 . In other words, the clamp logic circuit 1500 may further comprise one or all of the high pass filters 730 and 740 based on different design choices of the clamp logic circuit 1500 . The high pass filter 730 is coupled between the control end Nc of the transistor T 1 and the control end Nc 2 of the diode-connected transistor T 2 , and the high pass filter 740 is coupled between the control terminal A and the second end N 2 of the transistor T 1 . In the embodiment, for the external AC signal Sr, the high pass filter 730 provides a low impedance path from the first end N 3 of the diode-connected transistor T 2 through the high pass filter 730 to the control end Nc of the transistor T 1 , and the high pass filter 740 provides a low impedance path from the first end N 3 of the diode-connected transistor T 2 through the high pass filter 740 to the second end N 2 of the transistor T 1 . Therefore, effect of the non-linearity of the transistors T 1 and the diode-connected transistor T 2 on the external AC signal Sr would be reduced. Accordingly, distortion of the external AC signal Sr would be decreased, and integrity of the external AC signal Sr would be maintained. Each of the high pass filters 730 and 740 may also provide a bi-directional conducting path, which is helpful to reduce distortion of the external AC signal Sr. The high pass filter 730 may be a capacitor C 3 or the high pass filter 740 may be a capacitor C 4 .

Please refer to FIG. 10C . FIG. 10C is a circuit diagram of a clamp logic circuit 1600 according to another embodiment of the present invention. In the embodiment, the clamp logic circuit 1600 is similar to the clamp logic circuit 1000 shown in FIG. 6C . The main difference between the clamp logic circuits 1000 and 1600 is that the clamp logic circuit 1600 further comprises another rectifying device 720 B and a high pass filter 730 . A first end of the rectifying device 720 B is coupled to the second end of the rectifying device 620 B, and a second end of the rectifying device 720 B is coupled to the first end of the rectifying device 620 B. The rectifying device 720 B comprises a second diode D 2 . A first end (i.e., an anode) of the second diode D 2 is coupled to the second end (i.e., a cathode) of first diode D 1 , and a second end (i.e., a cathode) of the second diode D 2 is coupled to the first end (i.e., an anode) of first diode D 1 . The two rectifying devices 620 B and 720 B provide a bi-directional conducting path (e.g. a voltage path of positive half period of the external AC signal Sr and a voltage path of negative half period of the external AC signal Sr) between the control terminal A and the first end N 1 of the transistor T 1 , and the two rectifying devices 620 B and 720 B are helpful to reduce distortion of the external AC signal Sr. The high pass filter 730 is coupled between the control end Nc of the transistor T 1 and the second end (i.e., the cathode) of the diode D 1 to provide a low impedance path from the second end (i.e., the cathode) of the first diode D 1 and the first end (i.e., the anode) of the second diode D 2 through the high pass filter 730 to the control end Nc of the transistor T 1 . Therefore, effect of the non-linearity of the transistor T 1 on the external AC signal Sr would be reduced. As a result, distortion of the external AC signal Sr would be decreased, and integrity of the external AC signal Sr would be maintained. The high pass filter 730 may be a capacitor C 3 . In another embodiment, the rectifying device 720 B may comprise a diode-connected transistor. In yet another embodiment, the high pass filter 730 may be omitted based on different design choices of the clamp logic circuit 1600 .

In some embodiments of the present invention, all of the transistors (e.g., T 1 , T 2 , Ta and Tb) of the clamp logic circuit may be gallium arsenide (GaAs) transistors or gallium nitride (GaN) transistors.

The clamp logic circuits according to the embodiments of the present invention use the current clamp circuits to limit a maximum current flowing from the control terminal into the current clamp circuit of the clamp logic circuit to reduce the power consumption. The current clamp circuits of the clamp logic circuits may comprise a high impedance network to provide high impedance between the control end of the transistor and the reference voltage so as to increased linearity of the transistor of the current clamp circuits. Accordingly, distortion of the external AC signal would be reduced, and integrity of the external AC signal would be maintained. In addition, by using the capacitor and the resistor of the current clamp circuits, a low pass filter could be formed to filter out the external AC signal. As a result, effect of the external AC signal on the DC voltage level of the input end of the logic circuit may be reduced, such that the transition of the logic level of the output terminal of the clamp logic circuit (i.e., the transition of the logic level of the output end of the clamp logic circuit) would be normal.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.