Signal-multiplexing device

This application is a National Stage of International Application No. PCT/JP2017/008940 filed Mar. 7, 2017, claiming priority based on Japanese Patent Application No. 2016-070796 filed Mar. 31, 2016.

The present invention relates to a signal-multiplexing device.

Non-Patent Document 1 describes a signal-multiplexing device that multiplexes four input signals so as to generate a single output signal. This signal-multiplexing device includes four buffers that are connected in parallel. Each of the buffers includes a flip-flop and two transfer gates that are connected in series in order. Each of the transfer gates is adjusted so as to enter into the ON state at a prescribed timing. By doing this, input signals that have been inputted to the respective buffers are sequentially output as a single output signal from the signal-multiplexing device.

The signal-multiplexing device described in Non-Patent Document 1 is capable of widening an allowable range of a delay time of the flip-flop and handling, an increase in a date rate in comparison with a case where two input signals are multiplexed such that a single output signal is generated.

Non-Patent Literature

Non-Patent Document 1: Jihwan Kim et al., “A 16-to-40 Gb/s Quarter-Rate NRZ/PAM4 Dual-Model Transmitter in 14 nm CMOS”, 2015 IEEE International Solid-State Circuits Conference (ISSCC), (US), February 2015

Technical Problem

Inventors studied a conventional signal-multiplexing device so as to discover the problem below. That is, in the signal-multiplexing device described in Non-Patent Document 1 listed above, a parasitic resistance value and a parasitic capacitance value increase due to the serial connection of two transfer gates. Therefore, the waveform of an output signal is blunted, and a frequency band is limited. Accordingly, there is a problem that the signal-multiplexing device described in Non-Patent Document 1 listed above fails to satisfactorily handle an increase in a data rate.

An object of the present invention is to provide a signal-multiplexing device having a structure that is capable of satisfactorily handling an increase in a data rate.

Solution to Problem

In order to solve the problem above, a signal-multiplexing device according to the present embodiment outputs an input signal I m of M input signals I 1 to I M (M is an integer of 3 or more) during a prescribed period. The input signal I m is sequentially specified by a combination of the signal levels of at least an m-th control signal C m (in is an integer that is greater than or equal to 1 and is smaller than or equal to M) and an n-th control signal C n (n is 1 when m=M, and n is an integer of m+1 when m<M) that are selected from M control signals C 1 to C M . The prescribed period is a period during which the combination of the signal levels is maintained. Specifically, the signal-multiplexing device includes M pre-stage buffers B 1 to B M that are provided so as to respectively correspond to the input signals I 1 to I M , and an output buffer B out that is electrically connected to an output end of each of the pre-stage buffers B 1 to B M . An m-th pre-stage buffer B m of the pre-stage buffers B 1 to B M includes an input end that captures the input signal I m , an input end that captures the control signal C m , an input end that captures the control signal C n , and an output end that outputs the input signal I m . The pre-stage buffer B m outputs the input signal I m that has been inputted to the pre-stage buffer B m , when the signal levels of both the control signal C m and the control signal C n are significant. On the other hand, the pre-stage buffer B m enters into a high-impedance output state, when the signal level of at least one of the control signal C m and the control signal C n is non-significant. The output buffer B out sequentially outputs the input signals I 1 to I M that have been respectively outputted from the pre-stage buffers B 1 to B M at different timings.

Advantageous Effects of Invention

The signal-multiplexing device according to the present embodiment is capable of satisfactorily handling an increase in a data rate.

FIG. 1 illustrates a configuration of a signal-multiplexing device 1 according to the present embodiment.

FIG. 2 is a table that collectively illustrates relationships among the respective levels of control signals C 1 to C M , the respective output signals of pre-stage buffers B 1 to B m , and the output signal of an output buffer B out in the signal-multiplexing device 1 according to the present embodiment.

FIG. 3 is a timing chart illustrating each of the control signals C to C M , input signals I 1 to I M , and the output signal of the output buffer B out .

FIG. 4 illustrates an exemplary configuration of a generator 2 that generates M (=3) control signals.

FIG. 5 illustrates an exemplary configuration of a generator 2 that generates M (=5) control signals.

FIG. 6 illustrates an exemplary configuration of a generator 2 that generates M (=6) control signals.

FIG. 7 illustrates a first exemplary configuration of a pre-stage buffer B m .

FIG. 8 illustrates an exemplary configuration of a tri-state buffer 4 in the pre-stage buffer B m having the first exemplary configuration.

FIG. 9 illustrates a second exemplary configuration of the pre-stage buffer B m .

FIG. 10 illustrates a third exemplary configuration of the pre-stage buffer B m .

FIG. 11 illustrates a fourth exemplary configuration of the pre-stage buffer B m .

First, the contents of an embodiment of the present invention are individually described.

(1) A signal-multiplexing device according to the present embodiment outputs an input signal I m of M input signals I 1 to I M (M is an integer of 3 or more) during a prescribed period. The input signal I m is sequentially specified by a combination of the signal levels of at least an m-th control signal C m (m is an integer that is greater than or equal to 1 and is smaller than or equal to M) and an n-th control signal C n (n is 1 when m=M, and n is an integer of m+1 when m<M) that are selected from M control signals C 1 to C M . The prescribed period is a period during which the combination of the signal levels is maintained. In one aspect, the signal-multiplexing device includes M pre-stage buffers B 1 to B M that are provided so as to respectively correspond to the input signals I 1 to I M , and an output buffer B out that is electrically connected to an output end of each of the pre-stage buffers B 1 to B M . An m-th pre-stage buffer B m of the pre-stage buffers B 1 to B M includes an input end that captures the input signal I m , an input end that captures the control signal C m an input end that captures the control signal C n , and an output end that outputs the input signal I m . The pre-stage buffer B m outputs the input signal I m that has been inputted to the pre-stage buffer B m , when the signal levels of both the control signal C m and the control signal C n are significant. On the other hand, the pre-stage buffer B m enters into a high-impedance output state, when the signal level of at least one of the control signal C m and the control signal C n is non-significant. The output buffer B out sequentially outputs the input signals I 1 to I M that have been respectively outputted from the pre-stage buffers B 1 to B M at different timings.

(2) In one aspect of the present embodiment, various configurations can be applied to the pre-stage buffer B m . Specifically, a first exemplary configuration of the pre-stage buffer B m includes a tri-state buffer and a switch. The tri-state buffer is a circuit for which an output signal level is set to each of the output states “High”, “Low”, and “High-impedance”. Specifically, when the signal level of the control signal C m is significant, the tri-state buffer outputs a temporarily captured input signal (for example, a binary signal that is configured by two states, “High” and “Low”) I m . When the signal level of the control signal C m is non-significant, the tri-state buffer enters into the high-impedance output state (a state in which the tri-state buffer and the switch are substantially disconnected). The switch includes a first end that is electrically connected to an output end of the tri-state buffer, and a second end that is electrically connected to an input end of the output buffer B out . In this configuration, the switch changes a state of electrical connection between the first end and the second end in accordance with the signal level of the control signal C n . Specifically, when the signal level of the control signal C n is significant, the switch electrically connects the first end and the second end (the ON state). When the signal level of the control signal C n is non-significant, the switch electrically disconnects the first end and the second end (the OFF state).

(3) In one aspect of the present embodiment, the tri-state buffer may include a first gate circuit, a second gate circuit, and a first-configuration series circuit that is disposed between a first reference end and a second reference end. The first reference end is set to have a first reference potential, and a second reference end is set to have a second reference potential that is lower than the first reference potential. The first-configuration series circuit is configured by a PMOS transistor and an NMOS transistor that are disposed in order from a side of the first reference end to a side of the second reference end, and a drain of the PMOS transistor and a drain of the NMOS transistor are connected to each other. The first gate circuit outputs a signal indicating a negative AND (NAND) of the input signal I m and the control signal C m . The second gate circuit outputs a signal indicating a negative OR (NOR) of the input signal I m and a logic inversion signal of the control signal C m . The PMOS transistor includes a source that is electrically connected to the first reference end, a gate that is connected to an output end of the first gate circuit, and the drain that is electrically connected to the drain of the NMOS transistor. The NMOS transistor includes the drain that is electrically connected to the drain of the PMOS transistor, a gate that is electrically connected to an output end of the second gate circuit, and a source that is electrically connected to the second reference end. Further, a connection point of the drain of the PMOS transistor and the drain of the NMOS transistor is electrically connected to the switch.

(4) In one aspect of the present embodiment, a second exemplary configuration of the pre-stage buffer B m may include a first gate circuit, a second gate circuit, and a second-configuration series circuit that is disposed between the first reference end and the second reference end. The second-configuration series circuit is configured by a first buffer switch, a PMOS transistor, an NMOS transistor, and a second buffer switch that are disposed in order from a side of the first reference end to a side of the second reference end. The first gate circuit outputs a signal indicating an NAND of the input signal I m and the control signal C m . The second gate circuit outputs a signal indicating an NOR of the input signal I m and a logic inversion signal of the control signal C m . The first buffer switch includes a first end that is electrically connected to the first reference end, and a second end that is electrically connected to a source of the PMOS transistor. In addition, the first buffer switch changes a state of electrical connection between the first end and the second end of the first buffer switch in accordance with the signal level of the control signal C n . Stated another way, when the signal level of the control signal C n is significant, the first buffer switch electrically connects the first end and the second end (the ON state). When the signal level of the control signal C n is non-significant, the first buffer switch electrically disconnects the first end and the second end (the OFF state). The PMOS transistor includes a source that is electrically connected to the second end of the first buffer switch, a gate that is connected to an output end of the first gate circuit, and a drain that is electrically connected to a drain of the NMOS transistor. The NMOS transistor includes the drain that is connected to the drain of the PMOS transistor, a gate that is electrically connected to an output end of the second gate circuit, and a source that is electrically connected to a first end of the second buffer switch. The second buffer switch includes a first end that is electrically connected to the source of the NMOS transistor, and a second end that is electrically connected to the second reference end. In addition, the second buffer switch changes a state of electrical connection between the first end and the second end of the second buffer switch in accordance with the signal level of the control signal C n . Stated another way, when the signal level of the control signal C n is significant, the second buffer switch electrically connects the first end and the second end (the ON state). When the signal level of the control signal C n is non-significant, the second buffer switch electrically disconnects the first end and the second end (the OFF state). Further, a connection point of the drain of the PMOS transistor and the drain of the NMOS transistor is connected to the input end of the output buffer B out .

(5) In one aspect of the present embodiment, a third exemplary configuration of the pre-stage buffer B m may include a first gate circuit, a second gate circuit, and a third-configuration series circuit that is disposed between the first reference end and the second reference end. The third-configuration series circuit is configured by a PMOS transistor, a first buffer switch, a second buffer switch, and an NMOS transistor that are disposed in order from a side of the first reference end to a side of the second reference end. The first gate circuit outputs a signal indicating an NAND of the input signal I m and the control signal C m . The second gate circuit outputs a signal indicating an NOR of the input signal I m and a logic inversion signal of the control signal C m . The PMOS transistor includes a source that is electrically connected to the first reference end, a gate that is electrically connected to an output end of the first gate circuit, and a drain that is electrically connected to a first end of the first buffer switch. The first buffer switch includes a first end that is electrically connected to the drain of the PMOS transistor, and a second end that is electrically connected to a first end of the second buffer switch. In addition, the first buffer switch changes a state of electrical connection between the first end and the second end of the first buffer switch in accordance with the signal level of the control signal C n . Specifically, when the signal level of the control signal C n is significant, the first buffer switch electrically connects the first end and the second end (the ON state). When the signal level of the control signal C n is non-significant, the first buffer switch electrically disconnects the first end and the second end (the OFF state). The second buffer switch includes a first end that is electrically connected to the second end of the first buffer switch, and a second end that is electrically connected to a drain of the NMOS transistor. In addition, the second buffer switch changes a state of electrical connection between the first end and the second end of the second buffer switch in accordance with the signal level of the control signal C n . Specifically, when the signal level of the control signal C n is significant, the second buffer switch electrically connects the first end and the second end (the ON state). When the signal level of the control signal C n is non-significant, the second buffer switch electrically disconnects the first end and the second end (the OFF state). The NMOS transistor includes the drain that is electrically connected to the second end of the second buffer switch, a gate that is electrically connected to an output end of the second gate circuit, and a source that is electrically connected to the second reference end. Further, a connection point of the second end of the first buffer switch and the first end of the second buffer switch is electrically connected to the input end of the output buffer B out .

(6) In one aspect of the present embodiment, the third exemplary configuration of the pre-stage buffer B m may further include a first refresh circuit that refreshes a potential at a connection point of the drain of the PMOS transistor and the first end of the first buffer switch, and a second refresh circuit that refreshes a potential at a connection point of the drain of the NMOS transistor and the second end of the second buffer switch. In this case, the first refresh circuit includes a first end that is electrically connected to a third reference end, and a second end that is electrically connected to the connection point of the drain of the PMOS transistor and the first end of the first buffer switch. The third reference end is set to have a third reference potential that is higher than the second reference potential. The second refresh circuit includes a first end that is electrically connected to the connection point of the drain of the NMOS transistor and the second end of the second buffer switch, and a second end that is electrically connected to a fourth reference end. The fourth reference end is set to have a fourth reference potential that is lower than the first reference potential.

(7) In one aspect of the present embodiment, a fourth exemplary configuration of the pre-stage buffer B m may include a first gate circuit, a second gate circuit, a three gate circuit, a fourth gate circuit, and a fourth-configuration series circuit that is disposed between the first reference end and the second reference end. The fourth-configuration series circuit is configured by a PMOS transistor and an NMOS transistor that are disposed in order from a side of the first reference end to a side of the second reference end, and a drain of the PMOS transistor and a drain of the NMOS transistor are connected to each other. The first gate circuit outputs a signal indicating an NOR of the input signal I m and a logic inversion signal of the control signal C m . The second gate circuit outputs a signal indicating an NAND of an output signal of the first gate circuit and the control signal C n . The third gate circuit outputs a signal indicating an NAND of the input signal I m and the control signal C m . The fourth gate circuit outputs a signal indicating an NOR of an output signal of the third gate circuit and a logic inversion signal of the control signal C n . The PMOS transistor includes a source that is electrically connected to the first reference end, a gate that is connected to an output end of the second gate circuit, and the drain that is electrically connected to the drain of the NMOS transistor. The NMOS transistor includes the drain that is electrically connected to the drain of the PMOS transistor, a gate that is electrically connected to an output end of the fourth gate circuit, and a source that is electrically connected to the second reference end.

(8) In one aspect of the present embodiment, the signal-multiplexing device that has various structures described above may further include a generator that generates each of the control signals C 1 to C M (a control signal generator). When M=6, namely, when the generator generates control signals C 1 to C 6 that correspond to the control signals C 1 to C M , it is preferable that the generator include first to fifth latch circuits and fifth to eighth gate circuits. In this configuration, the first latch circuit receives an output signal of the seventh gate circuit, latches a value of the output signal of the seventh gate circuit at one timing of a rising timing and a falling timing of a clock, and outputs the latched value. The fifth gate circuit outputs a logic inversion signal of an output signal of the first latch circuit as the control signal C 3 . The second latch circuit receives the control signal C 3 , latches a value of the control signal C 3 at the other timing of the rising timing or the falling timing of the clock, and outputs the latched value as the control signal C 4 . The third latch circuit receives the output signal of the first latch circuit, latches a value of the output signal of the first latch circuit at the one timing described above, and outputs the latched value. The sixth gate circuit outputs a logic inversion signal of an output signal of the third latch circuit as the control signal C 5 . The fourth latch circuit latches a value of the control signal C 5 outputted from the sixth gate circuit at the other timing described above, and outputs the latched value as the control signal C 6 . The seventh gate circuit outputs a signal indicating an NAND of the output signal of the first latch circuit and the output signal of the third latch. The eighth gate circuit outputs a logic inversion signal of an output signal of the seventh gate circuit as the control signal C 1 . The fifth latch circuit latches a value of the control signal C 1 outputted from the eighth gate circuit at the other timing described above, and outputs the latched value as the control signal C 2 .

Each of the aspects described in the Description of Embodiment of the Present Invention can be applied to each of the other aspects or a combination of the other aspects.

Specific structures of the signal-multiplexing device according to the present embodiment are described below in detail with reference to the appended drawings. The present invention is not limited to these illustrations. The present invention is described in the claims, and is intended to include equivalents of the claims and all changes without departing from the scope of the claims. In the description of the drawings, the same components are denoted by the same reference signs, and duplicate description is omitted.

FIG. 1 illustrates the configuration of a signal-multiplexing device 1 according to the present embodiment. The signal-multiplexing device 1 illustrated in FIG. 1 outputs a signal that corresponds to any input signal of M input signals I 1 to I M (M is an integer of 3 or more) (substantially, an input signal) in accordance with the level of each of M control signals C 1 to C M . Stated another way, the signal-multiplexing device 1 is a device that multiplexes the input signals I 1 to I M each having been captured from an input end 1 A and outputs an output signal (a multiplexed output signal) from a single output end 1 B. The signal-multiplexing device 1 includes M pre-stage buffers B 1 to B M , an output buffer B out , and a generator 2 that generates each of the control signals C 1 to C M . As an example of signal-multiplexing, an input signal I m of the input signals I 1 to I M is output during a prescribed period. The input signal I m is sequentially specified by a combination of the signal levels of at least an m-th control signal C m (m is an integer that is greater than or equal to 1 and is smaller than or equal to M) and an n-th control signal C n (n is 1 when m=M, and n is an integer of m+1 when m<M) that are selected from the control signals C 1 to C M . The prescribed period is a period during which the combination of the signal levels of the control signal C m and the control signal C n is maintained.

As described above, an m-th pre-stage buffer B m of the pre-stage buffers B 1 to B M receives an m-th input signal I m of the input signals I 1 to I M captured in the signal-multiplexing device 1 via input ends I 1 to I M , and the control signal C m and the control signal C n of the control signals C 1 to C M . The pre-stage buffer B m outputs a signal that corresponds to the input signal I m (substantially, the input signal I m ), when the signal levels of both the control signal C m and the control signal C n are significant. The pre-stage buffer B m enters into a high-impedance output state (a substantially disconnection state), when the signal level of at least one of the control signal C m and the control signal C n is non-significant.

The output buffer B out is connected to respective output ends of the pre-stage buffers B 1 to B M . Stated another way, the pre-stage buffers B 1 to B M are connected in parallel to each other. The output buffer B out receives respective signals outputted from the pre-stage buffers B 1 to B M , at different timings, and outputs a signal that corresponds to a received signal (substantially, the input signal I m specified by the combination of the signal levels of the control signal C m and the control signal C n ).

FIG. 2 is a table that collectively illustrates relationships among the respective signal levels of the control signals C 1 to C M , the respective output signals of the pre-stage buffers B 1 to B M , and the output signal of the output buffer B out in the signal-multiplexing device 1 according to the present embodiment. In the table of FIG. 2 , as the signal level of a control signal, a significant level (a High level) is indicated by “1”, and a non-significant level (a Low level) is indicated by “0”. The high-impedance output state of a pre-stage buffer is indicated by “Hi-Z”.

FIG. 3 is a timing chart illustrating the control signals C 1 to C M , the input signals I 1 to I M , and the output signal (a multiplexed signal) of the output buffer B out . As illustrated in FIG. 3 , the control signals C 1 to C M are signals for which one cycle is MUI (a unit interval). Each of the control signals C 1 to C M is a signal in which a significant level (a High level) of 2 UI and a non-significant level (a Low level) of (M−2)UI are repeated. The control signal C m is a signal that is delayed by (m−1)UI with respect to the control signal C 1 . The unit interval is the unit length of an output signal of the signal-multiplexing device 1 . For example, when the data rate of an output signal is 40 Gb/s, UI is 25 ps.

Exemplary configurations of the generator 2 are described next.

FIG. 4 illustrates an exemplary configuration of a generator 2 that generates control signals C 1 to C 3 (M=3). As illustrated in FIG. 4 , a generator 2 at the time when M=3 includes a latch circuit L 11 , a latch circuit L 12 , and agate circuit GI. The latch circuit L 11 and the latch circuit L 12 are configured, for example, by a D flip-flop circuit.

The latch circuit L 11 receives a clock CLK 1 captured from an input end 2 A and an output signal of the gate circuit G 11 , and latches a value of the output signal of the gate circuit G 11 at a rising timing of the clock CLK 1 . The latched value is output as a control signal C 1 from the latch circuit 11 . The latch circuit L 12 receives the clock CLK 1 and the control signal C 1 serving as an output signal of the latch circuit L 11 , and latches a value of the control signal C 1 at a rising timing of the clock CLK 1 . The latched value is output as the control signal C 2 from the latch circuit L 12 .

The gate circuit G 11 receives the control signal C 1 serving as the output signal of the latch circuit L 11 , and the control signal C 2 serving as an output signal of the latch circuit L 12 , and outputs a signal indicating an NAND of these signals as the control signal C 3 . Stated another way, the latch circuit L 11 receives the control signal C 3 as the output signal of the gate circuit G 11 .

By employing the generator 2 at the time when M=3 that is configured as described above, each of the control signals C 1 to C 3 can be generated in which a significant level of 2 UI and a non-significant level of 1 UI are repeated.

In a configuration at the time when M=4, control signals C 1 to C 4 (M=4) are signals in which a significant level of 2 UI and a non-significant level of 2 UI are repeated, and are signals in which a period of the significant level is equal to a period of the non-significant level. Accordingly, the control signal C 1 and the control signal C 3 have a logic inversion relationship, and the control signal C 2 and the control signal C 4 also have the logic inversion relationship. Therefore, a generator 2 at the time when M=4 can generate each of the control signals C 1 to C 4 , for example, by including a delay circuit that delays a clock and a logic inversion circuit that inverts logic.

FIG. 5 illustrates an exemplary configuration of a generator 2 that generates control signals C 1 to C 5 (M=5). As illustrated in FIG. 5 , a generator 2 at the time when M=5 includes latch circuits L 21 to L 23 and gate circuits G 21 to G 27 . The latch circuits L 21 to L 23 are configured, for example, by a D flip-flop circuit.

The latch circuit L 21 receives a clock CLK 1 captured from an input end 2 A and an output signal of the gate circuit G 26 , and latches a value of the output signal of the gate circuit G 26 at a rising timing of the clock CLK 1 . The latched value is outputted from the latch circuit L 21 . The gate circuit G 21 receives an output signal of the latch circuit L 21 , and outputs a logic inversion signal of this signal as the control signal C 2 .

The latch circuit L 22 receives the clock CLK 1 and an output signal of the latch circuit L 21 , and latches a value of the output signal of the latch circuit L 21 at a rising timing of the clock CLK 1 . The latched value is outputted from the latch circuit L 22 . The gate circuit G 22 receives an output signal of the latch circuit L 22 , and outputs a logic inversion signal of this signal as the control signal C 3 .

The latch circuit L 23 receives the clock CLK 1 and an output signal of the latch circuit L 22 , and latches a value of the output signal of the latch circuit L 22 at a rising timing of the clock CLK 1 . The latched value is outputted from the latch circuit L 23 . The gate circuit G 23 receives an output signal of the latch circuit L 23 , and outputs a logic inversion signal of this signal as the control signal C 4 .

The gate circuit G 24 receives the output signal of the latch circuit L 21 and the output signal of the latch circuit L 22 , and outputs a signal indicating an NAND of these signals. The gate circuit G 25 receives an output signal of the gate circuit G 24 , and outputs a logic inversion signal of this signal as the control signal C 5 . The gate circuit G 26 receives the output signal of the latch circuit L 22 and the output signal of the latch circuit L 23 , and outputs a signal indicating an NAND of these signals. The gate circuit G 27 receives an output signal of the gate circuit G 26 , and outputs a logic inversion signal of this signal as the control signal C 1 .

By employing the generator 2 at the time when M=5 that is configured as described above, each of the control signals C 1 to C 5 can be generated in which a significant level of 2 UI and a non-significant level of 3 UI are repeated.

FIG. 6 illustrates an exemplary configuration of a generator 2 that generates control signals C 1 to C 6 (M=6). As illustrated in FIG. 6 , a generator 2 at the time when M=6 includes a 2-division circuit 3 , latch circuits L 31 to L 35 , and gate circuits G 31 to G 34 . The 2-division circuit 3 includes a latch circuit L 36 and a gate circuit G 35 . The latch circuits L 31 to L 36 are configured, for example, by a D flip-flop circuit.

The latch circuit L 36 receives a clock CLK 1 captured from an input end 2 A and an output signal of the gate circuit G 35 , and latches a value of the output signal of the gate circuit G 35 at a rising timing of the clock CLK 1 . The latched value is output as a clock CLK 2 from the latch circuit L 36 . The clock CLK 2 is a 2-divided signal obtained by 2-dividing the clock CLK 1 . The gate circuit G 35 receives the clock CLK 2 serving as an output signal of the latch circuit L 36 , and outputs a clock CLK 3 as a logic inversion signal of the clock CLK 2 . By employing the 2-division circuit 3 configured as described above, the clock CLK 2 and the clock CLK 3 are generated from the clock CLK 1 .

The latch circuit L 31 receives the clock CLK 2 and an output signal of the gate circuit G 33 , and latches a value of the output signal of the gate circuit G 33 at a rising timing of the clock CLK 2 . The latched value is outputted from the latch circuit L 31 . The gate circuit G 31 receives an output signal of the latch circuit L 31 , and outputs a logic inversion signal of this signal as the control signal C 3 .

The latch circuit L 32 receives the clock CLK 3 and the control signal C 3 serving as an output signal of the gate circuit G 31 , and latches a value of the control signal C 3 at a rising timing of the clock CLK 3 . The latched value is output as the control signal C 4 from the latch circuit L 32 . The latch circuit L 33 receives the clock CLK 2 and the output signal of the latch circuit L 31 , and latches a value of the output signal of the latch circuit L 31 at a rising timing of the clock CLK 2 . The latched value is outputted.

The gate circuit G 32 receives an output signal of the latch circuit L 33 , and outputs a logic inversion signal of this signal as the control signal C 5 . The latch circuit L 34 receives the clock CLK 3 and the control signal C 5 serving as an output signal of the gate circuit G 32 , and latches a value of the control signal C 5 at a rising timing of the clock CLK 3 . The latched value is output as the control signal C 6 from the latch circuit L 34 . The gate circuit G 33 receives the output signal of the latch circuit L 31 and the output signal of the latch circuit L 33 , and outputs a signal indicating an NAND of these signals.

The gate circuit G 34 receives an output signal of the gate circuit G 33 , and outputs a logic inversion signal of this signal as the control signal C 1 . The latch circuit L 35 receives the clock CLK 3 and the control signal C serving as an output signal of the gate circuit G 34 , and latches a value of the control signal C 1 at a rising timing of the clock CLK 3 . The latched value is output as the control signal C 2 from the latch circuit L 35 .

By employing the generator 2 at the time when M=6 that is configured as described above, each of the control signals C 1 to C 6 can be generated in which a significant level of 2 UI and a non-significant level of 4 UI are repeated.

The control signals C 1 to C M are equivalent to M-phase clocks for which a duty ratio is 2/M and a phase is shifted by 2π/M. Therefore, in the generator 2 , any of signals output as the control signals C 1 to C M may be set as the control signal C 1 , and the control signals C 2 to C M may be selected so as to be signals that are delayed by 1 UI to (M−1)UI with respect to the control signal C 1 . Specifically, for example, it has been described above that, in the generator 2 of FIG. 4 at the time when M=3, an output signal of the latch circuit L 11 is the control signal C 1 , an output signal of the latch circuit L 12 is the control signal C 2 , and an output signal of the gate circuit G 11 is the control signal C 3 . However, any of these output signals may be set as the control signal C 1 . The control signal C 2 may be selected so as to be a signal that is delayed by 1 UI with respect to the control signal C 1 . The control signal C 3 may be selected so as to be a signal that is delayed by 2 UI with respect to the control signal C 1 .

In the generator 2 of FIG. 6 at the time when M=6, the clock CLK 2 and the clock CLK 3 are 2-phase clocks, and a rising timing of one of the clock CLK 2 and the clock CLK 3 is identical to a falling timing of the other of the clock CLK 2 and the clock CLK 3 . Accordingly, the generator (of FIG. 6 ) 2 may be configured to generate the clock CLK 2 or the clock CLK 3 by using the 2-division circuit 3 and to latch a value of an input signal at a rising timing and a falling timing of the generated clock by using the latch circuits L 31 to L 35 . Specifically, the latch circuit L 31 and the latch circuit L 33 may be configured to latch a value of an input signal at one of a rising timing and a falling timing of the generated clock, and the latch circuit L 32 , the latch circuit L 34 , and the latch circuit L 35 may be configured to latch the value of the input signal at the other of the rising timing and the falling timing.

The generator 2 illustrated in FIG. 6 may have, for example, a configuration in which the clock CLK 2 and the clock CLK 3 are inputted from the outside. The generator 2 may have a configuration in which the clock CLK 2 or the clock CLK 3 is inputted from the outside and a logic inversion signal of the input clock is generated. Further, the generator 2 may have a configuration in which the clock CLK 2 or the clock CLK 3 is inputted from the outside and a value of an input signal is latched at a rising timing and a falling timing of the input clock.

Exemplary configurations of the m-th pre-stage buffer B m of the M buffers B 1 to B M are described next with reference to FIGS. 7 to 11 .

FIG. 7 illustrates a first exemplary configuration of the pre-stage buffer B m . The pre-stage buffer B m having the first exemplary configuration includes a tri-state buffer 4 and a switch S 41 . The tri-state buffer 4 includes an input end 1 A that captures the input signal I m , input ends 10 A and 10 B that respectively capture the control signals C m and C n , and an output end 10 C that outputs the input signal I m . The tri-state buffer 4 receives the input signal I m and the control signal C m that have been captured via the input end 1 A and the input end 10 A, respectively. When the signal level of the control signal C m is significant, the tri-state buffer 4 outputs a signal that corresponds to the input signal I m . On the other hand, when the signal level of the control signal C m is non-significant, the tri-state buffer 4 enters into a high-impedance output state. The switch S 41 is provided between an output end of the tri-state buffer 4 and an input end of the output buffer B out , and includes a first end that is electrically connected to the output end of the tri-state buffer 4 , and a second end that is electrically connected to the input end of the output buffer B out . In this configuration, the switch S 41 changes a state of electrical connection between the first end and the second end in accordance with the signal level of the control signal C n . Specifically, when the signal level of the control signal C n is significant, the switch S 41 electrically connects the first end and the second end (the ON state). When the signal level of the control signal C n is non-significant, the switch S 41 electrically disconnects the first end and the second end (the OFF state).

The tri-state buffer 4 may have an arbitrary configuration, and the tri-state buffer 4 can have, for example, the exemplary configuration illustrated in FIG. 8 . FIG. 8 illustrates an exemplary configuration of the tri-state buffer 4 in the first exemplary configuration of the pre-stage buffer B m . The tri-state buffer 4 includes a first gate circuit G 41 , a second gate circuit G 42 , and a first-configuration series circuit that is disposed between a first reference end T 1 and a second reference end T 2 . The first reference end T 1 is set to have a first reference potential, and the second reference end T 2 is set to have a second reference potential that is lower than the first reference potential. The first-configuration series circuit is configured by a PMOS transistor T 41 and an NMOS transistor T 42 that are disposed in order from a side of the first reference end T 1 to a side of the second reference end T 2 , and a drain of the PMOS transistor T 41 and a drain of the NMOS transistor T 42 are connected to each other. The first gate circuit G 41 receives the input signal I m and the control signal C m , and outputs a signal indicating an NAND of these signals. The second gate circuit G 42 receives the input signal I m and a logic inversion signal of the control signal C m , and outputs a signal indicating an NOR of these signals.

The PMOS transistor T 41 includes a source that is electrically connected to the first reference end T 1 , a gate that is connected to an output end of the first gate circuit G 41 , and the drain that is electrically connected to the drain of the NMOS transistor T 42 . The NMOS transistor T 42 includes the drain that is electrically connected to the drain of the PMOS transistor T 41 , a gate that is electrically connected to an output end of the second gate circuit G 42 , and a source that is electrically connected to the second reference end T 2 . Further, a connection point of the drain of the PMOS transistor T 41 and the drain of the NMOS transistor T 42 is electrically connected to the switch S 41 .

FIG. 9 illustrates a second exemplary configuration of the pre-stage buffer B m . The pre-stage buffer B m having the second exemplary configuration similarly includes an input end 1 A that captures the input signal I m , input ends 10 A and 10 B that respectively capture the control signals C m and C n , and an output end 10 C that outputs the input signal I m . The pre-stage buffer B m having the second exemplary configuration includes a first gate circuit G 51 , a second gate circuit G 52 , and a second-configuration series circuit that is disposed between a first reference end T 1 and a second reference end T 2 . The second-configuration series circuit is configured by a first buffer switch (hereinafter simply referred to as a “first switch”) S 51 , a PMOS transistor T 51 , an NMOS transistor T 52 , and a second buffer switch (hereinafter simply referred to as a “second switch”) S 52 that are disposed in order from a side of the first reference end T 1 to a side of the second reference end T 2 . The first gate circuit G 51 receives the input signal I m and the control signal C m , and outputs a signal indicating an NAND of these signals. The second gate circuit G 52 receives the input signal I m and a logic inversion signal of the control signal C m , and outputs a signal indicating an NOR of these signals.

The first switch S 51 includes a first end that is electrically connected to the first reference end T 1 , and a second end that is electrically connected to a source of the PMOS transistor T 51 . In addition, the first switch S 51 changes a state of electrical connection between the first end and the second end of the first switch S 51 in accordance with the signal level of the control signal C n . Stated another way, when the signal level of the control signal C n is significant, the first switch S 51 electrically connects the first end and the second end (the ON state). When the signal level of the control signal C n is non-significant, the first switch S 51 electrically disconnects the first end and the second end (the OFF state). The PMOS transistor T 51 includes a source that is electrically connected to the second end of the first switch S 51 , a gate that is connected to an output end of the first gate circuit G 51 , and a drain that is electrically connected to a drain of the NMOS transistor T 52 . The NMOS transistor T 52 includes the drain that is connected to the drain of the PMOS transistor T 51 , a gate that is electrically connected to an output end of the second gate circuit G 52 , and a source that is electrically connected to a first end of the second switch S 52 . The second switch S 52 includes a first end that is electrically connected to the source of the NMOS transistor T 52 , and a second end that is electrically connected to the second reference end T 2 . In addition, the second switch S 52 changes a state of electrical connection between the first end and the second end of the second switch S 52 in accordance with the signal level of the control signal C n . Stated another way, when the signal level of the control signal C n is significant, the second switch S 52 electrically connects the first end and the second end (the ON state). When the signal level of the control signal C n is non-significant, the second switch S 52 electrically disconnects the first end and the second end (the OFF state). Further, a connection point of the drain of the PMOS transistor T 51 and the drain of the NMOS transistor T 52 is connected to the input end of the output buffer B out .

FIG. 10 illustrates a third exemplary configuration of the pre-stage buffer B m . The pre-stage buffer B m having the third exemplary configuration similarly includes an input end 1 A that captures the input signal I m , input ends 10 A and 10 B that respectively capture the control signals C m and C n , and an output end 10 C that outputs the input signal I m . The pre-stage buffer B m having the third exemplary configuration includes a first gate circuit G 61 , a second gate circuit G 62 , and a third-configuration series circuit that is disposed between a first reference end T 1 and a second reference end T 2 . The third-configuration series circuit is configured by a PMOS transistor T 61 , a first switch S 61 , a second switch S 62 , and an NMOS transistor T 62 that are disposed in order from a side of the first reference end T 1 to a side of the second reference end T 2 . The pre-stage buffer B m having the third exemplary configuration further includes a first refresh circuit R 61 that refreshes a potential at a connection point of a drain of the PMOS transistor T 61 and a first end of the first switch S 61 , and a second refresh circuit R 62 that refreshes a potential at a connection point of a drain of the NMOS transistor T 62 and a second end of the second switch S 62 . The first gate circuit G 61 receives the input signal I m and the control signal C m , and outputs a signal indicating an NAND of these signals. The second gate circuit G 62 receives the input signal I m and a logic inversion signal of the control signal C m , and outputs a signal indicating an NOR of these signals.

The PMOS transistor T 61 includes a source that is electrically connected to the first reference end T 1 , a gate that is electrically connected to an output end of the first gate circuit G 61 , and the drain that is electrically connected to the first end of the first switch S 61 . The first switch S 61 includes the first end that is electrically connected to the drain of the PMOS transistor T 61 , and a second end that is electrically connected to a first end of the second switch S 62 . In addition, the first switch S 61 changes a state of electrical connection between the first end and the second end of the first switch S 61 in accordance with the signal level of the control signal C n . Specifically, when the signal level of the control signal C n is significant, the first switch S 61 electrically connects the first end and the second end (the ON state). When the signal level of the control signal C n is non-significant, the first switch S 61 electrically disconnects the first end and the second end (the OFF state). The second switch S 62 includes the first end that is electrically connected to the second end of the first switch S 61 , and the second end that is electrically connected to the drain of the NMOS transistor T 62 . In addition, the second switch S 62 changes a state of electrical connection between the first end and the second end of the second switch S 62 in accordance with the signal level of the control signal C n . Specifically, when the signal level of the control signal C n is significant, the second switch S 62 electrically connects the first end and the second end (the ON state). When the signal level of the control signal C n is non-significant, the second switch S 62 electrically disconnects the first end and the second end (the OFF state). The NMOS transistor T 62 includes the drain that is electrically connected to the second end of the second switch S 62 , a gate that is electrically connected to an output end of the second gate circuit G 62 , and a source that is electrically connected to the second reference end T 2 . Further, a connection point of the second end of the first switch S 61 and the first end of the second switch S 62 is electrically connected to the input end of the output buffer B out .

The first refresh circuit R 61 is provided in parallel to the PMOS transistor T 61 , and includes a first end that is electrically connected to a third reference end T 3 , and a second end that is electrically connected to the connection point of the drain of the PMOS transistor T 61 and the first end of the first switch S 61 . The third reference end T 3 is set to have a third reference potential that is higher than a second reference potential. The second refresh circuit R 62 is provided in parallel to the NMOS transistor T 62 , and includes a first end that is electrically connected to the connection point of the drain of the NMOS transistor T 62 and the second end of the second switch S 62 , and a second end that is electrically connected to a fourth reference end T 4 . The fourth reference end T 4 is set to have a fourth reference potential that is lower than a first reference potential.

FIG. 11 illustrates a fourth exemplary configuration of the pre-stage buffer B m . The pre-stage buffer B m having the fourth exemplary configuration similarly includes an input end 1 A that captures the input signal I m , input ends 10 A and LOB that respectively capture the control signals C m and C n , and an output end 10 C that outputs the input signal I m . The pre-stage buffer B m having the fourth exemplary configuration includes first to fourth gate circuits G 71 to G 74 , and a fourth-configuration series circuit that is disposed between a first reference end T 1 and a second reference end T 2 . The fourth-configuration series circuit is configured by a PMOS transistor T 71 and an NMOS transistor T 72 that are disposed in order from a side of the first reference end to a side of the second reference end, and a drain of the PMOS transistor T 71 and a drain of the NMOS transistor T 72 are connected to each other. The first gate circuit G 71 receives the input signal I m and a logic inversion signal of the control signal C m , and outputs a signal indicating an NOR of these signals. The second gate circuit G 72 receives an output signal of the first gate circuit G 71 and the control signal C n , and outputs a signal indicating an NAND of these signals. The third gate circuit G 73 receives the input signal I m and the control signal C m , and outputs a signal indicating an NAND of these signals. The fourth gate circuit G 74 receives an output signal of the third gate circuit G 73 and a logic inversion signal of the control signal C n , and outputs a signal indicating an NOR of these signals.

The PMOS transistor T 71 includes a source that is electrically connected to the first reference end T 1 , a gate that is connected to an output end of the second gate circuit G 72 , and the drain that is electrically connected to the drain of the NMOS transistor T 72 . The NMOS transistor T 72 includes the drain that is electrically connected to the drain of the PMOS transistor 171 , a gate that is electrically connected to an output end of the fourth gate circuit G 74 , and a source that is electrically connected to the second reference end T 2 . A connection point of the drain of the PMOS transistor T 71 and the drain of the NMOS transistor T 72 is connected to the input end of the output buffer B out .

In each of the exemplary configurations above of the pre-stage buffer B m , each of the switch S 41 , the first switch S 51 , the second switch S 52 , the first switch S 61 , the second switch S 62 , the first refresh circuit R 61 , and the second refresh circuit R 62 can be configured by a single MOS transistor, or can be configured by a transfer gate. Specifically, for example, in the exemplary configuration illustrated in FIG. 9 of the pre-stage buffer B m , the first switch S 51 can be configured by a PMOS transistor that receives the logic inversion signal of the control signal C n , and the second switch S 52 can be configured by an NMOS transistor that receives the control signal C n .

In each of the exemplary configurations above of the pre-stage buffer B m , any signal that has a logic inversion relationship with the control signal C m can be used as the logic inversion signal of the control signal C m , and any signal that has a logic inversion relationship with the control signal C n can be used as the logic inversion signal of the control signal C n . An arbitrary method for generating the logic inversion signal of the control signal C m and the logic inversion signal of the control signal C n can be used.

The pre-stage buffer B m does not need to employ a configuration in which two switches are connected in series. Therefore, a parasitic resistance value and a parasitic capacitance value due to a switch are reduced such that the waveform of an output signal can be prevented from being blunted, and this enables a frequency band to be expanded. Accordingly, the signal-multiplexing device 1 according to the present embodiment is capable of satisfactorily handling an increase in a data rate. The signal-multiplexing device 1 is also capable of mitigating what is called a charge sharing effect. The charge sharing effect is a phenomenon in which a buffer in the high-impedance output state includes a switch in the ON state, and a parasitic capacitance is charged or discharged via the switch such that the waveform of an output signal is blunted.

When the first to fourth exemplary configurations of the pre-stage buffer B m are compared with each other, two gate circuits are driven in the first to third exemplary configurations, and four gate circuits are driven in the fourth exemplary configuration. Therefore, in the first to third exemplary configurations, a driving load can be reduced in comparison with the fourth exemplary configuration. In contrast, the fourth exemplary configuration does not include a switch. Therefore, the fourth exemplary configuration is capable of satisfactorily handling a further increase in a data rate in comparison with the first to third exemplary configurations. In addition, the fourth exemplary configuration is capable of solving the charge sharing effect, whereas the first to third exemplary configurations only mitigate the charge sharing effect.

In the third exemplary configuration, if the first refresh circuit R 61 and the second refresh circuit R 62 are not provided, a potential at a connection point of the PMOS transistor T 61 and the first switch S 61 and a potential at a connection point of the NMOS transistor T 62 and the second switch S 62 depend on the previous level of an input signal, and the potentials may be unstable. Accordingly, in the third exemplary configuration, it is preferable that the first refresh circuit R 61 and the second refresh circuit R 62 be provided. The first exemplary configuration, the second exemplary configuration, and the fourth exemplary configuration do not have a problem of dependency on an input signal pattern, and therefore refresh circuits can be omitted.

The present invention is not limited to the embodiment described above, and various variations can be made. For example, the circuit configuration of each of the pre-stage buffers B 1 to B M and the output buffer B out is not limited to the exemplary configurations described above, and various configurations can be employed.

1 . . . Signal-multiplexing device; 2 . . . Generator, 4 . . . Tri-state buffer; B 1 to B M , B m . . . Pre-stage buffer; B out . . . Output buffer; C 1 to C M , C m , C n . . . Control signal; CLK 1 to CLK 3 . . . Clock; G 31 to G 34 . . . Gate circuit: G 41 , G 51 , G 61 , G 71 . . . First gate circuit; G 42 , G 52 , G 62 , G 72 . . . Second gate circuit; G 73 . . . Third gate circuit; G 74 . . . Fourth gate circuit; I 1 to I M , I m . . . Input signal; L 31 to L 35 . . . Latch circuit; S 41 . . . Switch; S 51 , S 61 . . . First switch; S 52 , S 62 . . . Second switch; T 41 , T 51 , T 61 , T 71 . . . PMOS transistor; T 42 , T 52 , T 62 , T 72 . . . NMOS transistor; R 61 . . . First refresh circuit; R 62 . . . Second refresh circuit; T 1 . . . First reference end; T 2 . . . Second reference end; T 3 . . . Third reference end; and T 4 . . . Fourth reference end.