Compensation of an arc curvature generated in a wafer

The present invention relates to a method and structure for performing compensation of bow generated in a wafer made from a material, in particular of semiconductor type.

Bow has been defined in the standard ASTM F534, § 3.1.2. As illustrated in FIG. 1 , a wafer 1 presents:

a front surface 10 and an opposite rear surface 11 ; a median surface S m defined as the set of points equidistant from the front and rear surfaces 10 , 11 when wafer 1 is free from clamping.

Bow B w , is the distance between the centre C of the median surface S m and a reference plane P ref . Reference plane P ref is defined by three points located uniformly around a circle of smaller diameter than the nominal diameter of wafer 1 . Bow B w is positive or negative depending on whether centre C is above or below reference plane P ref .

Bow can be generated when a layer is formed on the wafer at a given temperature, the layer having a much higher, or much lower, coefficient of thermal expansion CTE than that of the wafer at a given temperature. This effect is called bimetal effect.

For non-restrictive example purposes, an envisaged application is epitaxy of GaN on a silicon wafer at 1050° C. for fabrication of light-emitting diodes. When the wafer presents a diameter of 200 mm, the person skilled in the art preferentially seeks to obtain a bow of less than 200 μm in absolute value, A bow of more than 200 μm is liable to give rise to defects, such as cracking or delamination, that are detrimental for the subsequent steps e.g. photolithography, robotized handling of the wafer etc.

To compensate bow, it is known from the state of the art to form two metallic layers (or two dielectric layers) on the front and rear surfaces of the wafer. This method is in particular known for power component transfer applications.

It is also known from the state of the art, in particular from the document JP 2002134451, to form unfilled trenches on the front surface of the wafer to compensate warp of the wafer. The trenches are formed before grinding of the rear surface of the wafer. The trenches define a cutting path of the wafer.

It should be noted that warp differs from the bow defined in the foregoing. Warp has been defined in the ASTM F1390 standard. As illustrated in FIG. 2 , a wafer 1 presents:

a front surface 10 and an opposite rear surface 11 ; a median surface S m defined as the set of points equidistant from the front and rear surfaces 10 , 11 when wafer 1 is free from clamping.

A reference plane P ref also exists defined by three points located uniformly around a circle of smaller diameter than the nominal diameter of wafer 1 .

Warp W p is defined by the relation W p =D max,H −D max,B where:

D max,H is the maximum distance between the median surface S m and the reference plane, taken above the reference plane P ref ; D max,B is the maximum distance between the median surface S m and the reference plane, taken below the reference plane P ref .

Warp W p is always a positive number in so far as D max,B is a negative number by definition and method of calculation.

Such state-of-the-art methods are not entirely satisfactory in so far as they do not ensure a sufficiently small bow of the wafer (for example less than 200 μm in absolute value for a wafer diameter of 200 mm) when formation of a layer is performed at high temperature (for example about 1000° C.).

Accordingly, the object of the present invention is to either wholly or partially remedy the above-mentioned shortcomings, and relates for this purpose to a method for compensating bow generated in a wafer made from a material, the wafer comprising opposite first and second surfaces, the material of the wafer having a coefficient of thermal expansion, called CTE and noted α 0 ; the method comprising the steps of:

a) forming a set of first trenches on the first surface of the wafer;

b) forming a set of second trenches on the second surface of the wafer, at least partially facing the first trenches;

c) filling the first trenches with a first material having a CTE α 1 ;

d) filling the second trenches with a second material having a CTE α 2 , and verifying α 2 >α 0 or α 2 <α 0 depending on whether the first material verifies α 1 >α 0 or α 1 <α 0 .

Accordingly, such a method according to the invention enables bow to be compensated by anticipation, i.e. before a step generating the bow, such as formation of a layer on the first surface of the wafer at high temperature.

In order to do this, the first trenches are filled with a first material different from the material of the wafer (α 1 ≠α 0 ), and second trenches are formed at least partially facing the first trenches. The second trenches are advantageously formed totally facing the first trenches, preferentially with a symmetry with respect to the longitudinal median plane of the wafer. The second trenches are filled with a second material that is able to be identical to the first material (α 1 =α 2 ), The choice of α 2 is such that:

α 2 >α 0 if α 1 >α 0 ,

α 2 <α 0 if α 1 <α 0 ,

in order to obtain compensation of the bow.

The first material—called filling material—can comprise a set of N layers (N being a natural integer greater than or equal to 2) of different materials filling the first trenches. In this case, the CTE of the first material α 1 is calculated in the following manner:

where:

α 1i is the CTE of the material of the i-th layer, v i is the volumetric fraction of the material of the i-th layer inside the first trenches.

In the same way, the second material—called filling material—can comprise a set of N layers (N being a natural integer greater than or equal to 2) of different materials filling the second trenches. In this case, the CTE of the second material α 2 is calculated in the following manner:

where:

α 2i is the CTE of the material of the i-th layer, v i is the volumetric fraction of the material of the i-th layer inside the second trenches.

Advantageously, the first and second materials respectively occupy a first volume V 1 and a second volume V 2 inside the first and second trenches on completion of steps c) and d); and step d) is executed such that

In this way, such filling volumes enable compensation of the bow to be improved.

Advantageously, the first and second trenches respectively present a first form factor Φ 1 and a second form factor Φ 2 during steps a) and b), defined as the ratio between the width and depth of the corresponding trenches; and step b) is executed in such a way that Φ 2 =Φ 1 ±20%, preferably Φ 2 =Φ 1 ±15%, more preferentially Φ 2 =Φ 1 ±10%.

In this way, such form factors enable compensation of the bow to be improved.

Advantageously, step a) is executed in such a way that the first trenches define a cutting path of the wafer, and step b) is preferentially executed in such a way that the second trenches are totally facing the first trenches.

It is thus possible to enhance the cutting path in order to compensate the bow.

Advantageously, the method comprises a step a 1 ) consisting in coating the first trenches with a dielectric layer before step c), the dielectric layer preferentially being an oxide layer.

Such a dielectric layer thus enables the first trenches to be electrically insulated from the wafer.

Advantageously, the method comprises a step b 1 ) consisting in coating the second trenches with a dielectric layer before step d), the dielectric layer preferentially being an oxide layer.

Such a dielectric layer thus enables the second trenches to be electrically insulated from the wafer.

Advantageously, steps a 1 ) and b 1 ) are concomitant.

The operation time of the method is thereby reduced.

Advantageously, step d) is executed in such a way that the second material is identical to the first material, steps c) and d) preferably being concomitant.

Implementation of the method is thus simplified and the operation time is greatly reduced. Steps c) and d) are for example concomitant when the first and second materials are thermal oxides,

Advantageously, the method comprises:

a step c 1 ) consisting in planarizing the first material so as to be flush with the first surface after step c); and preferably

a step d 1 ) consisting in planarizing the second material so as to be flush with the second surface after step d).

Presence of the first material outside the first trenches is thus avoided, in particular on the first surface of the wafer, in active areas for future components.

Steps c 1 ) and d 1 ) are preferentially performed by chemical mechanical polishing.

Preferentially, the first and second materials are selected from the group comprising polycrystalline silicon, a polyimide, a polyepoxide, an acrylic, an oxide, a nitride, and a glass.

Preferentially, the material of the wafer is selected from the group comprising a semiconductor material, a ceramic, a glass, and sapphire; the semiconductor material preferably being silicon-based.

The present invention also relates to a structure for performing compensation of bow, comprising:

a wafer made from a material, comprising opposite first and second surfaces, the wafer material having a coefficient of thermal expansion, called CTE and noted α 0 ; a set of first trenches formed on the first surface and filled with a first material having a CTE α 1 ; a set of second trenches formed on the second surface, at least partially facing the first trenches, and filled with a second material having a CTE α 2 , and verifying α 2 >α 0 or α 2 <α 0 depending on whether the first material verifies α 1 >α 0 or α 1 <α 0 .

Such a structure according to the invention thereby enables bow to be compensated by anticipation, i.e. before a step generating the bow, such as formation of a layer on the first surface of the wafer at high temperature.

To do this, the first trenches are filled with a first material different from the material of the wafer (α 1 ≠α 0 ) and second trenches are formed at least partially facing the first trenches. The second trenches are advantageously formed totally facing the first trenches, preferentially with an axial symmetry. The second trenches are filled with a second material that is able to be identical to the first material (a 1 =a 2 ). The choice of α 2 is such that:

α 2 >α 0 if α 1 >α 0 ,

α 2 <α 0 if α 1 <α 0 ,

in order to obtain compensation of the bow.

The first material—called filling material—can comprise a set of N layers (N being a natural integer greater than or equal to 2) of different materials filling the first trenches. In this case, the CTE of the first material α 1 is calculated in the following manner:

where:

α 1i is the CTE of the material of the i-th layer,

v i is the volumetric fraction of the material of the i-th layer inside the first trenches.

In the same way, the second material—called filling material—can comprise a set of N layers (N being a natural integer greater than or equal to 2) of different materials filling the second trenches. In this case, the CTE of the second material α 2 is calculated in the following manner:

where:

α 2i is the CTE of the material of the i-th layer, v i is the volumetric fraction of the material of the i-th layer inside the second trenches.

Advantageously, the first and second materials respectively occupy a first volume V 1 and a second volume V 2 inside the first and second trenches, and verifying

In this way, such filling volumes enable compensation of the bow to be improved.

Advantageously, the first and second trenches respectively present a first form factor Φ 1 and a second form factor Φ 2 defined as the ratio between the width and depth of the corresponding trenches; and verifying Φ 2 =Φ 1 ±20%, preferably Φ 2 =Φ 1 ±15%, more preferentially Φ 2 =Φ 1 ±10%.

In this way, such form factors enable compensation of the bow to be improved.

Advantageously, the first trenches are coated with a dielectric layer inserted between the wafer material and the first material; and the second trenches are preferably coated with a dielectric layer inserted between the wafer material and the second material.

Such dielectric layers thus enable the first and second trenches to be electrically insulated from the wafer.

Advantageously, the first material is flush with the first surface; and preferably the second material is flush with the second surface.

Presence of the first material outside the first trenches is thus avoided, in particular on the first surface of the wafer, in active areas for future components.

Other features and advantages will become more clearly apparent from the following description of different embodiments of the invention, given for non-restrictive example purposes, with reference to the appended drawings, in which:

FIG. 1 (already described) is a schematic cross-sectional view of a wafer sustaining a bow;

FIG. 2 (already described) is a schematic cross-sectional view of a wafer sustaining a warp;

FIGS. 3 to 5 are schematic cross-sectional views illustrating steps of a method according to the invention.

For the different embodiments, the technical features described hereafter are to be considered either alone or in any technically possible combination; the same reference numerals are used for parts that are identical or perform the same function, for the sake of simplification of the description.

What is meant by “wafer” is:

a sliced part of a semiconductor material ingot, conventionally a disc, used as base material to form components, or more generally a preferably self-supported substrate of a material (e.g. a ceramic, a glass, sapphire).

What is meant by “semiconductor” is that the material presents an electric conductivity at 300 K comprised between 10 −8 S/cm and 10 3 S/cm.

What is meant by “dielectric” is that the material presents an electric conductivity at 300 K of less than 10 −8 S/cm.

What is meant by “longitudinal” is a direction perpendicular to the normal to the first and second surfaces of the wafer.

The method illustrated in FIGS. 1 to 3 is a method for performing compensation of bow generated in a wafer 1 made from a material, wafer 1 comprising opposite first and second surfaces 10 , 11 , the material of wafer 1 having a coefficient of thermal expansion, called CTE and noted α 0 ; the method comprising the steps of;

a) forming a set of first trenches 100 a , 100 b on the first surface 10 of wafer 1 ;

b) forming a set of second trenches 110 on the second surface 11 of wafer 1 , at least partially facing first trenches 100 a , 100 b;

c) filling first trenches 100 a , 100 b with a first material M 1 having a CTE α 1 ;

d) filling second trenches 110 with a second material M 2 having a CTE α 2 , and verifying α 2 >α 0 or α 2 <α 0 depending on whether first material M 1 verifies α 1 >α 0 or α 1 <α 0 .

Wafer

The material of wafer 1 is preferentially selected from the group comprising a semiconductor material, a ceramic, a glass, or sapphire. The semiconductor material of wafer 1 is preferentially silicon-based. For example purposes, α 0 (Si)=2.5×10 −6 K −1 at 300 K. The silicon is advantageously doped so that wafer 1 presents a resistivity of less than 1 ohm.cm, preferentially less than 10 −2 ohm.cm.

First trenches

First trenches 100 a , 100 b preferentially comprise primary first trenches 100 a and secondary first trenches 100 b . Step a) is advantageously executed in such a way that primary first trenches 100 a define a cutting path of wafer 1 . Secondary first trenches 100 b are advantageously arranged to electrically insulate electronic components 4 from first surface 10 of wafer 1 . Primary first trenches 100 a are deeper than secondary first trenches 100 b . As illustrated in FIG. 3 , first trenches 100 a , 100 b are formed during step a) preferentially by previously depositing a hard mask 2 and a photoresist 3 on first surface 10 of wafer 1 . Then first trenches 100 a , 100 b are formed during step a) by photolithography and etching steps.

First material M 1 occupies a first volume V 1 inside first trenches 100 a , 100 b on completion of step c), The method advantageously comprises a step c 1 ) consisting in planarizing first material M 1 so as to be flush with first surface 10 after step c). Step c 1 ) is preferentially performed by chemical mechanical polishing.

First material M 1 is advantageously selected from the group comprising polycrystalline silicon, a polyimide, a polyepoxide, an acrylic, an oxide, a nitride, and a glass.

First trenches 100 a , 100 b present a first form factor Φ 1 in step a). Φ 1 is defined as the ratio between the width I 1 and depth H 1 of the corresponding first trenches 100 a , 100 b.

The method advantageously comprises a step a 1 ) consisting in coating first trenches 100 a , 100 b with a dielectric layer 101 before step c). Dielectric layer 101 is preferentially an oxide layer, such as SiO 2 when the semiconductor material of wafer 1 is Si-based. The oxide layer is preferentially a thermal oxide. First material M 1 can be identical to dielectric layer 101 . For example, a (SiO 2 )=0.6×10 −6 K −1 at 300 K. However, for certain applications, first trenches 100 a , 100 b present a depth H 1 comprised between 50 μm and 100 μm; filling of the latter with a thermal oxide would result in a very long operation time and in a low mechanical strength with temperature. It may therefore be preferable to use a different first material M 1 from SiO 2 , such as polycrystalline silicon for certain applications.

Second trenches

Second trenches 110 are formed during step b) preferentially by previously depositing a hard mask 2 and a photoresist 3 on second surface 11 of wafer 1 . Then second trenches 110 are formed in step b) by photolithography and etching steps.

Step b) is preferentially executed in such a way that at least one second trench 110 of the set of second trenches 110 is totally facing at least one first trench 100 a , 100 b . Step b) is advantageously executed in such a way that second trenches 110 are at least partially, preferably totally, facing primary first trenches 100 a , as illustrated in FIG. 4 , Step b) can also be executed in such a way that second trenches 110 are at least partially, preferably totally, facing primary first trenches 100 a and secondary first trenches 100 b . Implementation of steps a) and b) is particularly simplified when second trenches 110 are facing primary first trenches 100 a , or even primary first trenches 100 a and secondary first trenches 100 b , in so far as it is possible to use the same mask alignment for their formation. Wafer 1 presents a longitudinal median plane. Second trenches 110 and primary first trenches 100 a are advantageously symmetrical with respect to the longitudinal median plane. Second trenches 110 and primary first trenches 100 a and secondary first trenches 100 b are advantageously symmetrical relatively to the longitudinal median plane.

Second material M 2 occupies a second volume V 2 inside second trenches 110 on completion of step d). The method advantageously comprises a step d 1 ) consisting in planarizing second material M 2 so as to be flush with second surface 11 after step d), Step d 1 ) is preferentially performed by chemical mechanical polishing.

Second material M 2 is advantageously selected from the group comprising polycrystalline silicon, a polyimide, a polyepoxide, an acrylic, an oxide, a nitride, and a glass. Second material M 2 is advantageously identical to first material M 1 so that steps c) and d) can be concomitant.

V 2 = V 1 ×  α 0 - α 1   α 0 - α 2  .

Calculation can be performed using Stoney's formula.

Second trenches 110 present a first form factor Φ 2 in steps b). Φ 2 is defined as the ratio between the width I 2 and the depth H 2 of the corresponding second trenches 110 . Step b) is advantageously executed in such a way that Φ 2 =Φ 1 ±20%, preferably Φ 2 =Φ 1 ±15%, more preferentially Φ 2 =Φ 1 ±10%.

The method advantageously comprises a step b 1 ) consisting in coating second trenches 110 with a dielectric layer 111 before step d). Dielectric layer 111 is preferentially an oxide layer such as SiO 2 when the semiconductor material of wafer 1 is Si-based. The oxide layer is preferentially a thermal oxide. When dielectric layers 101 , 111 are thermal oxides, steps a 1 ) and b 1 ) are advantageously concomitant. Second material M 2 can be identical to dielectric layer 111 . For example purposes, α (SiO 2 )=0.6×10 −6 K −1 at 300 K. However, for certain applications, second trenches 110 present a depth H 2 comprised between 50 μm and 100 μm; filling of the latter with a thermal oxide would result in a very long operation time and a low mechanical strength with temperature. It may therefore be preferable to use a different second material M 2 from SiO 2 , such as polycrystalline silicon for certain applications.

Simulations enable it to be observed that the parameters (α 2 , V 2 , Φ 2 ) defined according to the invention optimize compensation of the bow.

Application Example

On completion of the method according to the invention, it is possible to form components 4 , such as light-emitting diodes, on first surface 10 of wafer 1 . The light-emitting diodes can be formed by epitaxy of GaN, at a temperature of 1050° C. The light-emitting diodes are then preferentially coated with a protective substrate (or support substrate called handle) assembled on first surface 10 of wafer 1 by bonding. The handle can be temporary or permanent. This results in temporary or permanent bonding. The protective substrate is made from a material preferentially selected from the group comprising a glass, silicon, quartz, and sapphire. More generally, any rigid substrate, transparent in the emission spectrum of the light-emitting diodes, can be suitable for use as protective substrate. Then second surface 11 of wafer 1 is thinned until first trenches 110 are reached. Thinned second surface 11 will then be metallized for the contact connections.

Other applications can naturally be envisaged such as:

microfluidics applications when the material of wafer 1 is a glass, hybrid microelectronics applications when the material of wafer 1 is a ceramic.